Lines Matching defs:pdc_state

277 struct pdc_state {  struct
279 	u8 pdc_idx;
282 	struct platform_device *pdev;
289 	struct mbox_controller mbc;
291 	unsigned int pdc_irq;
294 	struct work_struct rx_work;
297 	u32 rx_status_len;
299 	bool use_bcm_hdr;
301 	u32 pdc_resp_hdr_len;
304 	void __iomem *pdc_reg_vbase;
307 	struct dma_pool *ring_pool;
310 	struct dma_pool *rx_buf_pool;
316 	struct pdc_ring_alloc tx_ring_alloc;
317 	struct pdc_ring_alloc rx_ring_alloc;
319 	struct pdc_regs *regs;    /* start of PDC registers */
321 	struct dma64_regs *txregs_64; /* dma tx engine registers */
322 	struct dma64_regs *rxregs_64; /* dma rx engine registers */
328 	struct dma64dd   *txd_64;  /* tx descriptor ring */
329 	struct dma64dd   *rxd_64;  /* rx descriptor ring */
332 	u32      ntxd;       /* # tx descriptors */
333 	u32      nrxd;       /* # rx descriptors */
334 	u32      nrxpost;    /* # rx buffers to keep posted */
335 	u32      ntxpost;    /* max number of tx buffers that can be posted */
342 	u32  txin;
350 	u32  tx_msg_start;
353 	u32  txout;
359 	u32      txin_numd[PDC_RING_ENTRIES];
365 	u32  rxin;
373 	u32  rx_msg_start;
380 	u32  last_rx_curr;
383 	u32  rxout;
385 	struct pdc_rx_ctx rx_ctx[PDC_RING_ENTRIES];
392 	struct scatterlist *src_sg[PDC_RING_ENTRIES];
395 	u32  pdc_requests;     /* number of request messages submitted */
396 	u32  pdc_replies;      /* number of reply messages received */
397 	u32  last_tx_not_done; /* too few tx descriptors to indicate done */
398 	u32  tx_ring_full;     /* unable to accept msg because tx ring full */
399 	u32  rx_ring_full;     /* unable to accept msg because rx ring full */
423 	struct pdc_state *pdcs;  in pdc_debugfs_read()  argument