Lines Matching +full:0 +full:xb000
19 #define LPG_SUBTYPE_REG 0x05
20 #define LPG_SUBTYPE_LPG 0x2
21 #define LPG_SUBTYPE_PWM 0xb
22 #define LPG_SUBTYPE_HI_RES_PWM 0xc
23 #define LPG_SUBTYPE_LPG_LITE 0x11
24 #define LPG_PATTERN_CONFIG_REG 0x40
25 #define LPG_SIZE_CLK_REG 0x41
26 #define PWM_CLK_SELECT_MASK GENMASK(1, 0)
28 #define PWM_CLK_SELECT_HI_RES_MASK GENMASK(2, 0)
30 #define LPG_PREDIV_CLK_REG 0x42
32 #define PWM_FREQ_EXP_MASK GENMASK(2, 0)
33 #define PWM_TYPE_CONFIG_REG 0x43
34 #define PWM_VALUE_REG 0x44
35 #define PWM_ENABLE_CONTROL_REG 0x46
36 #define PWM_SYNC_REG 0x47
37 #define LPG_RAMP_DURATION_REG 0x50
38 #define LPG_HI_PAUSE_REG 0x52
39 #define LPG_LO_PAUSE_REG 0x54
40 #define LPG_HI_IDX_REG 0x56
41 #define LPG_LO_IDX_REG 0x57
42 #define PWM_SEC_ACCESS_REG 0xd0
43 #define PWM_DTEST_REG(x) (0xe2 + (x) - 1)
45 #define SDAM_REG_PBS_SEQ_EN 0x42
46 #define SDAM_PBS_TRIG_SET 0xe5
47 #define SDAM_PBS_TRIG_CLR 0xe6
49 #define TRI_LED_SRC_SEL 0x45
50 #define TRI_LED_EN_CTL 0x46
51 #define TRI_LED_ATC_CTL 0x47
53 #define LPG_LUT_REG(x) (0x40 + (x) * 2)
54 #define RAMP_CONTROL_REG 0xc8
64 #define RAMP_STEP_DURATION(x) (((x) * 1000 / DEFAULT_TICK_DURATION_US) & 0xff)
68 #define SDAM_START_BASE 0x40
69 #define SDAM_REG_RAMP_STEP_DURATION 0x47
71 #define SDAM_LUT_SDAM_LUT_PATTERN_OFFSET 0x45
72 #define SDAM_LPG_SDAM_LUT_PATTERN_OFFSET 0x80
75 #define SDAM_LUT_EN_OFFSET 0x0
76 #define SDAM_PATTERN_CONFIG_OFFSET 0x1
77 #define SDAM_END_INDEX_OFFSET 0x3
78 #define SDAM_START_INDEX_OFFSET 0x4
79 #define SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET 0x6
80 #define SDAM_PAUSE_HI_MULTIPLIER_OFFSET 0x8
81 #define SDAM_PAUSE_LO_MULTIPLIER_OFFSET 0x9
145 * @dtest_line: DTEST line for output, or 0 if disabled
251 #define PBS_SW_TRIG_BIT BIT(0)
255 u8 val = 0; in lpg_clear_pbs_trigger()
259 return 0; in lpg_clear_pbs_trigger()
264 if (rc < 0) in lpg_clear_pbs_trigger()
270 if (rc < 0) in lpg_clear_pbs_trigger()
275 return 0; in lpg_clear_pbs_trigger()
284 return 0; in lpg_set_pbs_trigger()
288 if (rc < 0) in lpg_set_pbs_trigger()
293 if (rc < 0) in lpg_set_pbs_trigger()
297 if (rc < 0) in lpg_set_pbs_trigger()
303 return 0; in lpg_set_pbs_trigger()
311 return 0; in lpg_sdam_configure_triggers()
320 return 0; in triled_set()
340 idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size, 0, len, 0); in lpg_lut_store_sdam()
344 for (i = 0; i < len; i++) { in lpg_lut_store_sdam()
355 if (rc < 0) in lpg_lut_store_sdam()
364 return 0; in lpg_lut_store_sdam()
375 0, len, 0); in lpg_lut_store()
379 for (i = 0; i < len; i++) { in lpg_lut_store()
391 return 0; in lpg_lut_store()
408 return 0; in lpg_lut_sync()
413 static const unsigned int lpg_clk_rates[] = {0, 1024, 32768, 19200000};
414 static const unsigned int lpg_clk_rates_hi_res[] = {0, 1024, 32768, 19200000, 76800000};
421 unsigned int i, pwm_resolution_count, best_pwm_resolution_sel = 0; in lpg_calc_freq()
423 unsigned int clk_sel, clk_len, best_clk = 0; in lpg_calc_freq()
424 unsigned int div, best_div = 0; in lpg_calc_freq()
425 unsigned int m, best_m = 0; in lpg_calc_freq()
430 u64 best_period = 0; in lpg_calc_freq()
443 * M = [0..7]. in lpg_calc_freq()
465 min_period = div64_u64((u64)NSEC_PER_SEC * ((1 << pwm_resolution_arr[0]) - 1), in lpg_calc_freq()
485 for (i = 0; i < pwm_resolution_count; i++) { in lpg_calc_freq()
490 for (div = 0; div < ARRAY_SIZE(lpg_pre_divs); div++) { in lpg_calc_freq()
523 return 0; in lpg_calc_freq()
587 LPG_ENABLE_GLITCH_REMOVAL, 0); in lpg_enable_glitch()
614 #define LPG_PATTERN_CONFIG_PAUSE_LO BIT(0)
621 u8 val = 0, conf = 0, lut_offset = 0; in lpg_sdam_apply_lut_control()
664 unsigned int conf = 0; in lpg_apply_lut_control()
725 #define LPG_SYNC_PWM BIT(0)
744 return 0; in lpg_parse_dtest()
745 } else if (count < 0) { in lpg_parse_dtest()
754 for (i = 0; i < lpg->data->num_channels; i++) { in lpg_parse_dtest()
768 return 0; in lpg_parse_dtest()
781 regmap_write(lpg->map, chan->base + PWM_SEC_ACCESS_REG, 0xa5); in lpg_apply_dtest()
805 unsigned int triled_enabled = 0; in lpg_brightness_set()
806 unsigned int triled_mask = 0; in lpg_brightness_set()
807 unsigned int lut_mask = 0; in lpg_brightness_set()
812 for (i = 0; i < led->num_channels; i++) { in lpg_brightness_set()
868 return 0; in lpg_brightness_single_set()
884 return 0; in lpg_brightness_mc_set()
892 unsigned int triled_mask = 0; in lpg_blink_set()
905 for (i = 0; i < led->num_channels; i++) { in lpg_blink_set()
922 chan = led->channels[0]; in lpg_blink_set()
927 return 0; in lpg_blink_set()
969 unsigned int hi_pause = 0; in lpg_pattern_set()
970 unsigned int lo_pause = 0; in lpg_pattern_set()
1001 for (i = 0; i < len; i += 2) { in lpg_pattern_set()
1004 if (led_pattern[i + 1].delta_t != 0) in lpg_pattern_set()
1045 for (i = 0; i < len / 2; i++) { in lpg_pattern_set()
1089 lo_pause = pattern[0].delta_t; in lpg_pattern_set()
1092 if (delta_t != pattern[0].delta_t || delta_t != pattern[actual_len - 1].delta_t) in lpg_pattern_set()
1104 if (ret < 0) in lpg_pattern_set()
1107 for (i = 0; i < led->num_channels; i++) { in lpg_pattern_set()
1137 if (ret < 0) in lpg_pattern_single_set()
1142 return 0; in lpg_pattern_single_set()
1151 unsigned int triled_mask = 0; in lpg_pattern_mc_set()
1154 for (i = 0; i < led->num_channels; i++) in lpg_pattern_mc_set()
1156 triled_set(led->lpg, triled_mask, 0); in lpg_pattern_mc_set()
1159 if (ret < 0) in lpg_pattern_mc_set()
1165 return 0; in lpg_pattern_mc_set()
1176 chan = led->channels[0]; in lpg_pattern_clear()
1179 for (i = 0; i < led->num_channels; i++) { in lpg_pattern_clear()
1181 lpg_sdam_configure_triggers(chan, 0); in lpg_pattern_clear()
1183 chan->pattern_lo_idx = 0; in lpg_pattern_clear()
1184 chan->pattern_hi_idx = 0; in lpg_pattern_clear()
1189 return 0; in lpg_pattern_clear()
1217 return chan->in_use ? -EBUSY : 0; in lpg_pwm_request()
1225 * - A disabled channel outputs a logical 0.
1232 int ret = 0; in lpg_pwm_apply()
1241 if (ret < 0) in lpg_pwm_apply()
1250 triled_set(lpg, chan->triled_mask, chan->enabled ? chan->triled_mask : 0); in lpg_pwm_apply()
1299 state->period = 0; in lpg_pwm_get_state()
1300 state->duty_cycle = 0; in lpg_pwm_get_state()
1313 return 0; in lpg_pwm_get_state()
1327 lpg->pwm = chip = devm_pwmchip_alloc(lpg->dev, lpg->num_channels, 0); in lpg_add_pwm()
1357 if (ret < 0 && ret != -EINVAL) in lpg_parse_channel()
1365 return 0; in lpg_parse_channel()
1376 u32 color = 0; in lpg_add_led()
1381 if (ret < 0 && ret != -EINVAL) in lpg_add_led()
1401 i = 0; in lpg_add_led()
1404 if (ret < 0) in lpg_add_led()
1408 info[i].intensity = 0; in lpg_add_led()
1425 ret = lpg_parse_channel(lpg, np, &led->channels[0]); in lpg_add_led()
1426 if (ret < 0) in lpg_add_led()
1479 for (i = 0; i < data->num_channels; i++) { in lpg_init_channels()
1491 return 0; in lpg_init_channels()
1501 return 0; in lpg_init_triled()
1516 regmap_write(lpg->map, lpg->triled_base + TRI_LED_ATC_CTL, 0); in lpg_init_triled()
1523 regmap_write(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, 0); in lpg_init_triled()
1525 return 0; in lpg_init_triled()
1533 return 0; in lpg_init_lut()
1543 return 0; in lpg_init_lut()
1549 u8 val = 0; in lpg_init_sdam()
1552 if (sdam_count <= 0) in lpg_init_sdam()
1553 return 0; in lpg_init_sdam()
1577 for (i = 0; i < lpg->num_channels; i++) { in lpg_init_sdam()
1583 if (rc < 0) in lpg_init_sdam()
1586 rc = lpg_sdam_configure_triggers(chan, 0); in lpg_init_sdam()
1587 if (rc < 0) in lpg_init_sdam()
1591 if (rc < 0) in lpg_init_sdam()
1596 return 0; in lpg_init_sdam()
1621 if (ret < 0) in lpg_probe()
1625 if (ret < 0) in lpg_probe()
1629 if (ret < 0) in lpg_probe()
1633 if (ret < 0) in lpg_probe()
1637 if (ret < 0) in lpg_probe()
1646 for (i = 0; i < lpg->num_channels; i++) in lpg_probe()
1653 .lut_base = 0xb000,
1656 .triled_base = 0xd000,
1662 { .base = 0xb100, .triled_mask = BIT(5) },
1663 { .base = 0xb200, .triled_mask = BIT(6) },
1664 { .base = 0xb300, .triled_mask = BIT(7) },
1665 { .base = 0xb400 },
1672 { .base = 0xbc00 },
1677 .lut_base = 0xb000,
1680 .triled_base = 0xd000,
1686 { .base = 0xb100 },
1687 { .base = 0xb200 },
1688 { .base = 0xb300 },
1689 { .base = 0xb400 },
1690 { .base = 0xb500, .triled_mask = BIT(5) },
1691 { .base = 0xb600, .triled_mask = BIT(6) },
1692 { .base = 0xb700, .triled_mask = BIT(7) },
1693 { .base = 0xb800 },
1700 { .base = 0xb000 },
1705 .lut_base = 0xb000,
1710 { .base = 0xb100 },
1711 { .base = 0xb200 },
1712 { .base = 0xb300 },
1713 { .base = 0xb400 },
1714 { .base = 0xb500 },
1715 { .base = 0xb600 },
1721 .triled_base = 0xd000,
1727 { .base = 0xb300, .triled_mask = BIT(7), .sdam_offset = 0x48 },
1728 { .base = 0xb400, .triled_mask = BIT(6), .sdam_offset = 0x56 },
1729 { .base = 0xb500, .triled_mask = BIT(5), .sdam_offset = 0x64 },
1730 { .base = 0xb600 },
1731 { .base = 0xb700 },
1736 .lut_base = 0xb000,
1739 .triled_base = 0xd000,
1745 { .base = 0xb100, .triled_mask = BIT(5) },
1746 { .base = 0xb200, .triled_mask = BIT(6) },
1747 { .base = 0xb300, .triled_mask = BIT(7) },
1748 { .base = 0xb400 },
1753 .lut_base = 0xb000,
1756 .triled_base = 0xd000,
1760 { .base = 0xb100 },
1761 { .base = 0xb200 },
1762 { .base = 0xb300, .triled_mask = BIT(5) },
1763 { .base = 0xb400, .triled_mask = BIT(6) },
1764 { .base = 0xb500, .triled_mask = BIT(7) },
1765 { .base = 0xb600 },
1770 .lut_base = 0xb000,
1773 .triled_base = 0xd000,
1777 { .base = 0xb100, .triled_mask = BIT(7) },
1778 { .base = 0xb200, .triled_mask = BIT(6) },
1783 .lut_base = 0xb000,
1786 .triled_base = 0xd000,
1790 { .base = 0xb100, .triled_mask = BIT(7) },
1791 { .base = 0xb200, .triled_mask = BIT(6) },
1792 { .base = 0xb300, .triled_mask = BIT(5) },
1793 { .base = 0xbc00 },
1794 { .base = 0xbd00 },
1800 .triled_base = 0xef00,
1806 { .base = 0xe800, .triled_mask = BIT(7), .sdam_offset = 0x48 },
1807 { .base = 0xe900, .triled_mask = BIT(6), .sdam_offset = 0x56 },
1808 { .base = 0xea00, .triled_mask = BIT(5), .sdam_offset = 0x64 },
1809 { .base = 0xeb00 },
1816 { .base = 0xe800 },
1817 { .base = 0xe900 },