1 // SPDX-License-Identifier: GPL-2.0-only
36 #define REG_EDGE_POL_EDGE(params, x)	BIT((params)->edge_single_offset + (x))
37 #define REG_EDGE_POL_LOW(params, x)	BIT((params)->pol_low_offset + (x))
38 #define REG_BOTH_EDGE(params, x)	BIT((params)->edge_both_offset + (x))
186 	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
187 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
188 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
189 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
190 	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
191 	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
192 	{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
193 	{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
194 	{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
195 	{ .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
196 	{ .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
197 	{ .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
198 	{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
199 	{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
217 	raw_spin_lock_irqsave(&ctl->lock, flags);  in meson_gpio_irq_update_bits()
219 	tmp = readl_relaxed(ctl->base + reg);  in meson_gpio_irq_update_bits()
222 	writel_relaxed(tmp, ctl->base + reg);  in meson_gpio_irq_update_bits()
224 	raw_spin_unlock_irqrestore(&ctl->lock, flags);  in meson_gpio_irq_update_bits()
241 				   ctl->params->pin_sel_mask << bit_offset,  in meson8_gpio_irq_sel_pin()
256 				   ctl->params->pin_sel_mask << bit_offset,  in meson_a1_gpio_irq_sel_pin()
274 	raw_spin_lock_irqsave(&ctl->lock, flags);  in meson_gpio_irq_request_channel()
277 	idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);  in meson_gpio_irq_request_channel()
278 	if (idx >= ctl->params->nr_channels) {  in meson_gpio_irq_request_channel()
279 		raw_spin_unlock_irqrestore(&ctl->lock, flags);  in meson_gpio_irq_request_channel()
281 		return -ENOSPC;  in meson_gpio_irq_request_channel()
285 	set_bit(idx, ctl->channel_map);  in meson_gpio_irq_request_channel()
287 	raw_spin_unlock_irqrestore(&ctl->lock, flags);  in meson_gpio_irq_request_channel()
293 	ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);  in meson_gpio_irq_request_channel()
301 	*channel_hwirq = &(ctl->channel_irqs[idx]);  in meson_gpio_irq_request_channel()
303 	pr_debug("hwirq %lu assigned to channel %d - irq %u\n",  in meson_gpio_irq_request_channel()
313 	return channel_hwirq - ctl->channel_irqs;  in meson_gpio_irq_get_channel_idx()
323 	clear_bit(idx, ctl->channel_map);  in meson_gpio_irq_release_channel()
329 	const struct meson_gpio_irq_params *params = ctl->params;  in meson8_gpio_irq_set_type()
349 		if (!params->support_edge_both)  in meson8_gpio_irq_set_type()
350 			return -EINVAL;  in meson8_gpio_irq_set_type()
368  * gpio irq relative registers for s4
369  * -PADCTRL_GPIO_IRQ_CTRL0
371  * bit[12-23]: single edge trigger
372  * bit[0-11]:  polarity trigger
374  * -PADCTRL_GPIO_IRQ_CTRL[X]
375  * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2
376  * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1
377  * where X = 1-6
379  * -PADCTRL_GPIO_IRQ_CTRL[7]
380  * bit[0-11]: both edge trigger
385 	const struct meson_gpio_irq_params *params = ctl->params;  in meson_s4_gpio_irq_set_type()
393 	meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, BIT(idx), 0);  in meson_s4_gpio_irq_set_type()
396 		val = BIT(ctl->params->edge_both_offset + idx);  in meson_s4_gpio_irq_set_type()
397 		meson_gpio_irq_update_bits(ctl, params->edge_pol_reg, val, val);  in meson_s4_gpio_irq_set_type()
402 		val |= BIT(ctl->params->pol_low_offset + idx);  in meson_s4_gpio_irq_set_type()
405 		val |= BIT(ctl->params->edge_single_offset + idx);  in meson_s4_gpio_irq_set_type()
407 	meson_gpio_irq_update_bits(ctl, params->edge_pol_reg,  in meson_s4_gpio_irq_set_type()
432 	struct meson_gpio_irq_controller *ctl = data->domain->host_data;  in meson_gpio_irq_set_type()
436 	ret = ctl->params->ops.gpio_irq_set_type(ctl, type, channel_hwirq);  in meson_gpio_irq_set_type()
445 	.name			= "meson-gpio-irqchip",
462 	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {  in meson_gpio_irq_domain_translate()
463 		*hwirq	= fwspec->param[0];  in meson_gpio_irq_domain_translate()
464 		*type	= fwspec->param[1];  in meson_gpio_irq_domain_translate()
468 	return -EINVAL;  in meson_gpio_irq_domain_translate()
478 	fwspec.fwnode = domain->parent->fwnode;  in meson_gpio_irq_allocate_gic_irq()
493 	struct meson_gpio_irq_controller *ctl = domain->host_data;  in meson_gpio_irq_domain_alloc()
500 		return -EINVAL;  in meson_gpio_irq_domain_alloc()
528 	struct meson_gpio_irq_controller *ctl = domain->host_data;  in meson_gpio_irq_domain_free()
556 		return -ENODEV;  in meson_gpio_irq_parse_dt()
558 	ctl->params = match->data;  in meson_gpio_irq_parse_dt()
561 						  "amlogic,channel-interrupts",  in meson_gpio_irq_parse_dt()
562 						  ctl->channel_irqs,  in meson_gpio_irq_parse_dt()
563 						  ctl->params->nr_channels,  in meson_gpio_irq_parse_dt()
564 						  ctl->params->nr_channels);  in meson_gpio_irq_parse_dt()
566 		pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);  in meson_gpio_irq_parse_dt()
570 	ctl->params->ops.gpio_irq_init(ctl);  in meson_gpio_irq_parse_dt()
583 		return -ENODEV;  in meson_gpio_irq_of_init()
589 		return -ENXIO;  in meson_gpio_irq_of_init()
594 		return -ENOMEM;  in meson_gpio_irq_of_init()
596 	raw_spin_lock_init(&ctl->lock);  in meson_gpio_irq_of_init()
598 	ctl->base = of_iomap(node, 0);  in meson_gpio_irq_of_init()
599 	if (!ctl->base) {  in meson_gpio_irq_of_init()
600 		ret = -ENOMEM;  in meson_gpio_irq_of_init()
609 					     ctl->params->nr_hwirq,  in meson_gpio_irq_of_init()
615 		ret = -ENODEV;  in meson_gpio_irq_of_init()
619 	pr_info("%d to %d gpio interrupt mux initialized\n",  in meson_gpio_irq_of_init()
620 		ctl->params->nr_hwirq, ctl->params->nr_channels);  in meson_gpio_irq_of_init()
625 	iounmap(ctl->base);  in meson_gpio_irq_of_init()
633 IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_of_init)
637 MODULE_DESCRIPTION("Meson GPIO Interrupt Multiplexer driver");
639 MODULE_ALIAS("platform:meson-gpio-intc");