Lines Matching +full:chip +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
11 select IRQ_DOMAIN_HIERARCHY
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
17 select ARM_GIC
28 select ARM_GIC
29 select IRQ_MSI_LIB
30 select PCI_MSI
31 select IRQ_MSI_IOMMU
38 select IRQ_DOMAIN_HIERARCHY
39 select PARTITION_PERCPU
40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
41 select HAVE_ARM_SMCCC_DISCOVERY
42 select IRQ_MSI_IOMMU
46 select GENERIC_MSI_IRQ
47 select IRQ_MSI_LIB
49 select IRQ_MSI_IOMMU
59 select IRQ_DOMAIN_HIERARCHY
60 select GENERIC_IRQ_CHIP
64 select IRQ_DOMAIN
80 select GENERIC_IRQ_CHIP
81 select PCI_MSI if PCI
82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
87 select PCI_MSI
88 select GENERIC_IRQ_CHIP
94 select GENERIC_IRQ_CHIP
95 select IRQ_DOMAIN
101 select GENERIC_IRQ_CHIP
102 select IRQ_DOMAIN
103 select SPARSE_IRQ
107 select GENERIC_IRQ_CHIP
108 select IRQ_DOMAIN
109 select SPARSE_IRQ
113 select IRQ_DOMAIN
116 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
120 select GENERIC_IRQ_CHIP
121 select IRQ_DOMAIN_HIERARCHY
122 select GENERIC_MSI_IRQ
123 select IRQ_MSI_LIB
125 Enable support for the Broadcom BCM2712 MSI-X target peripheral
126 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
133 select GENERIC_IRQ_CHIP
134 select IRQ_DOMAIN
135 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
138 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
141 select GENERIC_IRQ_CHIP
142 select IRQ_DOMAIN
143 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
146 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
149 select GENERIC_IRQ_CHIP
150 select IRQ_DOMAIN
156 select GENERIC_IRQ_CHIP
157 select IRQ_DOMAIN
161 select GENERIC_IRQ_CHIP
162 select IRQ_DOMAIN
166 select GENERIC_IRQ_CHIP
167 select IRQ_DOMAIN_HIERARCHY
171 select IRQ_DOMAIN
172 select SPARSE_IRQ
176 select ARM_GIC_V3
177 select ARM_GIC_V3_ITS
181 select GENERIC_IRQ_CHIP
182 select IRQ_DOMAIN
186 select IRQ_DOMAIN
187 select SPARSE_IRQ
192 select GENERIC_IRQ_CHIP
193 select IRQ_DOMAIN
200 will be called irq-lan966x-oic.
207 select GENERIC_IRQ_CHIP
208 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
209 select IRQ_DOMAIN
210 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
215 select IRQ_DOMAIN
216 select SPARSE_IRQ
224 select IRQ_DOMAIN
228 select GENERIC_IRQ_CHIP
229 select IRQ_DOMAIN
233 select IRQ_DOMAIN
237 select GENERIC_IRQ_CHIP
238 select IRQ_DOMAIN
241 bool "J-Core integrated AIC" if COMPILE_TEST
243 select IRQ_DOMAIN
245 Support for the J-Core integrated AIC.
249 select IRQ_DOMAIN
253 select IRQ_DOMAIN
256 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
259 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
260 select GENERIC_IRQ_CHIP
261 select IRQ_DOMAIN
264 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
268 select IRQ_DOMAIN_HIERARCHY
271 to 8 external interrupts with configurable sense select.
275 select GENERIC_IRQ_CHIP
276 select IRQ_DOMAIN_HIERARCHY
283 select GENERIC_IRQ_CHIP
284 select IRQ_DOMAIN_HIERARCHY
291 select REGMAP_IRQ
298 select REGMAP
299 select MFD_SYSCON
308 select IRQ_DOMAIN_HIERARCHY
309 select IRQ_FASTEOI_HIERARCHY_HANDLERS
313 select GENERIC_IRQ_CHIP
317 select IRQ_DOMAIN
318 select GENERIC_IRQ_CHIP
321 tristate "TS-4800 IRQ controller"
322 select IRQ_DOMAIN
326 Support for the TS-4800 FPGA IRQ controller
330 select IRQ_DOMAIN
339 select IRQ_DOMAIN
340 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
345 select IRQ_DOMAIN
368 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
369 select GENERIC_IRQ_IPI if SMP
370 select IRQ_DOMAIN_HIERARCHY
371 select MIPS_CM
382 select MFD_SYSCON
383 select GENERIC_IRQ_CHIP
392 select IRQ_DOMAIN
398 select IRQ_DOMAIN
399 select STMP_DEVICE
403 select IRQ_DOMAIN
404 select GENERIC_IRQ_CHIP
407 select IRQ_MSI_LIB
415 select IRQ_MSI_LIB
416 select GENERIC_MSI_IRQ
426 select MFD_SYSCON
430 select IRQ_MSI_IOMMU
440 select IRQ_DOMAIN_HIERARCHY
441 select GENERIC_IRQ_CHIP
447 select IRQ_DOMAIN
448 select GENERIC_IRQ_CHIP
453 select IRQ_DOMAIN_HIERARCHY
462 select IRQ_DOMAIN_HIERARCHY
470 select IRQ_DOMAIN_HIERARCHY
477 select GENERIC_IRQ_CHIP
478 select IRQ_DOMAIN
486 select IRQ_DOMAIN_HIERARCHY
495 select IRQ_DOMAIN_HIERARCHY
504 Say yes here to enable C-SKY SMP interrupt controller driver used
505 for C-SKY SMP system.
510 bool "C-SKY APB Interrupt Controller"
513 Say yes here to enable C-SKY APB interrupt controller driver used
514 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
521 select IRQ_DOMAIN
528 select IRQ_DOMAIN
537 select IRQ_DOMAIN
538 select IRQ_DOMAIN_HIERARCHY
539 select GENERIC_MSI_IRQ
540 select IRQ_MSI_LIB
543 CPU-to-CPU MSI controller. This requires a specially crafted DT
549 bool "Loongson-1 Interrupt Controller"
552 select IRQ_DOMAIN
553 select GENERIC_IRQ_CHIP
555 Support for the Loongson-1 platform Interrupt Controller.
561 select IRQ_DOMAIN_HIERARCHY
572 select IRQ_DOMAIN_HIERARCHY
573 select TI_SCI_INTA_MSI_DOMAIN
584 select IRQ_DOMAIN
586 This enables support for the PRU-ICSS Local Interrupt Controller
587 present within a PRU-ICSS subsystem present on various TI SoCs.
594 select IRQ_DOMAIN_HIERARCHY
599 select IRQ_DOMAIN_HIERARCHY
604 select GENERIC_MSI_IRQ
610 select IRQ_DOMAIN_HIERARCHY
611 select GENERIC_IRQ_MATRIX_ALLOCATOR
612 select GENERIC_MSI_IRQ
613 select IRQ_MSI_LIB
618 select IRQ_DOMAIN_HIERARCHY
619 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
625 select IRQ_DOMAIN_HIERARCHY
627 This enables support for the INTC chip found in StarFive JH8100
633 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller"
636 select IRQ_DOMAIN_HIERARCHY
637 select GENERIC_IRQ_IPI_MUX
639 This enables support for T-HEAD specific ACLINT SSWI device
653 select GENERIC_IRQ_CHIP
654 select IRQ_DOMAIN
655 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
656 select LOONGSON_HTVEC
657 select LOONGSON_LIOINTC
658 select LOONGSON_EIOINTC
659 select LOONGSON_PCH_PIC
660 select LOONGSON_PCH_MSI
661 select LOONGSON_PCH_LPC
664 irq chip hierarchy on LoongArch platforms please read the document
665 Documentation/arch/loongarch/irq-chip-model.rst.
671 select IRQ_DOMAIN
672 select GENERIC_IRQ_CHIP
681 select IRQ_DOMAIN_HIERARCHY
682 select GENERIC_IRQ_CHIP
690 select IRQ_DOMAIN
691 select GENERIC_IRQ_CHIP
693 Support for the Loongson-3 HyperTransport PIC Controller.
699 select IRQ_DOMAIN_HIERARCHY
707 select IRQ_DOMAIN_HIERARCHY
708 select IRQ_FASTEOI_HIERARCHY_HANDLERS
717 select IRQ_DOMAIN_HIERARCHY
718 select IRQ_MSI_LIB
719 select PCI_MSI
728 select IRQ_DOMAIN_HIERARCHY
736 select IRQ_DOMAIN
737 select IRQ_DOMAIN_HIERARCHY
749 select GENERIC_IRQ_CHIP
750 select IRQ_DOMAIN
756 select GENERIC_IRQ_IPI_MUX
764 select IRQ_DOMAIN
765 select IRQ_DOMAIN_HIERARCHY
773 select IRQ_DOMAIN_HIERARCHY
774 select IRQ_MSI_LIB
775 select PCI_MSI
778 This on-chip interrupt controller enables MSI sources to be
786 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
787 chained controller, routing all interrupt source in P-Chip to
788 the primary controller on C-Chip.