Lines Matching +full:soc +full:- +full:ip

1 # SPDX-License-Identifier: GPL-2.0-only
116 	tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
125 	  Enable support for the Broadcom BCM2712 MSI-X target peripheral
126 	  (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
138 	tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
146 	tristate "Broadcom STB 7120-style L2 interrupt controller driver"
200 	  will be called irq-lan966x-oic.
241 	bool "J-Core integrated AIC" if COMPILE_TEST
245 	  Support for the J-Core integrated AIC.
256 	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
259 	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
264 	  devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
274 	bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
278 	  Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
321 	tristate "TS-4800 IRQ controller"
326 	  Support for the TS-4800 FPGA IRQ controller
343 	bool "Xilinx Interrupt Controller IP"
347 	  Support for the Xilinx Interrupt Controller IP core.
354 	  Support for a CROSSBAR ip that precedes the main interrupt controller.
356 	  a free irq and configures the IP. Thus the peripheral interrupts are
360 	tristate "Keystone 2 IRQ controller IP"
363 		Support for Texas Instruments Keystone 2 IRQ controller IP which
472          Support Meson SoC Family GPIO Interrupt Multiplexer
504 	  Say yes here to enable C-SKY SMP interrupt controller driver used
505 	  for C-SKY SMP system.
510 	bool "C-SKY APB Interrupt Controller"
513 	  Say yes here to enable C-SKY APB interrupt controller driver used
514 	  by C-SKY single core SOC system. It uses mmio map apb-bus to visit
543 	  CPU-to-CPU MSI controller. This requires a specially crafted DT
549 	bool "Loongson-1 Interrupt Controller"
555 	  Support for the Loongson-1 platform Interrupt Controller.
586 	  This enables support for the PRU-ICSS Local Interrupt Controller
587 	  present within a PRU-ICSS subsystem present on various TI SoCs.
589 	  different processors within the SoC.
628 	  SoC.
633 	bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller"
639 	  This enables support for T-HEAD specific ACLINT SSWI device
665 	  Documentation/arch/loongarch/irq-chip-model.rst.
693 	  Support for the Loongson-3 HyperTransport PIC Controller.
745 	  Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
778 	  This on-chip interrupt controller enables MSI sources to be
779 	  routed to the primary PLIC controller on SoC.
785 	  Support for the Sunplus SP7021 Interrupt Controller IP core.
786 	  SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
787 	  chained controller, routing all interrupt source in P-Chip to
788 	  the primary controller on C-Chip.