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1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2024 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
9 * Based on the 'RISC-V IOMMU Architecture Specification', Version 1.0
10 * Published at https://github.com/riscv-non-isa/riscv-iommu
29 #define RISCV_IOMMU_QUEUE_ENABLE BIT(0)
30 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1)
31 #define RISCV_IOMMU_QUEUE_MEM_FAULT BIT(8)
32 #define RISCV_IOMMU_QUEUE_OVERFLOW BIT(9)
33 #define RISCV_IOMMU_QUEUE_ACTIVE BIT(16)
34 #define RISCV_IOMMU_QUEUE_BUSY BIT(17)
64 #define RISCV_IOMMU_CAPABILITIES_PD20 BIT_ULL(40)
67 * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings
69 * @RISCV_IOMMU_CAPABILITIES_IGS_WSI: IOMMU supports only Wired-Signaled interrupt
82 #define RISCV_IOMMU_FCTL_BE BIT(0)
83 #define RISCV_IOMMU_FCTL_WSI BIT(1)
84 #define RISCV_IOMMU_FCTL_GXL BIT(2)
86 /* 5.5 Device-directory-table pointer (64bits) */
93 * enum riscv_iommu_ddtp_modes - IOMMU translation modes
95 * @RISCV_IOMMU_DDTP_IOMMU_MODE_BARE: Pass-through mode
96 * @RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL: One-level DDT
97 * @RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL: Two-level DDT
98 * @RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL: Three-level DDT
154 #define RISCV_IOMMU_CQCSR_CMD_TO BIT(9)
155 #define RISCV_IOMMU_CQCSR_CMD_ILL BIT(10)
156 #define RISCV_IOMMU_CQCSR_FENCE_W_IP BIT(11)
187 #define RISCV_IOMMU_IPSR_CIP BIT(RISCV_IOMMU_INTR_CQ)
188 #define RISCV_IOMMU_IPSR_FIP BIT(RISCV_IOMMU_INTR_FQ)
189 #define RISCV_IOMMU_IPSR_PMIP BIT(RISCV_IOMMU_INTR_PM)
190 #define RISCV_IOMMU_IPSR_PIP BIT(RISCV_IOMMU_INTR_PQ)
194 #define RISCV_IOMMU_IOCOUNTOVF_CY BIT(0)
199 #define RISCV_IOMMU_IOCOUNTINH_CY BIT(0)
223 /* Number of defined performance-monitoring event selectors */
227 * enum riscv_iommu_hpmevent_id - Performance-monitoring event identifier
236 * @RISCV_IOMMU_HPMEVENT_S_VS_WALKS: First-stage page table walks
237 * @RISCV_IOMMU_HPMEVENT_G_WALKS: Second-stage page table walks
265 #define RISCV_IOMMU_TR_REQ_CTL_DID GENMASK_ULL(63, 40)
300 * Device Directory Table macros for non-leaf nodes
306 * struct riscv_iommu_dc - Device Context
348 /* Second-stage (aka G-stage) context fields */
354 * enum riscv_iommu_dc_iohgatp_modes - Guest address translation/protection modes
356 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4: Sv32x4 (2-bit extension of Sv32), when fctl.GXL == 1
357 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: Sv39x4 (2-bit extension of Sv39), when fctl.GXL == 0
358 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: Sv48x4 (2-bit extension of Sv48), when fctl.GXL == 0
359 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: Sv57x4 (2-bit extension of Sv57), when fctl.GXL == 0
372 /* First-stage context fields */
377 * enum riscv_iommu_dc_fsc_atp_modes - First stage address translation/protection modes
383 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8: 1lvl PDT, 8bit process ids
384 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17: 2lvl PDT, 17bit process ids
385 * @RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20: 3lvl PDT, 20bit process ids
389 * the RISC-V MMU), and PDTP holds the process directory table, used to select a
417 * struct riscv_iommu_pc - Process Context
440 * Chapter 3: In-memory queue interface
444 * struct riscv_iommu_command - Generic IOMMU command structure
448 * The commands are interpreted as two 64bit fields, where the first
450 * command's format, followed by a 3bit field that specifies the
451 * function invoked by that command, and the rest is opcode-specific.
465 /* 3.1.1 IOMMU Page-table cache invalidation */
475 /* dword1[61:10] is the 4K-aligned page address */
487 /* dword1 is the address, word-size aligned and shifted to the right by two bits. */
496 #define RISCV_IOMMU_CMD_IODIR_DID GENMASK_ULL(63, 40)
507 #define RISCV_IOMMU_CMD_ATS_RID GENMASK_ULL(55, 40)
513 /* Bits 1 - 10 are zeroed */
518 /* Bits 0 - 31 are zeroed */
519 #define RISCV_IOMMU_CMD_ATS_PRGR_PRG_INDEX GENMASK_ULL(40, 32)
520 /* Bits 41 - 43 are zeroed */
525 * struct riscv_iommu_fq_record - Fault/Event Queue Record
528 * @iotval: Transaction-type/cause specific format
535 * fault/event-specific information. For more details see section
551 #define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40)
554 * enum riscv_iommu_fq_causes - Fault/event cause values
586 * Values are on table 11 of the spec, encodings 275 - 2047 are reserved for standard
587 * use, and 2048 - 4095 for custom use.
634 * Values are on table 12 of the spec, type 4 and 10 - 31 are reserved for standard use
635 * and 31 - 63 for custom use.
650 * struct riscv_iommu_pq_record - PCIe Page Request record
666 #define RISCV_IOMMU_PQ_HDR_DID GENMASK_ULL(63, 40)
677 * struct riscv_iommu_msipte - MSI Page Table Entry
679 * @mrif_info: Memory-resident interrupt file info
685 * is an array of MSI PTEs, not a multi-level pt, each entry
689 * be used by software, any other reserved fields on pte must be zeroed-out
713 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) | in riscv_iommu_cmd_inval_vma()
715 cmd->dword1 = 0; in riscv_iommu_cmd_inval_vma()
721 cmd->dword1 = FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, phys_to_pfn(addr)); in riscv_iommu_cmd_inval_set_addr()
722 cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV; in riscv_iommu_cmd_inval_set_addr()
728 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_PSCID, pscid) | in riscv_iommu_cmd_inval_set_pscid()
735 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_GSCID, gscid) | in riscv_iommu_cmd_inval_set_gscid()
741 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | in riscv_iommu_cmd_iofence()
744 cmd->dword1 = 0; in riscv_iommu_cmd_iofence()
750 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | in riscv_iommu_cmd_iofence_set_av()
754 cmd->dword1 = addr >> 2; in riscv_iommu_cmd_iofence_set_av()
759 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | in riscv_iommu_cmd_iodir_inval_ddt()
761 cmd->dword1 = 0; in riscv_iommu_cmd_iodir_inval_ddt()
766 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | in riscv_iommu_cmd_iodir_inval_pdt()
768 cmd->dword1 = 0; in riscv_iommu_cmd_iodir_inval_pdt()
774 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_DID, devid) | in riscv_iommu_cmd_iodir_set_did()
781 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_PID, pasid); in riscv_iommu_cmd_iodir_set_pid()