Lines Matching full:iommu
27 #include "iommu.h"
28 #include "../dma-iommu.h"
30 #include "../iommu-pages.h"
119 * Looks up an IOMMU-probed device using its source ID.
125 * released by the iommu subsystem after being returned. The caller
129 struct device *device_rbtree_find(struct intel_iommu *iommu, u16 rid) in device_rbtree_find() argument
135 spin_lock_irqsave(&iommu->device_rbtree_lock, flags); in device_rbtree_find()
136 node = rb_find(&rid, &iommu->device_rbtree, device_rid_cmp_key); in device_rbtree_find()
139 spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); in device_rbtree_find()
144 static int device_rbtree_insert(struct intel_iommu *iommu, in device_rbtree_insert() argument
150 spin_lock_irqsave(&iommu->device_rbtree_lock, flags); in device_rbtree_insert()
151 curr = rb_find_add(&info->node, &iommu->device_rbtree, device_rid_cmp); in device_rbtree_insert()
152 spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); in device_rbtree_insert()
161 struct intel_iommu *iommu = info->iommu; in device_rbtree_remove() local
164 spin_lock_irqsave(&iommu->device_rbtree_lock, flags); in device_rbtree_remove()
165 rb_erase(&info->node, &iommu->device_rbtree); in device_rbtree_remove()
166 spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); in device_rbtree_remove()
190 struct intel_iommu *iommu; /* the corresponding iommu */ member
220 static bool translation_pre_enabled(struct intel_iommu *iommu) in translation_pre_enabled() argument
222 return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
225 static void clear_translation_pre_enabled(struct intel_iommu *iommu) in clear_translation_pre_enabled() argument
227 iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
230 static void init_translation_status(struct intel_iommu *iommu) in init_translation_status() argument
234 gsts = readl(iommu->reg + DMAR_GSTS_REG); in init_translation_status()
236 iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
247 pr_info("IOMMU enabled\n"); in intel_iommu_setup()
251 pr_info("IOMMU disabled\n"); in intel_iommu_setup()
256 pr_warn("intel_iommu=forcedac deprecated; use iommu.forcedac instead\n"); in intel_iommu_setup()
259 pr_warn("intel_iommu=strict deprecated; use iommu.strict=1 instead\n"); in intel_iommu_setup()
271 pr_info("Intel-IOMMU: not forcing on after tboot. This could expose security risk for tboot\n"); in intel_iommu_setup()
294 * Calculate the Supported Adjusted Guest Address Widths of an IOMMU.
298 static unsigned long __iommu_calculate_sagaw(struct intel_iommu *iommu) in __iommu_calculate_sagaw() argument
302 fl_sagaw = BIT(2) | (cap_fl5lp_support(iommu->cap) ? BIT(3) : 0); in __iommu_calculate_sagaw()
303 sl_sagaw = cap_sagaw(iommu->cap); in __iommu_calculate_sagaw()
306 if (!sm_supported(iommu) || !ecap_flts(iommu->ecap)) in __iommu_calculate_sagaw()
310 if (!ecap_slts(iommu->ecap)) in __iommu_calculate_sagaw()
316 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) in __iommu_calculate_agaw() argument
321 sagaw = __iommu_calculate_sagaw(iommu); in __iommu_calculate_agaw()
331 * Calculate max SAGAW for each iommu.
333 int iommu_calculate_max_sagaw(struct intel_iommu *iommu) in iommu_calculate_max_sagaw() argument
335 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); in iommu_calculate_max_sagaw()
339 * calculate agaw for each iommu.
343 int iommu_calculate_agaw(struct intel_iommu *iommu) in iommu_calculate_agaw() argument
345 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); in iommu_calculate_agaw()
348 static bool iommu_paging_structure_coherency(struct intel_iommu *iommu) in iommu_paging_structure_coherency() argument
350 return sm_supported(iommu) ? in iommu_paging_structure_coherency()
351 ecap_smpwc(iommu->ecap) : ecap_coherent(iommu->ecap); in iommu_paging_structure_coherency()
371 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, in iommu_context_addr() argument
374 struct root_entry *root = &iommu->root_entry[bus]; in iommu_context_addr()
382 if (!alloc && context_copied(iommu, bus, devfn)) in iommu_context_addr()
386 if (sm_supported(iommu)) { in iommu_context_addr()
400 context = iommu_alloc_page_node(iommu->node, GFP_ATOMIC); in iommu_context_addr()
404 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); in iommu_context_addr()
407 __iommu_flush_cache(iommu, entry, sizeof(*entry)); in iommu_context_addr()
445 /* We know that this device on this chipset has its own IOMMU. in quirk_ioat_snb_local_iommu()
446 * If we find it under a different IOMMU, then the BIOS is lying in quirk_ioat_snb_local_iommu()
447 * to us. Hope that the IOMMU for this device is actually in quirk_ioat_snb_local_iommu()
458 /* we know that the this iommu should be at offset 0xa000 from vtbar */ in quirk_ioat_snb_local_iommu()
469 static bool iommu_is_dummy(struct intel_iommu *iommu, struct device *dev) in iommu_is_dummy() argument
471 if (!iommu || iommu->drhd->ignored) in iommu_is_dummy()
490 struct intel_iommu *iommu; in device_lookup_iommu() local
504 * the PF instead to find the IOMMU. */ in device_lookup_iommu()
512 for_each_iommu(iommu, drhd) { in device_lookup_iommu()
520 * which we used for the IOMMU lookup. Strictly speaking in device_lookup_iommu()
546 iommu = NULL; in device_lookup_iommu()
548 if (iommu_is_dummy(iommu, dev)) in device_lookup_iommu()
549 iommu = NULL; in device_lookup_iommu()
553 return iommu; in device_lookup_iommu()
563 static void free_context_table(struct intel_iommu *iommu) in free_context_table() argument
568 if (!iommu->root_entry) in free_context_table()
572 context = iommu_context_addr(iommu, i, 0, 0); in free_context_table()
576 if (!sm_supported(iommu)) in free_context_table()
579 context = iommu_context_addr(iommu, i, 0x80, 0); in free_context_table()
584 iommu_free_page(iommu->root_entry); in free_context_table()
585 iommu->root_entry = NULL; in free_context_table()
589 static void pgtable_walk(struct intel_iommu *iommu, unsigned long pfn, in pgtable_walk() argument
614 void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, in dmar_fault_dump_ptes() argument
626 pr_info("Dump %s table entries for IOVA 0x%llx\n", iommu->name, addr); in dmar_fault_dump_ptes()
629 if (!iommu->root_entry) { in dmar_fault_dump_ptes()
633 rt_entry = &iommu->root_entry[bus]; in dmar_fault_dump_ptes()
635 if (sm_supported(iommu)) in dmar_fault_dump_ptes()
642 ctx_entry = iommu_context_addr(iommu, bus, devfn, 0); in dmar_fault_dump_ptes()
652 if (!sm_supported(iommu)) { in dmar_fault_dump_ptes()
703 pgtable_walk(iommu, addr >> VTD_PAGE_SHIFT, bus, devfn, pgtable, level); in dmar_fault_dump_ptes()
716 /* Address beyond IOMMU's addressing capabilities. */ in pfn_to_dma_pte()
960 /* We can't just free the pages because the IOMMU may still be walking
982 /* iommu handling */
983 static int iommu_alloc_root_entry(struct intel_iommu *iommu) in iommu_alloc_root_entry() argument
987 root = iommu_alloc_page_node(iommu->node, GFP_ATOMIC); in iommu_alloc_root_entry()
990 iommu->name); in iommu_alloc_root_entry()
994 __iommu_flush_cache(iommu, root, ROOT_SIZE); in iommu_alloc_root_entry()
995 iommu->root_entry = root; in iommu_alloc_root_entry()
1000 static void iommu_set_root_entry(struct intel_iommu *iommu) in iommu_set_root_entry() argument
1006 addr = virt_to_phys(iommu->root_entry); in iommu_set_root_entry()
1007 if (sm_supported(iommu)) in iommu_set_root_entry()
1010 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_set_root_entry()
1011 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); in iommu_set_root_entry()
1013 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); in iommu_set_root_entry()
1016 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_set_root_entry()
1019 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_set_root_entry()
1025 if (cap_esrtps(iommu->cap)) in iommu_set_root_entry()
1028 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); in iommu_set_root_entry()
1029 if (sm_supported(iommu)) in iommu_set_root_entry()
1030 qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0); in iommu_set_root_entry()
1031 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); in iommu_set_root_entry()
1034 void iommu_flush_write_buffer(struct intel_iommu *iommu) in iommu_flush_write_buffer() argument
1039 if (!rwbf_quirk && !cap_rwbf(iommu->cap)) in iommu_flush_write_buffer()
1042 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_flush_write_buffer()
1043 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); in iommu_flush_write_buffer()
1046 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_flush_write_buffer()
1049 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_flush_write_buffer()
1053 static void __iommu_flush_context(struct intel_iommu *iommu, in __iommu_flush_context() argument
1073 iommu->name, type); in __iommu_flush_context()
1078 raw_spin_lock_irqsave(&iommu->register_lock, flag); in __iommu_flush_context()
1079 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); in __iommu_flush_context()
1082 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, in __iommu_flush_context()
1085 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in __iommu_flush_context()
1088 void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, in __iommu_flush_iotlb() argument
1091 int tlb_offset = ecap_iotlb_offset(iommu->ecap); in __iommu_flush_iotlb()
1110 iommu->name, type); in __iommu_flush_iotlb()
1114 if (cap_write_drain(iommu->cap)) in __iommu_flush_iotlb()
1117 raw_spin_lock_irqsave(&iommu->register_lock, flag); in __iommu_flush_iotlb()
1120 dmar_writeq(iommu->reg + tlb_offset, val_iva); in __iommu_flush_iotlb()
1121 dmar_writeq(iommu->reg + tlb_offset + 8, val); in __iommu_flush_iotlb()
1124 IOMMU_WAIT_OP(iommu, tlb_offset + 8, in __iommu_flush_iotlb()
1127 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in __iommu_flush_iotlb()
1140 struct intel_iommu *iommu, u8 bus, u8 devfn) in domain_lookup_dev_info() argument
1147 if (info->iommu == iommu && info->bus == bus && in domain_lookup_dev_info()
1225 iopf_queue_remove_device(info->iommu->iopf_queue, info->dev); in iommu_disable_pci_pri()
1236 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) in iommu_disable_protect_mem_regions() argument
1241 if (!cap_plmr(iommu->cap) && !cap_phmr(iommu->cap)) in iommu_disable_protect_mem_regions()
1244 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_disable_protect_mem_regions()
1245 pmen = readl(iommu->reg + DMAR_PMEN_REG); in iommu_disable_protect_mem_regions()
1247 writel(pmen, iommu->reg + DMAR_PMEN_REG); in iommu_disable_protect_mem_regions()
1250 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, in iommu_disable_protect_mem_regions()
1253 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_disable_protect_mem_regions()
1256 static void iommu_enable_translation(struct intel_iommu *iommu) in iommu_enable_translation() argument
1261 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_enable_translation()
1262 iommu->gcmd |= DMA_GCMD_TE; in iommu_enable_translation()
1263 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_enable_translation()
1266 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_enable_translation()
1269 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_enable_translation()
1272 static void iommu_disable_translation(struct intel_iommu *iommu) in iommu_disable_translation() argument
1277 if (iommu_skip_te_disable && iommu->drhd->gfx_dedicated && in iommu_disable_translation()
1278 (cap_read_drain(iommu->cap) || cap_write_drain(iommu->cap))) in iommu_disable_translation()
1281 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_disable_translation()
1282 iommu->gcmd &= ~DMA_GCMD_TE; in iommu_disable_translation()
1283 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_disable_translation()
1286 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_disable_translation()
1289 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_disable_translation()
1292 static int iommu_init_domains(struct intel_iommu *iommu) in iommu_init_domains() argument
1296 ndomains = cap_ndoms(iommu->cap); in iommu_init_domains()
1298 iommu->name, ndomains); in iommu_init_domains()
1300 spin_lock_init(&iommu->lock); in iommu_init_domains()
1302 iommu->domain_ids = bitmap_zalloc(ndomains, GFP_KERNEL); in iommu_init_domains()
1303 if (!iommu->domain_ids) in iommu_init_domains()
1312 set_bit(0, iommu->domain_ids); in iommu_init_domains()
1322 set_bit(FLPT_DEFAULT_DID, iommu->domain_ids); in iommu_init_domains()
1327 static void disable_dmar_iommu(struct intel_iommu *iommu) in disable_dmar_iommu() argument
1329 if (!iommu->domain_ids) in disable_dmar_iommu()
1333 * All iommu domains must have been detached from the devices, in disable_dmar_iommu()
1336 if (WARN_ON(bitmap_weight(iommu->domain_ids, cap_ndoms(iommu->cap)) in disable_dmar_iommu()
1340 if (iommu->gcmd & DMA_GCMD_TE) in disable_dmar_iommu()
1341 iommu_disable_translation(iommu); in disable_dmar_iommu()
1344 static void free_dmar_iommu(struct intel_iommu *iommu) in free_dmar_iommu() argument
1346 if (iommu->domain_ids) { in free_dmar_iommu()
1347 bitmap_free(iommu->domain_ids); in free_dmar_iommu()
1348 iommu->domain_ids = NULL; in free_dmar_iommu()
1351 if (iommu->copied_tables) { in free_dmar_iommu()
1352 bitmap_free(iommu->copied_tables); in free_dmar_iommu()
1353 iommu->copied_tables = NULL; in free_dmar_iommu()
1357 free_context_table(iommu); in free_dmar_iommu()
1359 if (ecap_prs(iommu->ecap)) in free_dmar_iommu()
1360 intel_iommu_finish_prq(iommu); in free_dmar_iommu()
1367 static bool first_level_by_default(struct intel_iommu *iommu) in first_level_by_default() argument
1370 if (!sm_supported(iommu)) in first_level_by_default()
1374 if (ecap_flts(iommu->ecap) ^ ecap_slts(iommu->ecap)) in first_level_by_default()
1375 return ecap_flts(iommu->ecap); in first_level_by_default()
1380 int domain_attach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) in domain_attach_iommu() argument
1393 spin_lock(&iommu->lock); in domain_attach_iommu()
1394 curr = xa_load(&domain->iommu_array, iommu->seq_id); in domain_attach_iommu()
1397 spin_unlock(&iommu->lock); in domain_attach_iommu()
1402 ndomains = cap_ndoms(iommu->cap); in domain_attach_iommu()
1403 num = find_first_zero_bit(iommu->domain_ids, ndomains); in domain_attach_iommu()
1405 pr_err("%s: No free domain ids\n", iommu->name); in domain_attach_iommu()
1409 set_bit(num, iommu->domain_ids); in domain_attach_iommu()
1412 info->iommu = iommu; in domain_attach_iommu()
1413 curr = xa_cmpxchg(&domain->iommu_array, iommu->seq_id, in domain_attach_iommu()
1420 spin_unlock(&iommu->lock); in domain_attach_iommu()
1424 clear_bit(info->did, iommu->domain_ids); in domain_attach_iommu()
1426 spin_unlock(&iommu->lock); in domain_attach_iommu()
1431 void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu) in domain_detach_iommu() argument
1438 spin_lock(&iommu->lock); in domain_detach_iommu()
1439 info = xa_load(&domain->iommu_array, iommu->seq_id); in domain_detach_iommu()
1441 clear_bit(info->did, iommu->domain_ids); in domain_detach_iommu()
1442 xa_erase(&domain->iommu_array, iommu->seq_id); in domain_detach_iommu()
1446 spin_unlock(&iommu->lock); in domain_detach_iommu()
1474 static void copied_context_tear_down(struct intel_iommu *iommu, in copied_context_tear_down() argument
1480 if (!context_copied(iommu, bus, devfn)) in copied_context_tear_down()
1483 assert_spin_locked(&iommu->lock); in copied_context_tear_down()
1488 if (did_old < cap_ndoms(iommu->cap)) { in copied_context_tear_down()
1489 iommu->flush.flush_context(iommu, did_old, in copied_context_tear_down()
1493 iommu->flush.flush_iotlb(iommu, did_old, 0, 0, in copied_context_tear_down()
1497 clear_context_copied(iommu, bus, devfn); in copied_context_tear_down()
1506 static void context_present_cache_flush(struct intel_iommu *iommu, u16 did, in context_present_cache_flush() argument
1509 if (cap_caching_mode(iommu->cap)) { in context_present_cache_flush()
1510 iommu->flush.flush_context(iommu, 0, in context_present_cache_flush()
1514 iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); in context_present_cache_flush()
1516 iommu_flush_write_buffer(iommu); in context_present_cache_flush()
1521 struct intel_iommu *iommu, in domain_context_mapping_one() argument
1525 domain_lookup_dev_info(domain, iommu, bus, devfn); in domain_context_mapping_one()
1526 u16 did = domain_id_iommu(domain, iommu); in domain_context_mapping_one()
1535 spin_lock(&iommu->lock); in domain_context_mapping_one()
1537 context = iommu_context_addr(iommu, bus, devfn, 1); in domain_context_mapping_one()
1542 if (context_present(context) && !context_copied(iommu, bus, devfn)) in domain_context_mapping_one()
1545 copied_context_tear_down(iommu, context, bus, devfn); in domain_context_mapping_one()
1559 if (!ecap_coherent(iommu->ecap)) in domain_context_mapping_one()
1561 context_present_cache_flush(iommu, did, bus, devfn); in domain_context_mapping_one()
1565 spin_unlock(&iommu->lock); in domain_context_mapping_one()
1574 struct intel_iommu *iommu = info->iommu; in domain_context_mapping_cb() local
1577 return domain_context_mapping_one(domain, iommu, in domain_context_mapping_cb()
1585 struct intel_iommu *iommu = info->iommu; in domain_context_mapping() local
1590 return domain_context_mapping_one(domain, iommu, bus, devfn); in domain_context_mapping()
1771 struct intel_iommu *iommu = info->iommu; in domain_context_clear_one() local
1775 spin_lock(&iommu->lock); in domain_context_clear_one()
1776 context = iommu_context_addr(iommu, bus, devfn, 0); in domain_context_clear_one()
1778 spin_unlock(&iommu->lock); in domain_context_clear_one()
1784 __iommu_flush_cache(iommu, context, sizeof(*context)); in domain_context_clear_one()
1785 spin_unlock(&iommu->lock); in domain_context_clear_one()
1789 int __domain_setup_first_level(struct intel_iommu *iommu, in __domain_setup_first_level() argument
1795 return intel_pasid_setup_first_level(iommu, dev, pgd, in __domain_setup_first_level()
1797 return intel_pasid_replace_first_level(iommu, dev, pgd, pasid, did, in __domain_setup_first_level()
1798 iommu_domain_did(old, iommu), in __domain_setup_first_level()
1802 static int domain_setup_second_level(struct intel_iommu *iommu, in domain_setup_second_level() argument
1808 return intel_pasid_setup_second_level(iommu, domain, in domain_setup_second_level()
1810 return intel_pasid_replace_second_level(iommu, domain, dev, in domain_setup_second_level()
1811 iommu_domain_did(old, iommu), in domain_setup_second_level()
1815 static int domain_setup_passthrough(struct intel_iommu *iommu, in domain_setup_passthrough() argument
1820 return intel_pasid_setup_pass_through(iommu, dev, pasid); in domain_setup_passthrough()
1821 return intel_pasid_replace_pass_through(iommu, dev, in domain_setup_passthrough()
1822 iommu_domain_did(old, iommu), in domain_setup_passthrough()
1826 static int domain_setup_first_level(struct intel_iommu *iommu, in domain_setup_first_level() argument
1844 return __domain_setup_first_level(iommu, dev, pasid, in domain_setup_first_level()
1845 domain_id_iommu(domain, iommu), in domain_setup_first_level()
1853 struct intel_iommu *iommu = info->iommu; in dmar_domain_attach_device() local
1857 ret = domain_attach_iommu(domain, iommu); in dmar_domain_attach_device()
1869 if (!sm_supported(iommu)) in dmar_domain_attach_device()
1872 ret = domain_setup_first_level(iommu, domain, dev, in dmar_domain_attach_device()
1875 ret = domain_setup_second_level(iommu, domain, dev, in dmar_domain_attach_device()
1924 struct intel_iommu *iommu = info->iommu; in device_def_domain_type() local
1930 if (!ecap_pass_through(iommu->ecap)) in device_def_domain_type()
1943 static void intel_iommu_init_qi(struct intel_iommu *iommu) in intel_iommu_init_qi() argument
1946 * Start from the sane iommu hardware state. in intel_iommu_init_qi()
1951 if (!iommu->qi) { in intel_iommu_init_qi()
1955 dmar_fault(-1, iommu); in intel_iommu_init_qi()
1960 dmar_disable_qi(iommu); in intel_iommu_init_qi()
1963 if (dmar_enable_qi(iommu)) { in intel_iommu_init_qi()
1967 iommu->flush.flush_context = __iommu_flush_context; in intel_iommu_init_qi()
1968 iommu->flush.flush_iotlb = __iommu_flush_iotlb; in intel_iommu_init_qi()
1970 iommu->name); in intel_iommu_init_qi()
1972 iommu->flush.flush_context = qi_flush_context; in intel_iommu_init_qi()
1973 iommu->flush.flush_iotlb = qi_flush_iotlb; in intel_iommu_init_qi()
1974 pr_info("%s: Using Queued invalidation\n", iommu->name); in intel_iommu_init_qi()
1978 static int copy_context_table(struct intel_iommu *iommu, in copy_context_table() argument
2000 __iommu_flush_cache(iommu, new_ce, in copy_context_table()
2030 new_ce = iommu_alloc_page_node(iommu->node, GFP_KERNEL); in copy_context_table()
2044 if (did >= 0 && did < cap_ndoms(iommu->cap)) in copy_context_table()
2045 set_bit(did, iommu->domain_ids); in copy_context_table()
2047 set_context_copied(iommu, bus, devfn); in copy_context_table()
2053 __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE); in copy_context_table()
2062 static int copy_translation_tables(struct intel_iommu *iommu) in copy_translation_tables() argument
2072 rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG); in copy_translation_tables()
2074 new_ext = !!sm_supported(iommu); in copy_translation_tables()
2085 iommu->copied_tables = bitmap_zalloc(BIT_ULL(16), GFP_KERNEL); in copy_translation_tables()
2086 if (!iommu->copied_tables) in copy_translation_tables()
2105 ret = copy_context_table(iommu, &old_rt[bus], in copy_translation_tables()
2109 iommu->name, bus); in copy_translation_tables()
2114 spin_lock(&iommu->lock); in copy_translation_tables()
2123 iommu->root_entry[bus].lo = val; in copy_translation_tables()
2130 iommu->root_entry[bus].hi = val; in copy_translation_tables()
2133 spin_unlock(&iommu->lock); in copy_translation_tables()
2137 __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE); in copy_translation_tables()
2150 struct intel_iommu *iommu; in init_dmars() local
2153 for_each_iommu(iommu, drhd) { in init_dmars()
2155 iommu_disable_translation(iommu); in init_dmars()
2160 * Find the max pasid size of all IOMMU's in the system. in init_dmars()
2164 if (pasid_supported(iommu)) { in init_dmars()
2165 u32 temp = 2 << ecap_pss(iommu->ecap); in init_dmars()
2171 intel_iommu_init_qi(iommu); in init_dmars()
2173 ret = iommu_init_domains(iommu); in init_dmars()
2177 init_translation_status(iommu); in init_dmars()
2179 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_dmars()
2180 iommu_disable_translation(iommu); in init_dmars()
2181 clear_translation_pre_enabled(iommu); in init_dmars()
2183 iommu->name); in init_dmars()
2189 * among all IOMMU's. Need to Split it later. in init_dmars()
2191 ret = iommu_alloc_root_entry(iommu); in init_dmars()
2195 if (translation_pre_enabled(iommu)) { in init_dmars()
2198 ret = copy_translation_tables(iommu); in init_dmars()
2201 * We found the IOMMU with translation in init_dmars()
2210 iommu->name); in init_dmars()
2211 iommu_disable_translation(iommu); in init_dmars()
2212 clear_translation_pre_enabled(iommu); in init_dmars()
2215 iommu->name); in init_dmars()
2219 intel_svm_check(iommu); in init_dmars()
2227 for_each_active_iommu(iommu, drhd) { in init_dmars()
2228 iommu_flush_write_buffer(iommu); in init_dmars()
2229 iommu_set_root_entry(iommu); in init_dmars()
2241 for_each_iommu(iommu, drhd) { in init_dmars()
2248 iommu_disable_protect_mem_regions(iommu); in init_dmars()
2252 iommu_flush_write_buffer(iommu); in init_dmars()
2254 if (ecap_prs(iommu->ecap)) { in init_dmars()
2260 ret = intel_iommu_enable_prq(iommu); in init_dmars()
2266 ret = dmar_set_interrupt(iommu); in init_dmars()
2274 for_each_active_iommu(iommu, drhd) { in init_dmars()
2275 disable_dmar_iommu(iommu); in init_dmars()
2276 free_dmar_iommu(iommu); in init_dmars()
2310 /* This IOMMU has *only* gfx devices. Either bypass it or in init_no_remapping_devices()
2322 struct intel_iommu *iommu = NULL; in init_iommu_hw() local
2325 for_each_active_iommu(iommu, drhd) { in init_iommu_hw()
2326 if (iommu->qi) { in init_iommu_hw()
2327 ret = dmar_reenable_qi(iommu); in init_iommu_hw()
2333 for_each_iommu(iommu, drhd) { in init_iommu_hw()
2340 iommu_disable_protect_mem_regions(iommu); in init_iommu_hw()
2344 iommu_flush_write_buffer(iommu); in init_iommu_hw()
2345 iommu_set_root_entry(iommu); in init_iommu_hw()
2346 iommu_enable_translation(iommu); in init_iommu_hw()
2347 iommu_disable_protect_mem_regions(iommu); in init_iommu_hw()
2356 struct intel_iommu *iommu; in iommu_flush_all() local
2358 for_each_active_iommu(iommu, drhd) { in iommu_flush_all()
2359 iommu->flush.flush_context(iommu, 0, 0, 0, in iommu_flush_all()
2361 iommu->flush.flush_iotlb(iommu, 0, 0, 0, in iommu_flush_all()
2369 struct intel_iommu *iommu = NULL; in iommu_suspend() local
2374 for_each_active_iommu(iommu, drhd) { in iommu_suspend()
2375 iommu_disable_translation(iommu); in iommu_suspend()
2377 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_suspend()
2379 iommu->iommu_state[SR_DMAR_FECTL_REG] = in iommu_suspend()
2380 readl(iommu->reg + DMAR_FECTL_REG); in iommu_suspend()
2381 iommu->iommu_state[SR_DMAR_FEDATA_REG] = in iommu_suspend()
2382 readl(iommu->reg + DMAR_FEDATA_REG); in iommu_suspend()
2383 iommu->iommu_state[SR_DMAR_FEADDR_REG] = in iommu_suspend()
2384 readl(iommu->reg + DMAR_FEADDR_REG); in iommu_suspend()
2385 iommu->iommu_state[SR_DMAR_FEUADDR_REG] = in iommu_suspend()
2386 readl(iommu->reg + DMAR_FEUADDR_REG); in iommu_suspend()
2388 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_suspend()
2396 struct intel_iommu *iommu = NULL; in iommu_resume() local
2401 panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); in iommu_resume()
2403 WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); in iommu_resume()
2407 for_each_active_iommu(iommu, drhd) { in iommu_resume()
2409 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_resume()
2411 writel(iommu->iommu_state[SR_DMAR_FECTL_REG], in iommu_resume()
2412 iommu->reg + DMAR_FECTL_REG); in iommu_resume()
2413 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], in iommu_resume()
2414 iommu->reg + DMAR_FEDATA_REG); in iommu_resume()
2415 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], in iommu_resume()
2416 iommu->reg + DMAR_FEADDR_REG); in iommu_resume()
2417 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], in iommu_resume()
2418 iommu->reg + DMAR_FEUADDR_REG); in iommu_resume()
2420 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_resume()
2645 struct intel_iommu *iommu = dmaru->iommu; in intel_iommu_add() local
2651 if (iommu->gcmd & DMA_GCMD_TE) in intel_iommu_add()
2652 iommu_disable_translation(iommu); in intel_iommu_add()
2654 ret = iommu_init_domains(iommu); in intel_iommu_add()
2656 ret = iommu_alloc_root_entry(iommu); in intel_iommu_add()
2660 intel_svm_check(iommu); in intel_iommu_add()
2667 iommu_disable_protect_mem_regions(iommu); in intel_iommu_add()
2671 intel_iommu_init_qi(iommu); in intel_iommu_add()
2672 iommu_flush_write_buffer(iommu); in intel_iommu_add()
2674 if (ecap_prs(iommu->ecap)) { in intel_iommu_add()
2675 ret = intel_iommu_enable_prq(iommu); in intel_iommu_add()
2680 ret = dmar_set_interrupt(iommu); in intel_iommu_add()
2684 iommu_set_root_entry(iommu); in intel_iommu_add()
2685 iommu_enable_translation(iommu); in intel_iommu_add()
2687 iommu_disable_protect_mem_regions(iommu); in intel_iommu_add()
2691 disable_dmar_iommu(iommu); in intel_iommu_add()
2693 free_dmar_iommu(iommu); in intel_iommu_add()
2700 struct intel_iommu *iommu = dmaru->iommu; in dmar_iommu_hotplug() local
2704 if (iommu == NULL) in dmar_iommu_hotplug()
2710 disable_dmar_iommu(iommu); in dmar_iommu_hotplug()
2711 free_dmar_iommu(iommu); in dmar_iommu_hotplug()
2764 static int dmar_ats_supported(struct pci_dev *dev, struct intel_iommu *iommu) in dmar_ats_supported() argument
2779 * When IOMMU is in legacy mode, enabling ATS is done in dmar_ats_supported()
2784 return !(satcu->atc_required && !sm_supported(iommu)); in dmar_ats_supported()
2892 struct intel_iommu *iommu = NULL; in intel_disable_iommus() local
2895 for_each_iommu(iommu, drhd) in intel_disable_iommus()
2896 iommu_disable_translation(iommu); in intel_disable_iommus()
2902 struct intel_iommu *iommu = NULL; in intel_iommu_shutdown() local
2912 iommu = drhd->iommu; in intel_iommu_shutdown()
2915 iommu_disable_protect_mem_regions(iommu); in intel_iommu_shutdown()
2918 iommu_disable_translation(iommu); in intel_iommu_shutdown()
2926 return container_of(iommu_dev, struct intel_iommu, iommu); in dev_to_intel_iommu()
2932 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in version_show() local
2933 u32 ver = readl(iommu->reg + DMAR_VER_REG); in version_show()
2942 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in address_show() local
2943 return sysfs_emit(buf, "%llx\n", iommu->reg_phys); in address_show()
2950 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in cap_show() local
2951 return sysfs_emit(buf, "%llx\n", iommu->cap); in cap_show()
2958 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in ecap_show() local
2959 return sysfs_emit(buf, "%llx\n", iommu->ecap); in ecap_show()
2966 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in domains_supported_show() local
2967 return sysfs_emit(buf, "%ld\n", cap_ndoms(iommu->cap)); in domains_supported_show()
2974 struct intel_iommu *iommu = dev_to_intel_iommu(dev); in domains_used_show() local
2976 bitmap_weight(iommu->domain_ids, in domains_used_show()
2977 cap_ndoms(iommu->cap))); in domains_used_show()
2992 .name = "intel-iommu",
3020 pr_info("Intel-IOMMU force enabled due to platform opt in\n"); in platform_optin_force_iommu()
3023 * If Intel-IOMMU is disabled by default, we will apply identity in platform_optin_force_iommu()
3039 struct intel_iommu *iommu __maybe_unused; in probe_acpi_namespace_devices()
3043 for_each_active_iommu(iommu, drhd) { in probe_acpi_namespace_devices()
3078 pr_warn("Forcing Intel-IOMMU to enabled\n"); in tboot_force_iommu()
3090 struct intel_iommu *iommu; in intel_iommu_init() local
3093 * Intel IOMMU is required for a TXT/tboot launch or platform in intel_iommu_init()
3127 * We exit the function here to ensure IOMMU's remapping and in intel_iommu_init()
3128 * mempool aren't setup, which means that the IOMMU's PMRs in intel_iommu_init()
3135 for_each_iommu(iommu, drhd) in intel_iommu_init()
3136 iommu_disable_protect_mem_regions(iommu); in intel_iommu_init()
3171 for_each_active_iommu(iommu, drhd) { in intel_iommu_init()
3177 * the virtual and physical IOMMU page-tables. in intel_iommu_init()
3179 if (cap_caching_mode(iommu->cap) && in intel_iommu_init()
3180 !first_level_by_default(iommu)) { in intel_iommu_init()
3181 pr_info_once("IOMMU batching disallowed due to virtualization\n"); in intel_iommu_init()
3184 iommu_device_sysfs_add(&iommu->iommu, NULL, in intel_iommu_init()
3186 "%s", iommu->name); in intel_iommu_init()
3188 * The iommu device probe is protected by the iommu_probe_device_lock. in intel_iommu_init()
3193 iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); in intel_iommu_init()
3196 iommu_pmu_register(iommu); in intel_iommu_init()
3203 for_each_iommu(iommu, drhd) { in intel_iommu_init()
3204 if (!drhd->ignored && !translation_pre_enabled(iommu)) in intel_iommu_init()
3205 iommu_enable_translation(iommu); in intel_iommu_init()
3207 iommu_disable_protect_mem_regions(iommu); in intel_iommu_init()
3232 * NB - intel-iommu lacks any sort of reference counting for the users of
3257 struct intel_iommu *iommu = info->iommu; in device_block_translation() local
3264 if (sm_supported(iommu)) in device_block_translation()
3265 intel_pasid_tear_down_entry(iommu, dev, in device_block_translation()
3278 domain_detach_iommu(info->domain, iommu); in device_block_translation()
3301 static int iommu_superpage_capability(struct intel_iommu *iommu, bool first_stage) in iommu_superpage_capability() argument
3307 return cap_fl1gp_support(iommu->cap) ? 2 : 1; in iommu_superpage_capability()
3309 return fls(cap_super_page_val(iommu->cap)); in iommu_superpage_capability()
3315 struct intel_iommu *iommu = info->iommu; in paging_domain_alloc() local
3334 addr_width = agaw_to_width(iommu->agaw); in paging_domain_alloc()
3335 if (addr_width > cap_mgaw(iommu->cap)) in paging_domain_alloc()
3336 addr_width = cap_mgaw(iommu->cap); in paging_domain_alloc()
3338 domain->agaw = iommu->agaw; in paging_domain_alloc()
3341 /* iommu memory access coherency */ in paging_domain_alloc()
3342 domain->iommu_coherency = iommu_paging_structure_coherency(iommu); in paging_domain_alloc()
3346 domain->iommu_superpage = iommu_superpage_capability(iommu, first_stage); in paging_domain_alloc()
3380 struct intel_iommu *iommu = info->iommu; in intel_iommu_domain_alloc_paging_flags() local
3389 if (nested_parent && !nested_supported(iommu)) in intel_iommu_domain_alloc_paging_flags()
3391 if (user_data || (dirty_tracking && !ssads_supported(iommu))) in intel_iommu_domain_alloc_paging_flags()
3400 if (!sm_supported(iommu) || !ecap_slts(iommu->ecap)) in intel_iommu_domain_alloc_paging_flags()
3404 first_stage = first_level_by_default(iommu); in intel_iommu_domain_alloc_paging_flags()
3445 struct intel_iommu *iommu = info->iommu; in paging_domain_compatible() local
3451 if (dmar_domain->force_snooping && !ecap_sc_support(iommu->ecap)) in paging_domain_compatible()
3454 if (domain->dirty_ops && !ssads_supported(iommu)) in paging_domain_compatible()
3458 iommu_paging_structure_coherency(iommu)) in paging_domain_compatible()
3462 iommu_superpage_capability(iommu, dmar_domain->use_first_level)) in paging_domain_compatible()
3466 (!sm_supported(iommu) || !ecap_flts(iommu->ecap))) in paging_domain_compatible()
3469 /* check if this iommu agaw is sufficient for max mapped address */ in paging_domain_compatible()
3470 addr_width = agaw_to_width(iommu->agaw); in paging_domain_compatible()
3471 if (addr_width > cap_mgaw(iommu->cap)) in paging_domain_compatible()
3472 addr_width = cap_mgaw(iommu->cap); in paging_domain_compatible()
3474 if (dmar_domain->gaw > addr_width || dmar_domain->agaw > iommu->agaw) in paging_domain_compatible()
3477 if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev) && in paging_domain_compatible()
3478 context_copied(iommu, info->bus, info->devfn)) in paging_domain_compatible()
3520 pr_err("%s: iommu width (%d) is not " in intel_iommu_map()
3635 if (!ecap_sc_support(info->iommu->ecap)) { in domain_support_force_snooping()
3659 intel_pasid_setup_page_snoop_control(info->iommu, info->dev, in domain_set_force_snooping()
3696 return ecap_sc_support(info->iommu->ecap); in intel_iommu_capable()
3698 return ssads_supported(info->iommu); in intel_iommu_capable()
3708 struct intel_iommu *iommu; in intel_iommu_probe_device() local
3712 iommu = device_lookup_iommu(dev, &bus, &devfn); in intel_iommu_probe_device()
3713 if (!iommu || !iommu->iommu.ops) in intel_iommu_probe_device()
3727 info->segment = iommu->segment; in intel_iommu_probe_device()
3731 info->iommu = iommu; in intel_iommu_probe_device()
3733 if (ecap_dev_iotlb_support(iommu->ecap) && in intel_iommu_probe_device()
3735 dmar_ats_supported(pdev, iommu)) { in intel_iommu_probe_device()
3740 * For IOMMU that supports device IOTLB throttling in intel_iommu_probe_device()
3742 * of a VF such that IOMMU HW can gauge queue depth in intel_iommu_probe_device()
3746 if (ecap_dit(iommu->ecap)) in intel_iommu_probe_device()
3750 if (sm_supported(iommu)) { in intel_iommu_probe_device()
3751 if (pasid_supported(iommu)) { in intel_iommu_probe_device()
3758 if (info->ats_supported && ecap_prs(iommu->ecap) && in intel_iommu_probe_device()
3767 ret = device_rbtree_insert(iommu, info); in intel_iommu_probe_device()
3772 if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) { in intel_iommu_probe_device()
3779 if (!context_copied(iommu, info->bus, info->devfn)) { in intel_iommu_probe_device()
3788 return &iommu->iommu; in intel_iommu_probe_device()
3802 struct intel_iommu *iommu = info->iommu; in intel_iommu_probe_finalize() local
3814 if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev)) in intel_iommu_probe_finalize()
3822 struct intel_iommu *iommu = info->iommu; in intel_iommu_release_device() local
3832 mutex_lock(&iommu->iopf_lock); in intel_iommu_release_device()
3835 mutex_unlock(&iommu->iopf_lock); in intel_iommu_release_device()
3837 if (sm_supported(iommu) && !dev_is_real_dma_subdevice(dev) && in intel_iommu_release_device()
3838 !context_copied(iommu, info->bus, info->devfn)) in intel_iommu_release_device()
3915 struct intel_iommu *iommu = info->iommu; in intel_iommu_enable_iopf() local
3926 ret = iopf_queue_add_device(iommu->iopf_queue, dev); in intel_iommu_enable_iopf()
3938 struct intel_iommu *iommu = info->iommu; in intel_iommu_disable_iopf() local
3946 iopf_queue_remove_device(iommu->iopf_queue, dev); in intel_iommu_disable_iopf()
3984 return translation_pre_enabled(info->iommu) && !info->domain; in intel_iommu_is_attach_deferred()
3990 * thus not be able to bypass the IOMMU restrictions.
3996 "Skipping IOMMU quirk for dev [%04X:%04X] on untrusted PCI link\n", in risky_device()
4017 struct intel_iommu *iommu = info->iommu; in domain_remove_dev_pasid() local
4040 domain_detach_iommu(dmar_domain, iommu); in domain_remove_dev_pasid()
4053 intel_pasid_tear_down_entry(info->iommu, dev, pasid, false); in blocking_domain_set_dev_pasid()
4065 struct intel_iommu *iommu = info->iommu; in domain_add_dev_pasid() local
4074 ret = domain_attach_iommu(dmar_domain, iommu); in domain_add_dev_pasid()
4090 domain_detach_iommu(dmar_domain, iommu); in domain_add_dev_pasid()
4102 struct intel_iommu *iommu = info->iommu; in intel_iommu_set_dev_pasid() local
4109 if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) in intel_iommu_set_dev_pasid()
4115 if (context_copied(iommu, info->bus, info->devfn)) in intel_iommu_set_dev_pasid()
4127 ret = domain_setup_first_level(iommu, dmar_domain, in intel_iommu_set_dev_pasid()
4130 ret = domain_setup_second_level(iommu, dmar_domain, in intel_iommu_set_dev_pasid()
4149 struct intel_iommu *iommu = info->iommu; in intel_iommu_hw_info() local
4157 vtd->cap_reg = iommu->cap; in intel_iommu_hw_info()
4158 vtd->ecap_reg = iommu->ecap; in intel_iommu_hw_info()
4174 ret = intel_pasid_setup_dirty_tracking(info->iommu, info->dev, in device_set_dirty_tracking()
4291 struct intel_iommu *iommu = info->iommu; in context_setup_pass_through() local
4294 spin_lock(&iommu->lock); in context_setup_pass_through()
4295 context = iommu_context_addr(iommu, bus, devfn, 1); in context_setup_pass_through()
4297 spin_unlock(&iommu->lock); in context_setup_pass_through()
4301 if (context_present(context) && !context_copied(iommu, bus, devfn)) { in context_setup_pass_through()
4302 spin_unlock(&iommu->lock); in context_setup_pass_through()
4306 copied_context_tear_down(iommu, context, bus, devfn); in context_setup_pass_through()
4314 context_set_address_width(context, iommu->msagaw); in context_setup_pass_through()
4318 if (!ecap_coherent(iommu->ecap)) in context_setup_pass_through()
4320 context_present_cache_flush(iommu, FLPT_DEFAULT_DID, bus, devfn); in context_setup_pass_through()
4321 spin_unlock(&iommu->lock); in context_setup_pass_through()
4347 struct intel_iommu *iommu = info->iommu; in identity_domain_attach_dev() local
4355 if (sm_supported(iommu)) in identity_domain_attach_dev()
4356 ret = intel_pasid_setup_pass_through(iommu, dev, IOMMU_NO_PASID); in identity_domain_attach_dev()
4368 struct intel_iommu *iommu = info->iommu; in identity_domain_set_dev_pasid() local
4371 if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev)) in identity_domain_set_dev_pasid()
4374 ret = domain_setup_passthrough(iommu, dev, pasid, old); in identity_domain_set_dev_pasid()
4429 pci_info(dev, "Disabling IOMMU for graphics on this chipset\n"); in quirk_iommu_igfx()
4513 pci_info(dev, "BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); in quirk_calpella_no_shadow_gtt()
4541 pci_info(dev, "Skip IOMMU disabling for graphics\n"); in quirk_igfx_skip_te_disable()
4635 * before unmap/unbind. For #3, iommu driver gets mmu_notifier to
4652 qi_flush_dev_iotlb(info->iommu, sid, info->pfsid, in quirk_extra_dev_tlb_flush()
4655 qi_flush_dev_iotlb_pasid(info->iommu, sid, info->pfsid, in quirk_extra_dev_tlb_flush()
4674 int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob) in ecmd_submit_sync() argument
4680 if (!cap_ecmds(iommu->cap)) in ecmd_submit_sync()
4683 raw_spin_lock_irqsave(&iommu->register_lock, flags); in ecmd_submit_sync()
4685 res = dmar_readq(iommu->reg + DMAR_ECRSP_REG); in ecmd_submit_sync()
4698 dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob); in ecmd_submit_sync()
4699 dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT)); in ecmd_submit_sync()
4701 IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, dmar_readq, in ecmd_submit_sync()
4711 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in ecmd_submit_sync()