Lines Matching +full:diff +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0-only
9 * ad7380/1 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7380-7381.pdf
10 * ad7383/4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-7384.pdf
11 …* ad7386/7/8 : https://www.analog.com/media/en/technical-documentation/data-sheets/AD7386-7387-738…
12 * ad7380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7380-4.pdf
13 * ad7381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7381-4.pdf
14 …* ad7383/4-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7383-4-ad7384…
15 …* ad7386/7/8-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/ad7386-4-7387…
16 * adaq4370-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4370-4.pdf
17 * adaq4380-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4380-4.pdf
18 * adaq4381-4 : https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4381-4.pdf
42 #include <linux/iio/buffer-dmaengine.h>
105 #define AD7380_SPI_BYTES(scan_type) ((scan_type)->realbits > 16 ? 4 : 2)
113 const struct iio_chan_spec *channels; member
153 /* Extended scan types for 12-bit unsigned chips. */
169 /* Extended scan types for 14-bit signed chips. */
185 /* Extended scan types for 14-bit unsigned chips. */
201 /* Extended scan types for 16-bit signed_chips. */
217 /* Extended scan types for 16-bit unsigned chips. */
238 /* Extended scan types for 12-bit unsigned chips, offload support. */
254 /* Extended scan types for 14-bit signed chips, offload support. */
270 /* Extended scan types for 14-bit unsigned chips, offload support. */
286 /* Extended scan types for 16-bit signed_chips, offload support. */
302 /* Extended scan types for 16-bit unsigned chips, offload support. */
318 #define _AD7380_CHANNEL(index, bits, diff, sign, gain) { \ argument
322 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \
328 .differential = (diff), \
329 .channel = (diff) ? (2 * (index)) : (index), \
330 .channel2 = (diff) ? (2 * (index) + 1) : 0, \
339 #define _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, gain) { \ argument
343 ((diff) ? 0 : BIT(IIO_CHAN_INFO_OFFSET)), \
351 .differential = (diff), \
352 .channel = (diff) ? (2 * (index)) : (index), \
353 .channel2 = (diff) ? (2 * (index) + 1) : 0, \
364 * Notes on the offload channels:
365 * - There is no soft timestamp since everything is done in hardware.
366 * - There is a sampling frequency attribute added. This controls the SPI
368 * - The storagebits value depends on the SPI offload provider. Currently there
370 * which always uses 32-bit words for data values, even for <= 16-bit ADCs.
374 #define AD7380_CHANNEL(index, bits, diff, sign) \ argument
375 _AD7380_CHANNEL(index, bits, diff, sign, false)
377 #define ADAQ4380_CHANNEL(index, bits, diff, sign) \ argument
378 _AD7380_CHANNEL(index, bits, diff, sign, true)
380 #define DEFINE_AD7380_2_CHANNEL(name, bits, diff, sign) \ argument
382 AD7380_CHANNEL(0, bits, diff, sign), \
383 AD7380_CHANNEL(1, bits, diff, sign), \
387 #define DEFINE_AD7380_4_CHANNEL(name, bits, diff, sign) \ argument
389 AD7380_CHANNEL(0, bits, diff, sign), \
390 AD7380_CHANNEL(1, bits, diff, sign), \
391 AD7380_CHANNEL(2, bits, diff, sign), \
392 AD7380_CHANNEL(3, bits, diff, sign), \
396 #define DEFINE_ADAQ4380_4_CHANNEL(name, bits, diff, sign) \ argument
398 ADAQ4380_CHANNEL(0, bits, diff, sign), \
399 ADAQ4380_CHANNEL(1, bits, diff, sign), \
400 ADAQ4380_CHANNEL(2, bits, diff, sign), \
401 ADAQ4380_CHANNEL(3, bits, diff, sign), \
405 #define DEFINE_AD7380_8_CHANNEL(name, bits, diff, sign) \ argument
407 AD7380_CHANNEL(0, bits, diff, sign), \
408 AD7380_CHANNEL(1, bits, diff, sign), \
409 AD7380_CHANNEL(2, bits, diff, sign), \
410 AD7380_CHANNEL(3, bits, diff, sign), \
411 AD7380_CHANNEL(4, bits, diff, sign), \
412 AD7380_CHANNEL(5, bits, diff, sign), \
413 AD7380_CHANNEL(6, bits, diff, sign), \
414 AD7380_CHANNEL(7, bits, diff, sign), \
418 #define AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign) \ argument
419 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, false)
421 #define ADAQ4380_OFFLOAD_CHANNEL(index, bits, diff, sign) \ argument
422 _AD7380_OFFLOAD_CHANNEL(index, bits, diff, sign, true)
424 #define DEFINE_AD7380_2_OFFLOAD_CHANNEL(name, bits, diff, sign) \ argument
426 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \
427 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \
430 #define DEFINE_AD7380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \ argument
432 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \
433 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \
434 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \
435 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \
438 #define DEFINE_ADAQ4380_4_OFFLOAD_CHANNEL(name, bits, diff, sign) \ argument
440 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \
441 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \
442 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \
443 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \
446 #define DEFINE_AD7380_8_OFFLOAD_CHANNEL(name, bits, diff, sign) \ argument
448 AD7380_OFFLOAD_CHANNEL(0, bits, diff, sign), \
449 AD7380_OFFLOAD_CHANNEL(1, bits, diff, sign), \
450 AD7380_OFFLOAD_CHANNEL(2, bits, diff, sign), \
451 AD7380_OFFLOAD_CHANNEL(3, bits, diff, sign), \
452 AD7380_OFFLOAD_CHANNEL(4, bits, diff, sign), \
453 AD7380_OFFLOAD_CHANNEL(5, bits, diff, sign), \
454 AD7380_OFFLOAD_CHANNEL(6, bits, diff, sign), \
455 AD7380_OFFLOAD_CHANNEL(7, bits, diff, sign), \
479 /* offload channels */
506 "ldo", "vcc", "vlogic", "vs-p", "vs-n", "refin",
517 /* Since this is simultaneous sampling, we don't allow individual channels. */
532 * export 4 channels and ad7386-4/7-4/8-4 export 8 channels.
534 * Inputs AinX0 of multiplexers correspond to the first half of IIO channels
535 * (i.e 0-1 or 0-3) and inputs AinX1 correspond to second half (i.e 2-3 or
536 * 4-7). Example for AD7386/7/8 (2 channels parts):
539 * | +----------------------------
542 * voltage0 | AinA0 --|--->| | | |
543 * | | | mux |----->| ADCA |---
544 * voltage2 | AinA1 --|--->| | | |
548 * voltage1 | AinB0 --|--->| | | |
549 * | | | mux |----->| ADCB |---
550 * voltage3 | AinB1 --|--->| | | |
553 * | +----------------------------
558 * AinX0 and AinX1 channels. From an IIO point of view, we ca enable all
559 * channels, at the cost of an extra read, thus dividing the maximum rate by
606 .channels = ad7380_channels,
619 .channels = ad7381_channels,
632 .channels = ad7383_channels,
647 .channels = ad7384_channels,
662 .channels = ad7386_channels,
676 .channels = ad7387_channels,
690 .channels = ad7388_channels,
703 .name = "ad7380-4",
704 .channels = ad7380_4_channels,
717 .name = "ad7381-4",
718 .channels = ad7381_4_channels,
730 .name = "ad7383-4",
731 .channels = ad7383_4_channels,
745 .name = "ad7384-4",
746 .channels = ad7384_4_channels,
760 .name = "ad7386-4",
761 .channels = ad7386_4_channels,
774 .name = "ad7387-4",
775 .channels = ad7387_4_channels,
788 .name = "ad7388-4",
789 .channels = ad7388_4_channels,
802 .name = "adaq4370-4",
803 .channels = adaq4380_4_channels,
817 .name = "adaq4380-4",
818 .channels = adaq4380_4_channels,
832 .name = "adaq4381-4",
833 .channels = adaq4381_4_channels,
876 * Make the buffer large enough for MAX_NUM_CHANNELS 32-bit samples and
877 * one 64-bit aligned 64-bit timestamp.
894 .tx_buf = &st->tx, in ad7380_regmap_reg_write()
897 st->tx = FIELD_PREP(AD7380_REG_WR, 1) | in ad7380_regmap_reg_write()
901 return spi_sync_transfer(st->spi, &xfer, 1); in ad7380_regmap_reg_write()
913 .tx_buf = &st->tx, in ad7380_regmap_reg_read()
916 .value = st->chip_info->timing_specs->t_csh_ns, in ad7380_regmap_reg_read()
923 .rx_buf = &st->rx, in ad7380_regmap_reg_read()
928 st->tx = FIELD_PREP(AD7380_REG_WR, 0) | in ad7380_regmap_reg_read()
932 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers)); in ad7380_regmap_reg_read()
936 *val = FIELD_GET(AD7380_REG_DATA, st->rx); in ad7380_regmap_reg_read()
975 return -EBUSY; in ad7380_debugfs_reg_access()
978 ret = regmap_read(st->regmap, reg, readval); in ad7380_debugfs_reg_access()
980 ret = regmap_write(st->regmap, reg, writeval); in ad7380_debugfs_reg_access()
988 * ad7380_regval_to_osr - convert OSR register value to ratio
1008 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); in ad7380_get_osr()
1034 if (st->ch == ch) in ad7380_set_ch()
1041 ret = regmap_update_bits(st->regmap, in ad7380_set_ch()
1049 st->ch = ch; in ad7380_set_ch()
1053 T_CONVERT_X_NS * (oversampling_ratio - 1) * in ad7380_set_ch()
1054 st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; in ad7380_set_ch()
1056 return spi_sync_transfer(st->spi, &xfer, 1); in ad7380_set_ch()
1060 * ad7380_update_xfers - update the SPI transfers base on the current scan type
1067 struct spi_transfer *xfer = st->seq ? st->seq_xfer : st->normal_xfer; in ad7380_update_xfers()
1082 (oversampling_ratio - 1) * in ad7380_update_xfers()
1083 st->chip_info->num_simult_channels / AD7380_NUM_SDO_LINES; in ad7380_update_xfers()
1085 if (st->seq) { in ad7380_update_xfers()
1089 scan_type->realbits; in ad7380_update_xfers()
1092 st->chip_info->num_simult_channels; in ad7380_update_xfers()
1103 xfer[1].bits_per_word = scan_type->realbits; in ad7380_update_xfers()
1105 st->chip_info->num_simult_channels; in ad7380_update_xfers()
1121 ret = spi_offload_trigger_validate(st->offload_trigger, &config); in ad7380_set_sample_freq()
1125 st->offload_trigger_hz = config.periodic.frequency_hz; in ad7380_set_sample_freq()
1133 struct spi_transfer *xfer = &st->offload_xfer; in ad7380_init_offload_msg()
1134 struct device *dev = &st->spi->dev; in ad7380_init_offload_msg()
1140 &indio_dev->channels[0]); in ad7380_init_offload_msg()
1144 if (st->chip_info->has_mux) { in ad7380_init_offload_msg()
1153 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, in ad7380_init_offload_msg()
1158 st->seq = true; in ad7380_init_offload_msg()
1170 xfer->bits_per_word = scan_type->realbits; in ad7380_init_offload_msg()
1171 xfer->offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; in ad7380_init_offload_msg()
1172 xfer->len = AD7380_SPI_BYTES(scan_type) * st->chip_info->num_simult_channels; in ad7380_init_offload_msg()
1174 spi_message_init_with_transfers(&st->offload_msg, xfer, 1); in ad7380_init_offload_msg()
1175 st->offload_msg.offload = st->offload; in ad7380_init_offload_msg()
1177 ret = spi_optimize_message(st->spi, &st->offload_msg); in ad7380_init_offload_msg()
1193 .frequency_hz = st->offload_trigger_hz, in ad7380_offload_buffer_postenable()
1202 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config); in ad7380_offload_buffer_postenable()
1204 spi_unoptimize_message(&st->offload_msg); in ad7380_offload_buffer_postenable()
1214 spi_offload_trigger_disable(st->offload, st->offload_trigger); in ad7380_offload_buffer_predisable()
1215 spi_unoptimize_message(&st->offload_msg); in ad7380_offload_buffer_predisable()
1217 if (st->seq) { in ad7380_offload_buffer_predisable()
1218 ret = regmap_update_bits(st->regmap, in ad7380_offload_buffer_predisable()
1225 st->seq = false; in ad7380_offload_buffer_predisable()
1240 struct spi_message *msg = &st->normal_msg; in ad7380_triggered_buffer_preenable()
1244 * Currently, we always read all channels at the same time. The scan_type in ad7380_triggered_buffer_preenable()
1245 * is the same for all channels, so we just pass the first channel. in ad7380_triggered_buffer_preenable()
1247 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]); in ad7380_triggered_buffer_preenable()
1251 if (st->chip_info->has_mux) { in ad7380_triggered_buffer_preenable()
1259 * IIO channels enabled. Otherwise, CH bit is set. in ad7380_triggered_buffer_preenable()
1267 ret = regmap_update_bits(st->regmap, in ad7380_triggered_buffer_preenable()
1273 msg = &st->seq_msg; in ad7380_triggered_buffer_preenable()
1274 st->seq = true; in ad7380_triggered_buffer_preenable()
1287 return spi_optimize_message(st->spi, msg); in ad7380_triggered_buffer_preenable()
1293 struct spi_message *msg = &st->normal_msg; in ad7380_triggered_buffer_postdisable()
1296 if (st->seq) { in ad7380_triggered_buffer_postdisable()
1297 ret = regmap_update_bits(st->regmap, in ad7380_triggered_buffer_postdisable()
1304 msg = &st->seq_msg; in ad7380_triggered_buffer_postdisable()
1305 st->seq = false; in ad7380_triggered_buffer_postdisable()
1321 struct iio_dev *indio_dev = pf->indio_dev; in ad7380_trigger_handler()
1323 struct spi_message *msg = st->seq ? &st->seq_msg : &st->normal_msg; in ad7380_trigger_handler()
1326 ret = spi_sync(st->spi, msg); in ad7380_trigger_handler()
1330 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan_data, in ad7380_trigger_handler()
1331 pf->timestamp); in ad7380_trigger_handler()
1334 iio_trigger_notify_done(indio_dev->trig); in ad7380_trigger_handler()
1345 if (st->chip_info->has_mux) { in ad7380_read_direct()
1348 if (index >= st->chip_info->num_simult_channels) { in ad7380_read_direct()
1349 index -= st->chip_info->num_simult_channels; in ad7380_read_direct()
1362 ret = spi_sync(st->spi, &st->normal_msg); in ad7380_read_direct()
1366 if (scan_type->realbits > 16) { in ad7380_read_direct()
1367 if (scan_type->sign == 's') in ad7380_read_direct()
1368 *val = sign_extend32(*(u32 *)(st->scan_data + 4 * index), in ad7380_read_direct()
1369 scan_type->realbits - 1); in ad7380_read_direct()
1371 *val = *(u32 *)(st->scan_data + 4 * index) & in ad7380_read_direct()
1372 GENMASK(scan_type->realbits - 1, 0); in ad7380_read_direct()
1374 if (scan_type->sign == 's') in ad7380_read_direct()
1375 *val = sign_extend32(*(u16 *)(st->scan_data + 2 * index), in ad7380_read_direct()
1376 scan_type->realbits - 1); in ad7380_read_direct()
1378 *val = *(u16 *)(st->scan_data + 2 * index) & in ad7380_read_direct()
1379 GENMASK(scan_type->realbits - 1, 0); in ad7380_read_direct()
1401 return -EBUSY; in ad7380_read_raw()
1403 ret = ad7380_read_direct(st, chan->scan_index, in ad7380_read_raw()
1413 * * VREF / 2^N, for pseudo-differential chips in ad7380_read_raw()
1419 if (st->chip_info->has_hardware_gain) in ad7380_read_raw()
1420 *val = mult_frac(st->vref_mv, MILLI, in ad7380_read_raw()
1421 st->gain_milli[chan->scan_index]); in ad7380_read_raw()
1423 *val = st->vref_mv; in ad7380_read_raw()
1424 *val2 = scan_type->realbits - chan->differential; in ad7380_read_raw()
1432 *val = st->vcm_mv[chan->channel] * (1 << scan_type->realbits) in ad7380_read_raw()
1433 / st->vref_mv; in ad7380_read_raw()
1438 return -EBUSY; in ad7380_read_raw()
1449 *val = st->offload_trigger_hz; in ad7380_read_raw()
1452 return -EINVAL; in ad7380_read_raw()
1471 *vals = st->sample_freq_range; in ad7380_read_avail()
1475 return -EINVAL; in ad7380_read_avail()
1480 * ad7380_osr_to_regval - convert ratio to OSR register value
1487 * Returns: register value (0 to 7) or -EINVAL if there is not an exact match
1498 return -EINVAL; in ad7380_osr_to_regval()
1512 ret = regmap_update_bits(st->regmap, in ad7380_set_oversampling_ratio()
1521 st->resolution_boost_enabled = boost; in ad7380_set_oversampling_ratio()
1528 ret = regmap_update_bits(st->regmap, in ad7380_set_oversampling_ratio()
1545 return -EINVAL; in ad7380_write_raw()
1549 return -EBUSY; in ad7380_write_raw()
1557 return -EINVAL; in ad7380_write_raw()
1566 return st->resolution_boost_enabled ? AD7380_SCAN_TYPE_RESOLUTION_BOOST in ad7380_get_current_scan_type()
1579 return -EBUSY; in ad7380_read_event_config()
1581 ret = regmap_read(st->regmap, AD7380_REG_ADDR_CONFIG1, &tmp); in ad7380_read_event_config()
1601 return -EBUSY; in ad7380_write_event_config()
1603 ret = regmap_update_bits(st->regmap, in ad7380_write_event_config()
1627 * The register value is 12-bits and is compared to the most significant in ad7380_get_alert_th()
1631 shift = scan_type->realbits - 12; in ad7380_get_alert_th()
1635 ret = regmap_read(st->regmap, in ad7380_get_alert_th()
1644 ret = regmap_read(st->regmap, in ad7380_get_alert_th()
1653 return -EINVAL; in ad7380_get_alert_th()
1669 return -EBUSY; in ad7380_read_event_value()
1676 return -EINVAL; in ad7380_read_event_value()
1692 * 16-bits internal alert high register. LSB are set to 0xf. in ad7380_set_alert_th()
1707 th = val >> (scan_type->realbits - 12); in ad7380_set_alert_th()
1711 return regmap_write(st->regmap, in ad7380_set_alert_th()
1715 return regmap_write(st->regmap, in ad7380_set_alert_th()
1719 return -EINVAL; in ad7380_set_alert_th()
1735 return -EBUSY; in ad7380_write_event_value()
1742 return -EINVAL; in ad7380_write_event_value()
1763 ret = regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, in ad7380_init()
1772 ret = regmap_set_bits(st->regmap, AD7380_REG_ADDR_CONFIG1, in ad7380_init()
1779 st->ch = 0; in ad7380_init()
1780 st->seq = false; in ad7380_init()
1782 /* SPI 1-wire mode */ in ad7380_init()
1783 return regmap_update_bits(st->regmap, AD7380_REG_ADDR_CONFIG2, in ad7380_init()
1792 struct spi_device *spi = st->spi; in ad7380_probe_spi_offload()
1793 struct device *dev = &spi->dev; in ad7380_probe_spi_offload()
1797 indio_dev->setup_ops = &ad7380_offload_buffer_setup_ops; in ad7380_probe_spi_offload()
1798 indio_dev->channels = st->chip_info->offload_channels; in ad7380_probe_spi_offload()
1800 indio_dev->num_channels--; in ad7380_probe_spi_offload()
1802 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, in ad7380_probe_spi_offload()
1804 if (IS_ERR(st->offload_trigger)) in ad7380_probe_spi_offload()
1805 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), in ad7380_probe_spi_offload()
1808 sample_rate = st->chip_info->max_conversion_rate_hz * in ad7380_probe_spi_offload()
1809 AD7380_NUM_SDO_LINES / st->chip_info->num_simult_channels; in ad7380_probe_spi_offload()
1811 st->sample_freq_range[0] = 1; /* min */ in ad7380_probe_spi_offload()
1812 st->sample_freq_range[1] = 1; /* step */ in ad7380_probe_spi_offload()
1813 st->sample_freq_range[2] = sample_rate; /* max */ in ad7380_probe_spi_offload()
1823 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); in ad7380_probe_spi_offload()
1838 struct device *dev = &spi->dev; in ad7380_probe()
1846 return -ENOMEM; in ad7380_probe()
1849 st->spi = spi; in ad7380_probe()
1850 st->chip_info = spi_get_device_match_data(spi); in ad7380_probe()
1851 if (!st->chip_info) in ad7380_probe()
1852 return dev_err_probe(dev, -EINVAL, "missing match data\n"); in ad7380_probe()
1854 ret = devm_regulator_bulk_get_enable(dev, st->chip_info->num_supplies, in ad7380_probe()
1855 st->chip_info->supplies); in ad7380_probe()
1862 if (st->chip_info->adaq_internal_ref_only) { in ad7380_probe()
1870 st->vref_mv = ADAQ4380_INTERNAL_REF_MV; in ad7380_probe()
1874 } else if (st->chip_info->external_ref_only) { in ad7380_probe()
1880 st->vref_mv = ret / 1000; in ad7380_probe()
1890 if (ret < 0 && ret != -ENODEV) in ad7380_probe()
1894 external_ref_en = ret != -ENODEV; in ad7380_probe()
1895 st->vref_mv = external_ref_en ? ret / 1000 : AD7380_INTERNAL_REF_MV; in ad7380_probe()
1898 if (st->chip_info->num_vcm_supplies > ARRAY_SIZE(st->vcm_mv)) in ad7380_probe()
1899 return dev_err_probe(dev, -EINVAL, in ad7380_probe()
1903 * pseudo-differential chips have common mode supplies for the negative in ad7380_probe()
1906 for (i = 0; i < st->chip_info->num_vcm_supplies; i++) { in ad7380_probe()
1907 const char *vcm = st->chip_info->vcm_supplies[i]; in ad7380_probe()
1915 st->vcm_mv[i] = ret / 1000; in ad7380_probe()
1919 st->gain_milli[i] = AD7380_DEFAULT_GAIN_MILLI; in ad7380_probe()
1921 if (st->chip_info->has_hardware_gain) { in ad7380_probe()
1931 if (channel >= st->chip_info->num_channels - 1) in ad7380_probe()
1932 return dev_err_probe(dev, -EINVAL, in ad7380_probe()
1936 ret = fwnode_property_read_u32(node, "adi,gain-milli", in ad7380_probe()
1938 if (ret && ret != -EINVAL) in ad7380_probe()
1942 if (ret != -EINVAL) { in ad7380_probe()
1949 st->gain_milli[channel] = ad7380_gains[gain_idx]; in ad7380_probe()
1954 st->regmap = devm_regmap_init(dev, NULL, st, &ad7380_regmap_config); in ad7380_probe()
1955 if (IS_ERR(st->regmap)) in ad7380_probe()
1956 return dev_err_probe(dev, PTR_ERR(st->regmap), in ad7380_probe()
1968 * - first, toggle CS (no data xfer) to trigger a conversion in ad7380_probe()
1969 * - then, read data in ad7380_probe()
1971 st->normal_xfer[0].cs_change = 1; in ad7380_probe()
1972 st->normal_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; in ad7380_probe()
1973 st->normal_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; in ad7380_probe()
1974 st->normal_xfer[1].rx_buf = st->scan_data; in ad7380_probe()
1976 spi_message_init_with_transfers(&st->normal_msg, st->normal_xfer, in ad7380_probe()
1977 ARRAY_SIZE(st->normal_xfer)); in ad7380_probe()
1980 * - CS toggle (no data xfer) to get the right point in the sequence in ad7380_probe()
1981 * - CS toggle (no data xfer) to trigger a conversion of AinX0 and in ad7380_probe()
1983 * - 2 data reads, to read AinX0 and AinX1 in ad7380_probe()
1985 st->seq_xfer[0].cs_change = 1; in ad7380_probe()
1986 st->seq_xfer[0].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; in ad7380_probe()
1987 st->seq_xfer[0].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; in ad7380_probe()
1988 st->seq_xfer[1].cs_change = 1; in ad7380_probe()
1989 st->seq_xfer[1].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; in ad7380_probe()
1990 st->seq_xfer[1].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; in ad7380_probe()
1992 st->seq_xfer[2].rx_buf = st->scan_data; in ad7380_probe()
1993 st->seq_xfer[2].cs_change = 1; in ad7380_probe()
1994 st->seq_xfer[2].cs_change_delay.value = st->chip_info->timing_specs->t_csh_ns; in ad7380_probe()
1995 st->seq_xfer[2].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; in ad7380_probe()
1997 spi_message_init_with_transfers(&st->seq_msg, st->seq_xfer, in ad7380_probe()
1998 ARRAY_SIZE(st->seq_xfer)); in ad7380_probe()
2000 indio_dev->channels = st->chip_info->channels; in ad7380_probe()
2001 indio_dev->num_channels = st->chip_info->num_channels; in ad7380_probe()
2002 indio_dev->name = st->chip_info->name; in ad7380_probe()
2003 indio_dev->info = &ad7380_info; in ad7380_probe()
2004 indio_dev->modes = INDIO_DIRECT_MODE; in ad7380_probe()
2005 indio_dev->available_scan_masks = st->chip_info->available_scan_masks; in ad7380_probe()
2007 st->offload = devm_spi_offload_get(dev, spi, &ad7380_offload_config); in ad7380_probe()
2008 ret = PTR_ERR_OR_ZERO(st->offload); in ad7380_probe()
2009 if (ret && ret != -ENODEV) in ad7380_probe()
2013 if (ret == -ENODEV) { in ad7380_probe()
2041 { .compatible = "adi,ad7380-4", .data = &ad7380_4_chip_info },
2042 { .compatible = "adi,ad7381-4", .data = &ad7381_4_chip_info },
2043 { .compatible = "adi,ad7383-4", .data = &ad7383_4_chip_info },
2044 { .compatible = "adi,ad7384-4", .data = &ad7384_4_chip_info },
2045 { .compatible = "adi,ad7386-4", .data = &ad7386_4_chip_info },
2046 { .compatible = "adi,ad7387-4", .data = &ad7387_4_chip_info },
2047 { .compatible = "adi,ad7388-4", .data = &ad7388_4_chip_info },
2048 { .compatible = "adi,adaq4370-4", .data = &adaq4370_4_chip_info },
2049 { .compatible = "adi,adaq4380-4", .data = &adaq4380_4_chip_info },
2050 { .compatible = "adi,adaq4381-4", .data = &adaq4381_4_chip_info },
2062 { "ad7380-4", (kernel_ulong_t)&ad7380_4_chip_info },
2063 { "ad7381-4", (kernel_ulong_t)&ad7381_4_chip_info },
2064 { "ad7383-4", (kernel_ulong_t)&ad7383_4_chip_info },
2065 { "ad7384-4", (kernel_ulong_t)&ad7384_4_chip_info },
2066 { "ad7386-4", (kernel_ulong_t)&ad7386_4_chip_info },
2067 { "ad7387-4", (kernel_ulong_t)&ad7387_4_chip_info },
2068 { "ad7388-4", (kernel_ulong_t)&ad7388_4_chip_info },
2069 { "adaq4370-4", (kernel_ulong_t)&adaq4370_4_chip_info },
2070 { "adaq4380-4", (kernel_ulong_t)&adaq4380_4_chip_info },
2071 { "adaq4381-4", (kernel_ulong_t)&adaq4381_4_chip_info },