Lines Matching +full:1 +full:st
38 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
61 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
62 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
80 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
91 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
110 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
134 #define AD7194_CH_POS(x) (((x) - 1) << 4)
135 #define AD7194_CH_NEG(x) ((x) - 1)
143 #define AD7194_CH_AIN_START 1
161 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
168 #define AD7192_NO_SYNC_FILTER 1
232 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set_syscalib_mode() local
234 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
242 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_get_syscalib_mode() local
244 return st->syscalib_mode[chan->channel]; in ad7192_get_syscalib_mode()
252 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_write_syscalib() local
263 temp = st->syscalib_mode[chan->channel]; in ad7192_write_syscalib()
266 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, in ad7192_write_syscalib()
269 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, in ad7192_write_syscalib()
305 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_channel() local
307 st->conf &= ~AD7192_CONF_CHAN_MASK; in ad7192_set_channel()
308 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel); in ad7192_set_channel()
310 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_channel()
316 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_mode() local
318 st->mode &= ~AD7192_MODE_SEL_MASK; in ad7192_set_mode()
319 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode); in ad7192_set_mode()
321 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_mode()
326 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_append_status() local
327 unsigned int mode = st->mode; in ad7192_append_status()
333 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); in ad7192_append_status()
337 st->mode = mode; in ad7192_append_status()
344 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_disable_all() local
345 u32 conf = st->conf; in ad7192_disable_all()
350 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_disable_all()
354 st->conf = conf; in ad7192_disable_all()
397 static int ad7192_calibrate_all(struct ad7192_state *st) in ad7192_calibrate_all() argument
399 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, in ad7192_calibrate_all()
411 * configuration AD7192_CLK_EXT_MCLK1_2 and position 1, mclk, corresponds to
432 struct ad7192_state *st = clk_hw_to_ad7192(hw); in ad7192_clk_output_is_enabled() local
434 return st->clock_sel == AD7192_CLK_INT_CO; in ad7192_clk_output_is_enabled()
439 struct ad7192_state *st = clk_hw_to_ad7192(hw); in ad7192_clk_prepare() local
442 st->mode &= ~AD7192_MODE_CLKSRC_MASK; in ad7192_clk_prepare()
443 st->mode |= AD7192_CLK_INT_CO; in ad7192_clk_prepare()
445 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_clk_prepare()
449 st->clock_sel = AD7192_CLK_INT_CO; in ad7192_clk_prepare()
456 struct ad7192_state *st = clk_hw_to_ad7192(hw); in ad7192_clk_unprepare() local
459 st->mode &= ~AD7192_MODE_CLKSRC_MASK; in ad7192_clk_unprepare()
460 st->mode |= AD7192_CLK_INT; in ad7192_clk_unprepare()
462 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_clk_unprepare()
466 st->clock_sel = AD7192_CLK_INT; in ad7192_clk_unprepare()
476 static int ad7192_register_clk_provider(struct ad7192_state *st) in ad7192_register_clk_provider() argument
478 struct device *dev = &st->sd.spi->dev; in ad7192_register_clk_provider()
495 st->int_clk_hw.init = &init; in ad7192_register_clk_provider()
496 ret = devm_clk_hw_register(dev, &st->int_clk_hw); in ad7192_register_clk_provider()
501 &st->int_clk_hw); in ad7192_register_clk_provider()
504 static int ad7192_clock_setup(struct ad7192_state *st) in ad7192_clock_setup() argument
506 struct device *dev = &st->sd.spi->dev; in ad7192_clock_setup()
516 st->clock_sel = AD7192_CLK_INT_CO; in ad7192_clock_setup()
517 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
523 st->clock_sel = AD7192_CLK_EXT_MCLK1_2; in ad7192_clock_setup()
524 st->mclk = devm_clk_get_enabled(dev, "mclk"); in ad7192_clock_setup()
525 if (IS_ERR(st->mclk)) in ad7192_clock_setup()
526 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad7192_clock_setup()
529 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
530 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
542 st->clock_sel = AD7192_CLK_INT; in ad7192_clock_setup()
543 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
545 ret = ad7192_register_clk_provider(st); in ad7192_clock_setup()
552 st->clock_sel = AD7192_CLK_EXT_MCLK1_2 + ret; in ad7192_clock_setup()
554 st->mclk = devm_clk_get_enabled(dev, ad7192_clock_names[ret]); in ad7192_clock_setup()
555 if (IS_ERR(st->mclk)) in ad7192_clock_setup()
556 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad7192_clock_setup()
559 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
560 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
569 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_setup() local
576 ret = ad_sd_reset(&st->sd); in ad7192_setup()
582 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); in ad7192_setup()
588 if (id != st->chip_info->chip_id) in ad7192_setup()
590 id, st->chip_info->chip_id); in ad7192_setup()
592 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) | in ad7192_setup()
593 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) | in ad7192_setup()
596 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0); in ad7192_setup()
600 st->mode |= AD7192_MODE_REJ60; in ad7192_setup()
603 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) in ad7192_setup()
604 st->conf |= AD7192_CONF_REFSEL; in ad7192_setup()
606 st->conf &= ~AD7192_CONF_CHOP; in ad7192_setup()
610 st->conf |= AD7192_CONF_BUF; in ad7192_setup()
614 st->conf |= AD7192_CONF_UNIPOLAR; in ad7192_setup()
619 st->conf |= AD7192_CONF_BURN; in ad7192_setup()
625 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_setup()
629 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_setup()
633 ret = ad7192_calibrate_all(st); in ad7192_setup()
638 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { in ad7192_setup()
639 scale_uv = ((u64)st->int_vref_mv * 100000000) in ad7192_setup()
641 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf)); in ad7192_setup()
644 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; in ad7192_setup()
645 st->scale_avail[i][0] = scale_uv; in ad7192_setup()
648 st->oversampling_ratio_avail[0] = 1; in ad7192_setup()
649 st->oversampling_ratio_avail[1] = 2; in ad7192_setup()
650 st->oversampling_ratio_avail[2] = 8; in ad7192_setup()
651 st->oversampling_ratio_avail[3] = 16; in ad7192_setup()
653 st->filter_freq_avail[0][0] = 600; in ad7192_setup()
654 st->filter_freq_avail[1][0] = 800; in ad7192_setup()
655 st->filter_freq_avail[2][0] = 2300; in ad7192_setup()
656 st->filter_freq_avail[3][0] = 2720; in ad7192_setup()
658 st->filter_freq_avail[0][1] = 1000; in ad7192_setup()
659 st->filter_freq_avail[1][1] = 1000; in ad7192_setup()
660 st->filter_freq_avail[2][1] = 1000; in ad7192_setup()
661 st->filter_freq_avail[3][1] = 1000; in ad7192_setup()
671 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_ac_excitation() local
673 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf)); in ad7192_show_ac_excitation()
681 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_bridge_switch() local
684 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon)); in ad7192_show_bridge_switch()
693 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set() local
708 st->gpocon |= AD7192_GPOCON_BPDSW; in ad7192_set()
710 st->gpocon &= ~AD7192_GPOCON_BPDSW; in ad7192_set()
712 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); in ad7192_set()
716 st->conf |= AD7192_CONF_ACX; in ad7192_set()
718 st->conf &= ~AD7192_CONF_ACX; in ad7192_set()
720 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set()
731 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en) in ad7192_compute_f_order() argument
735 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode); in ad7192_compute_f_order()
738 return 1; in ad7192_compute_f_order()
740 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected]; in ad7192_compute_f_order()
743 return AD7192_SYNC3_FILTER + oversampling_ratio - 1; in ad7192_compute_f_order()
745 return AD7192_SYNC4_FILTER + oversampling_ratio - 1; in ad7192_compute_f_order()
748 static int ad7192_get_f_order(struct ad7192_state *st) in ad7192_get_f_order() argument
752 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode); in ad7192_get_f_order()
753 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf); in ad7192_get_f_order()
755 return ad7192_compute_f_order(st, sinc3_en, chop_en); in ad7192_get_f_order()
758 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en, in ad7192_compute_f_adc() argument
761 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en); in ad7192_compute_f_adc()
763 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_compute_f_adc()
764 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); in ad7192_compute_f_adc()
767 static int ad7192_get_f_adc(struct ad7192_state *st) in ad7192_get_f_adc() argument
769 unsigned int f_order = ad7192_get_f_order(st); in ad7192_get_f_adc()
771 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_f_adc()
772 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); in ad7192_get_f_adc()
775 static void ad7192_update_filter_freq_avail(struct ad7192_state *st) in ad7192_update_filter_freq_avail() argument
780 fadc = ad7192_compute_f_adc(st, false, true); in ad7192_update_filter_freq_avail()
781 st->filter_freq_avail[0][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_update_filter_freq_avail()
783 fadc = ad7192_compute_f_adc(st, true, true); in ad7192_update_filter_freq_avail()
784 st->filter_freq_avail[1][0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_update_filter_freq_avail()
786 fadc = ad7192_compute_f_adc(st, false, false); in ad7192_update_filter_freq_avail()
787 st->filter_freq_avail[2][0] = DIV_ROUND_CLOSEST(fadc * 230, 1024); in ad7192_update_filter_freq_avail()
789 fadc = ad7192_compute_f_adc(st, true, false); in ad7192_update_filter_freq_avail()
790 st->filter_freq_avail[3][0] = DIV_ROUND_CLOSEST(fadc * 272, 1024); in ad7192_update_filter_freq_avail()
825 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, in ad7192_set_3db_filter_freq() argument
835 for (i = 0; i < ARRAY_SIZE(st->filter_freq_avail); i++) { in ad7192_set_3db_filter_freq()
836 diff_new = abs(freq - st->filter_freq_avail[i][0]); in ad7192_set_3db_filter_freq()
845 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
847 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
849 case 1: in ad7192_set_3db_filter_freq()
850 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
852 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
855 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
857 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
860 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
862 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
866 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_3db_filter_freq()
870 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_3db_filter_freq()
873 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) in ad7192_get_3db_filter_freq() argument
877 fadc = ad7192_get_f_adc(st); in ad7192_get_3db_filter_freq()
879 if (FIELD_GET(AD7192_CONF_CHOP, st->conf)) in ad7192_get_3db_filter_freq()
881 if (FIELD_GET(AD7192_MODE_SINC3, st->mode)) in ad7192_get_3db_filter_freq()
893 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_read_raw() local
894 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf); in ad7192_read_raw()
895 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf); in ad7192_read_raw()
903 mutex_lock(&st->lock); in ad7192_read_raw()
904 *val = st->scale_avail[gain][0]; in ad7192_read_raw()
905 *val2 = st->scale_avail[gain][1]; in ad7192_read_raw()
906 mutex_unlock(&st->lock); in ad7192_read_raw()
917 *val = -(1 << (chan->scan_type.realbits - 1)); in ad7192_read_raw()
927 if (st->aincom_mv && !chan->differential) in ad7192_read_raw()
928 *val += DIV_ROUND_CLOSEST_ULL((u64)st->aincom_mv * NANO, in ad7192_read_raw()
929 st->scale_avail[gain][1]); in ad7192_read_raw()
939 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024); in ad7192_read_raw()
942 *val = ad7192_get_3db_filter_freq(st); in ad7192_read_raw()
946 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)]; in ad7192_read_raw()
959 struct ad7192_state *st = iio_priv(indio_dev); in __ad7192_write_raw() local
963 guard(mutex)(&st->lock); in __ad7192_write_raw()
967 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { in __ad7192_write_raw()
968 if (val2 != st->scale_avail[i][1]) in __ad7192_write_raw()
971 tmp = st->conf; in __ad7192_write_raw()
972 st->conf &= ~AD7192_CONF_GAIN_MASK; in __ad7192_write_raw()
973 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i); in __ad7192_write_raw()
974 if (tmp == st->conf) in __ad7192_write_raw()
976 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in __ad7192_write_raw()
977 ad7192_calibrate_all(st); in __ad7192_write_raw()
985 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); in __ad7192_write_raw()
986 if (div < 1 || div > 1023) in __ad7192_write_raw()
989 st->mode &= ~AD7192_MODE_RATE_MASK; in __ad7192_write_raw()
990 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); in __ad7192_write_raw()
991 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in __ad7192_write_raw()
992 ad7192_update_filter_freq_avail(st); in __ad7192_write_raw()
995 return ad7192_set_3db_filter_freq(st, val, val2 / 1000); in __ad7192_write_raw()
997 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) { in __ad7192_write_raw()
998 if (val != st->oversampling_ratio_avail[i]) in __ad7192_write_raw()
1001 tmp = st->mode; in __ad7192_write_raw()
1002 st->mode &= ~AD7192_MODE_AVG_MASK; in __ad7192_write_raw()
1003 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i); in __ad7192_write_raw()
1004 if (tmp == st->mode) in __ad7192_write_raw()
1006 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in __ad7192_write_raw()
1007 ad7192_update_filter_freq_avail(st); in __ad7192_write_raw()
1057 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_read_avail() local
1061 *vals = (int *)st->scale_avail; in ad7192_read_avail()
1064 *length = ARRAY_SIZE(st->scale_avail) * 2; in ad7192_read_avail()
1068 *vals = (int *)st->filter_freq_avail; in ad7192_read_avail()
1070 *length = ARRAY_SIZE(st->filter_freq_avail) * 2; in ad7192_read_avail()
1074 *vals = (int *)st->oversampling_ratio_avail; in ad7192_read_avail()
1076 *length = ARRAY_SIZE(st->oversampling_ratio_avail); in ad7192_read_avail()
1086 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_update_scan_mode() local
1087 u32 conf = st->conf; in ad7192_update_scan_mode()
1095 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_update_scan_mode()
1099 st->conf = conf; in ad7192_update_scan_mode()
1136 .differential = ((_channel2) == -1 ? 0 : 1), \
1137 .indexed = 1, \
1166 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
1170 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
1181 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
1184 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
1185 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
1188 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
1196 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
1197 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
1202 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
1254 if (!ad7194_validate_ain_channel(dev, ain[1])) in ad7194_parse_channels()
1257 ain[1]); in ad7194_parse_channels()
1262 ad7194_channels->channel2 = ain[1]; in ad7194_parse_channels()
1263 ad7194_channels->address = AD7194_DIFF_CH(ain[0], ain[1]); in ad7194_parse_channels()
1340 struct ad7192_state *st; in ad7192_probe() local
1347 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); in ad7192_probe()
1351 st = iio_priv(indio_dev); in ad7192_probe()
1353 mutex_init(&st->lock); in ad7192_probe()
1364 st->aincom_mv = ret == -ENODEV ? 0 : ret / MILLI; in ad7192_probe()
1402 st->int_vref_mv = ret == -ENODEV ? avdd_mv : ret / MILLI; in ad7192_probe()
1404 st->chip_info = spi_get_device_match_data(spi); in ad7192_probe()
1405 if (!st->chip_info) in ad7192_probe()
1408 indio_dev->name = st->chip_info->name; in ad7192_probe()
1410 indio_dev->info = st->chip_info->info; in ad7192_probe()
1411 if (st->chip_info->parse_channels) { in ad7192_probe()
1412 ret = st->chip_info->parse_channels(indio_dev); in ad7192_probe()
1416 indio_dev->channels = st->chip_info->channels; in ad7192_probe()
1417 indio_dev->num_channels = st->chip_info->num_channels; in ad7192_probe()
1420 ret = ad_sd_init(&st->sd, indio_dev, spi, st->chip_info->sigma_delta_info); in ad7192_probe()
1428 ret = ad7192_clock_setup(st); in ad7192_probe()