Lines Matching +full:1 +full:st
48 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0)
84 #define AD4130_CONFIG_PGA_MASK GENMASK(3, 1)
89 #define AD4130_FILTER_SELECT_MIN 1
126 #define AD4130_INVALID_SLOT -1
129 [AD4130_STATUS_REG] = 1,
134 [AD4130_ID_REG] = 1,
137 [AD4130_MCLK_COUNT_REG] = 1,
138 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
139 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
140 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
142 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
145 [AD4130_FIFO_STATUS_REG] = 1,
222 AD4130_PIN_FN_DIFF = BIT(1),
313 u8 reg_read_tx_buf[1];
364 .samp_freq_avail_len = 1, \
371 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4, 1, 10),
373 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3, 1, 2047),
374 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1, 2047),
394 static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg, in ad4130_get_reg_size() argument
405 static unsigned int ad4130_data_reg_size(struct ad4130_state *st) in ad4130_data_reg_size() argument
410 ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size); in ad4130_data_reg_size()
417 static unsigned int ad4130_resolution(struct ad4130_state *st) in ad4130_resolution() argument
419 return ad4130_data_reg_size(st) * BITS_PER_BYTE; in ad4130_resolution()
424 struct ad4130_state *st = context; in ad4130_reg_write() local
428 ret = ad4130_get_reg_size(st, reg, &size); in ad4130_reg_write()
432 st->reg_write_tx_buf[0] = reg; in ad4130_reg_write()
436 put_unaligned_be24(val, &st->reg_write_tx_buf[1]); in ad4130_reg_write()
439 put_unaligned_be16(val, &st->reg_write_tx_buf[1]); in ad4130_reg_write()
441 case 1: in ad4130_reg_write()
442 st->reg_write_tx_buf[1] = val; in ad4130_reg_write()
448 return spi_write(st->spi, st->reg_write_tx_buf, size + 1); in ad4130_reg_write()
453 struct ad4130_state *st = context; in ad4130_reg_read() local
456 .tx_buf = st->reg_read_tx_buf, in ad4130_reg_read()
457 .len = sizeof(st->reg_read_tx_buf), in ad4130_reg_read()
460 .rx_buf = st->reg_read_rx_buf, in ad4130_reg_read()
466 ret = ad4130_get_reg_size(st, reg, &size); in ad4130_reg_read()
470 st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg; in ad4130_reg_read()
471 t[1].len = size; in ad4130_reg_read()
473 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); in ad4130_reg_read()
479 *val = get_unaligned_be24(st->reg_read_rx_buf); in ad4130_reg_read()
482 *val = get_unaligned_be16(st->reg_read_rx_buf); in ad4130_reg_read()
484 case 1: in ad4130_reg_read()
485 *val = st->reg_read_rx_buf[0]; in ad4130_reg_read()
503 struct ad4130_state *st = gpiochip_get_data(gc); in ad4130_gpio_init_valid_mask() local
512 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE; in ad4130_gpio_init_valid_mask()
528 struct ad4130_state *st = gpiochip_get_data(gc); in ad4130_gpio_set() local
532 regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask, in ad4130_gpio_set()
536 static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode) in ad4130_set_mode() argument
538 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, in ad4130_set_mode()
543 static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en) in ad4130_set_watermark_interrupt_en() argument
545 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_watermark_interrupt_en()
558 static int ad4130_set_fifo_mode(struct ad4130_state *st, in ad4130_set_fifo_mode() argument
561 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_fifo_mode()
568 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_push_fifo_data() local
569 unsigned int data_reg_size = ad4130_data_reg_size(st); in ad4130_push_fifo_data()
570 unsigned int transfer_len = st->effective_watermark * data_reg_size; in ad4130_push_fifo_data()
571 unsigned int set_size = st->num_enabled_channels * data_reg_size; in ad4130_push_fifo_data()
575 st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark); in ad4130_push_fifo_data()
576 st->fifo_xfer[1].len = transfer_len; in ad4130_push_fifo_data()
578 ret = spi_sync(st->spi, &st->fifo_msg); in ad4130_push_fifo_data()
583 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]); in ad4130_push_fifo_data()
589 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_irq_handler() local
594 complete(&st->completion); in ad4130_irq_handler()
633 static int ad4130_find_slot(struct ad4130_state *st, in ad4130_find_slot() argument
643 struct ad4130_slot_info *slot_info = &st->slots_info[i]; in ad4130_find_slot()
657 slot_info->channels < st->slots_info[*slot].channels) in ad4130_find_slot()
669 static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel) in ad4130_unlink_channel() argument
671 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_unlink_channel()
672 struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot]; in ad4130_unlink_channel()
678 static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot) in ad4130_unlink_slot() argument
683 struct ad4130_chan_info *chan_info = &st->chans_info[i]; in ad4130_unlink_slot()
688 ad4130_unlink_channel(st, i); in ad4130_unlink_slot()
694 static int ad4130_link_channel_slot(struct ad4130_state *st, in ad4130_link_channel_slot() argument
697 struct ad4130_slot_info *slot_info = &st->slots_info[slot]; in ad4130_link_channel_slot()
698 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_link_channel_slot()
701 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), in ad4130_link_channel_slot()
713 static int ad4130_write_slot_setup(struct ad4130_state *st, in ad4130_write_slot_setup() argument
728 ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val); in ad4130_write_slot_setup()
735 ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val); in ad4130_write_slot_setup()
739 memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info)); in ad4130_write_slot_setup()
744 static int ad4130_write_channel_setup(struct ad4130_state *st, in ad4130_write_channel_setup() argument
747 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_write_channel_setup()
756 * 1. Enabled and linked channel with setup changes: in ad4130_write_channel_setup()
784 ad4130_unlink_channel(st, channel); in ad4130_write_channel_setup()
790 /* Cases 1 & 2 */ in ad4130_write_channel_setup()
791 ret = ad4130_find_slot(st, setup_info, &slot, &overwrite); in ad4130_write_channel_setup()
796 /* Case 1 */ in ad4130_write_channel_setup()
797 ad4130_unlink_channel(st, channel); in ad4130_write_channel_setup()
800 ret = ad4130_unlink_slot(st, slot); in ad4130_write_channel_setup()
804 ret = ad4130_write_slot_setup(st, slot, setup_info); in ad4130_write_channel_setup()
809 return ad4130_link_channel_slot(st, channel, slot); in ad4130_write_channel_setup()
812 static int ad4130_set_channel_enable(struct ad4130_state *st, in ad4130_set_channel_enable() argument
815 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_enable()
823 ret = ad4130_write_channel_setup(st, channel, true); in ad4130_set_channel_enable()
828 slot_info = &st->slots_info[chan_info->slot]; in ad4130_set_channel_enable()
830 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), in ad4130_set_channel_enable()
836 slot_info->enabled_channels += status ? 1 : -1; in ad4130_set_channel_enable()
859 * Notice that FS = 1 actually means max ODR, and that ODR decreases by
862 * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=>
863 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
864 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
865 * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div)
870 * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=>
871 * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=>
872 * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR
919 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_set_filter_type() local
921 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_filter_type()
928 guard(mutex)(&st->lock); in ad4130_set_filter_type()
948 ret = ad4130_write_channel_setup(st, channel, false); in ad4130_set_filter_type()
961 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_get_filter_type() local
963 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_get_filter_type()
966 guard(mutex)(&st->lock); in ad4130_get_filter_type()
995 .indexed = 1,
996 .differential = 1,
1010 static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel, in ad4130_set_channel_pga() argument
1013 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_pga()
1019 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && in ad4130_set_channel_pga()
1020 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) in ad4130_set_channel_pga()
1026 guard(mutex)(&st->lock); in ad4130_set_channel_pga()
1033 ret = ad4130_write_channel_setup(st, channel, false); in ad4130_set_channel_pga()
1042 static int ad4130_set_channel_freq(struct ad4130_state *st, in ad4130_set_channel_freq() argument
1045 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_freq()
1050 guard(mutex)(&st->lock); in ad4130_set_channel_freq()
1060 ret = ad4130_write_channel_setup(st, channel, false); in ad4130_set_channel_freq()
1072 struct ad4130_state *st = iio_priv(indio_dev); in _ad4130_read_sample() local
1075 ret = ad4130_set_channel_enable(st, channel, true); in _ad4130_read_sample()
1079 reinit_completion(&st->completion); in _ad4130_read_sample()
1081 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); in _ad4130_read_sample()
1085 ret = wait_for_completion_timeout(&st->completion, in _ad4130_read_sample()
1090 ret = ad4130_set_mode(st, AD4130_MODE_IDLE); in _ad4130_read_sample()
1094 ret = regmap_read(st->regmap, AD4130_DATA_REG, val); in _ad4130_read_sample()
1098 ret = ad4130_set_channel_enable(st, channel, false); in _ad4130_read_sample()
1108 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_read_sample() local
1110 guard(mutex)(&st->lock); in ad4130_read_sample()
1119 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_read_raw() local
1121 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_read_raw()
1133 guard(mutex)(&st->lock); in ad4130_read_raw()
1134 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; in ad4130_read_raw()
1135 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; in ad4130_read_raw()
1140 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0; in ad4130_read_raw()
1144 guard(mutex)(&st->lock); in ad4130_read_raw()
1160 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_read_avail() local
1162 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_read_avail()
1167 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; in ad4130_read_avail()
1168 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; in ad4130_read_avail()
1174 scoped_guard(mutex, &st->lock) { in ad4130_read_avail()
1205 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_write_raw() local
1210 return ad4130_set_channel_pga(st, channel, val, val2); in ad4130_write_raw()
1212 return ad4130_set_channel_freq(st, channel, val, val2); in ad4130_write_raw()
1221 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_reg_access() local
1224 return regmap_read(st->regmap, reg, readval); in ad4130_reg_access()
1226 return regmap_write(st->regmap, reg, writeval); in ad4130_reg_access()
1232 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_update_scan_mode() local
1237 guard(mutex)(&st->lock); in ad4130_update_scan_mode()
1240 ret = ad4130_set_channel_enable(st, channel, true); in ad4130_update_scan_mode()
1247 st->num_enabled_channels = val; in ad4130_update_scan_mode()
1254 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_set_fifo_watermark() local
1261 eff = val * st->num_enabled_channels; in ad4130_set_fifo_watermark()
1267 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels); in ad4130_set_fifo_watermark()
1269 guard(mutex)(&st->lock); in ad4130_set_fifo_watermark()
1271 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_fifo_watermark()
1278 st->effective_watermark = eff; in ad4130_set_fifo_watermark()
1279 st->watermark = val; in ad4130_set_fifo_watermark()
1296 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_buffer_postenable() local
1299 guard(mutex)(&st->lock); in ad4130_buffer_postenable()
1301 ret = ad4130_set_watermark_interrupt_en(st, true); in ad4130_buffer_postenable()
1305 ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); in ad4130_buffer_postenable()
1309 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM); in ad4130_buffer_postenable()
1313 return ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); in ad4130_buffer_postenable()
1318 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_buffer_predisable() local
1322 guard(mutex)(&st->lock); in ad4130_buffer_predisable()
1324 ret = ad4130_set_mode(st, AD4130_MODE_IDLE); in ad4130_buffer_predisable()
1328 ret = irq_set_irq_type(st->spi->irq, st->irq_trigger); in ad4130_buffer_predisable()
1332 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED); in ad4130_buffer_predisable()
1336 ret = ad4130_set_watermark_interrupt_en(st, false); in ad4130_buffer_predisable()
1345 ret = ad4130_set_channel_enable(st, i, false); in ad4130_buffer_predisable()
1361 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev)); in hwfifo_watermark_show() local
1364 guard(mutex)(&st->lock); in hwfifo_watermark_show()
1365 val = st->watermark; in hwfifo_watermark_show()
1373 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev)); in hwfifo_enabled_show() local
1377 ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val); in hwfifo_enabled_show()
1390 return sysfs_emit(buf, "%s\n", "1"); in hwfifo_watermark_min_show()
1428 static int ad4130_get_ref_voltage(struct ad4130_state *st, in ad4130_get_ref_voltage() argument
1433 return regulator_get_voltage(st->regulators[2].consumer); in ad4130_get_ref_voltage()
1435 return regulator_get_voltage(st->regulators[3].consumer); in ad4130_get_ref_voltage()
1437 return regulator_get_voltage(st->regulators[0].consumer); in ad4130_get_ref_voltage()
1439 return st->int_ref_uv; in ad4130_get_ref_voltage()
1445 static int ad4130_parse_fw_setup(struct ad4130_state *st, in ad4130_parse_fw_setup() argument
1449 struct device *dev = &st->spi->dev; in ad4130_parse_fw_setup()
1462 fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp); in ad4130_parse_fw_setup()
1489 st->int_ref_en = true; in ad4130_parse_fw_setup()
1491 ret = ad4130_get_ref_voltage(st, setup_info->ref_sel); in ad4130_parse_fw_setup()
1499 static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin) in ad4130_validate_diff_channel() argument
1501 struct device *dev = &st->spi->dev; in ad4130_validate_diff_channel()
1510 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_diff_channel()
1513 st->pins_fn[pin]); in ad4130_validate_diff_channel()
1515 st->pins_fn[pin] |= AD4130_PIN_FN_DIFF; in ad4130_validate_diff_channel()
1520 static int ad4130_validate_diff_channels(struct ad4130_state *st, in ad4130_validate_diff_channels() argument
1527 ret = ad4130_validate_diff_channel(st, pins[i]); in ad4130_validate_diff_channels()
1535 static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin) in ad4130_validate_excitation_pin() argument
1537 struct device *dev = &st->spi->dev; in ad4130_validate_excitation_pin()
1543 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_excitation_pin()
1546 st->pins_fn[pin]); in ad4130_validate_excitation_pin()
1548 st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION; in ad4130_validate_excitation_pin()
1553 static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin) in ad4130_validate_vbias_pin() argument
1555 struct device *dev = &st->spi->dev; in ad4130_validate_vbias_pin()
1561 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_vbias_pin()
1564 st->pins_fn[pin]); in ad4130_validate_vbias_pin()
1566 st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS; in ad4130_validate_vbias_pin()
1571 static int ad4130_validate_vbias_pins(struct ad4130_state *st, in ad4130_validate_vbias_pins() argument
1577 for (i = 0; i < st->num_vbias_pins; i++) { in ad4130_validate_vbias_pins()
1578 ret = ad4130_validate_vbias_pin(st, pins[i]); in ad4130_validate_vbias_pins()
1589 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_parse_fw_channel() local
1590 unsigned int resolution = ad4130_resolution(st); in ad4130_parse_fw_channel()
1592 struct device *dev = &st->spi->dev; in ad4130_parse_fw_channel()
1601 chan = &st->chans[index]; in ad4130_parse_fw_channel()
1602 chan_info = &st->chans_info[index]; in ad4130_parse_fw_channel()
1618 ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins)); in ad4130_parse_fw_channel()
1623 chan->channel2 = pins[1]; in ad4130_parse_fw_channel()
1625 ret = ad4130_parse_fw_setup(st, child, &chan_info->setup); in ad4130_parse_fw_channel()
1632 ret = ad4130_validate_excitation_pin(st, chan_info->iout0); in ad4130_parse_fw_channel()
1637 fwnode_property_read_u32(child, "adi,excitation-pin-1", in ad4130_parse_fw_channel()
1640 ret = ad4130_validate_excitation_pin(st, chan_info->iout1); in ad4130_parse_fw_channel()
1650 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_parse_fw_children() local
1651 struct device *dev = &st->spi->dev; in ad4130_parse_fw_children()
1654 indio_dev->channels = st->chans; in ad4130_parse_fw_children()
1667 struct ad4130_state *st = iio_priv(indio_dev); in ad4310_parse_fw() local
1668 struct device *dev = &st->spi->dev; in ad4310_parse_fw()
1675 st->mclk = devm_clk_get_optional(dev, "mclk"); in ad4310_parse_fw()
1676 if (IS_ERR(st->mclk)) in ad4310_parse_fw()
1677 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad4310_parse_fw()
1680 st->int_pin_sel = AD4130_INT_PIN_INT; in ad4310_parse_fw()
1686 st->int_pin_sel = i; in ad4310_parse_fw()
1691 if (st->int_pin_sel == AD4130_INT_PIN_DOUT) in ad4310_parse_fw()
1695 if (st->int_pin_sel == AD4130_INT_PIN_P2) in ad4310_parse_fw()
1696 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL; in ad4310_parse_fw()
1705 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ) in ad4310_parse_fw()
1706 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT; in ad4310_parse_fw()
1707 else if (st->mclk) in ad4310_parse_fw()
1708 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT; in ad4310_parse_fw()
1710 st->mclk_sel = AD4130_MCLK_76_8KHZ; in ad4310_parse_fw()
1712 if (st->int_pin_sel == AD4130_INT_PIN_CLK && in ad4310_parse_fw()
1713 st->mclk_sel != AD4130_MCLK_76_8KHZ) in ad4310_parse_fw()
1716 st->mclk_sel, st->int_pin_sel); in ad4310_parse_fw()
1718 st->int_ref_uv = AD4130_INT_REF_2_5V; in ad4310_parse_fw()
1725 avdd_uv = regulator_get_voltage(st->regulators[0].consumer); in ad4310_parse_fw()
1727 st->int_ref_uv = AD4130_INT_REF_1_25V; in ad4310_parse_fw()
1729 st->bipolar = device_property_read_bool(dev, "adi,bipolar"); in ad4310_parse_fw()
1737 st->num_vbias_pins = ret; in ad4310_parse_fw()
1740 st->vbias_pins, in ad4310_parse_fw()
1741 st->num_vbias_pins); in ad4310_parse_fw()
1746 ret = ad4130_validate_vbias_pins(st, st->vbias_pins, in ad4310_parse_fw()
1747 st->num_vbias_pins); in ad4310_parse_fw()
1759 static void ad4130_fill_scale_tbls(struct ad4130_state *st) in ad4130_fill_scale_tbls() argument
1761 unsigned int pow = ad4130_resolution(st) - st->bipolar; in ad4130_fill_scale_tbls()
1768 ret = ad4130_get_ref_voltage(st, i); in ad4130_fill_scale_tbls()
1775 st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI); in ad4130_fill_scale_tbls()
1784 static int ad4130_set_mclk_sel(struct ad4130_state *st, in ad4130_set_mclk_sel() argument
1787 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, in ad4130_set_mclk_sel()
1801 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); in ad4130_int_clk_is_enabled() local
1803 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT; in ad4130_int_clk_is_enabled()
1808 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); in ad4130_int_clk_prepare() local
1811 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT); in ad4130_int_clk_prepare()
1815 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT; in ad4130_int_clk_prepare()
1822 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); in ad4130_int_clk_unprepare() local
1825 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ); in ad4130_int_clk_unprepare()
1829 st->mclk_sel = AD4130_MCLK_76_8KHZ; in ad4130_int_clk_unprepare()
1839 static int ad4130_setup_int_clk(struct ad4130_state *st) in ad4130_setup_int_clk() argument
1841 struct device *dev = &st->spi->dev; in ad4130_setup_int_clk()
1847 if (st->int_pin_sel == AD4130_INT_PIN_CLK || in ad4130_setup_int_clk()
1848 st->mclk_sel != AD4130_MCLK_76_8KHZ) in ad4130_setup_int_clk()
1860 st->int_clk_hw.init = &init; in ad4130_setup_int_clk()
1861 ret = devm_clk_hw_register(dev, &st->int_clk_hw); in ad4130_setup_int_clk()
1866 &st->int_clk_hw); in ad4130_setup_int_clk()
1871 struct ad4130_state *st = iio_priv(indio_dev); in ad4130_setup() local
1872 struct device *dev = &st->spi->dev; in ad4130_setup()
1879 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT) in ad4130_setup()
1882 ret = clk_set_rate(st->mclk, rate); in ad4130_setup()
1886 ret = clk_prepare_enable(st->mclk); in ad4130_setup()
1891 st->mclk); in ad4130_setup()
1895 if (st->int_ref_uv == AD4130_INT_REF_2_5V) in ad4130_setup()
1901 val = FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1); in ad4130_setup()
1902 val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar); in ad4130_setup()
1903 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en); in ad4130_setup()
1905 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel); in ad4130_setup()
1908 ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val); in ad4130_setup()
1918 if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE) in ad4130_setup()
1921 val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel); in ad4130_setup()
1923 ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val); in ad4130_setup()
1928 for (i = 0; i < st->num_vbias_pins; i++) in ad4130_setup()
1929 val |= BIT(st->vbias_pins[i]); in ad4130_setup()
1931 ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val); in ad4130_setup()
1935 ret = regmap_clear_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_setup()
1941 ret = ad4130_set_watermark_interrupt_en(st, false); in ad4130_setup()
1947 struct ad4130_chan_info *chan_info = &st->chans_info[i]; in ad4130_setup()
1948 struct iio_chan_spec *chan = &st->chans[i]; in ad4130_setup()
1956 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val); in ad4130_setup()
1964 static int ad4130_soft_reset(struct ad4130_state *st) in ad4130_soft_reset() argument
1968 ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf)); in ad4130_soft_reset()
1979 struct ad4130_state *st = data; in ad4130_disable_regulators() local
1981 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); in ad4130_disable_regulators()
1988 struct ad4130_state *st; in ad4130_probe() local
1991 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); in ad4130_probe()
1995 st = iio_priv(indio_dev); in ad4130_probe()
1997 memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); in ad4130_probe()
1998 init_completion(&st->completion); in ad4130_probe()
1999 mutex_init(&st->lock); in ad4130_probe()
2000 st->spi = spi; in ad4130_probe()
2007 st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; in ad4130_probe()
2008 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf; in ad4130_probe()
2009 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf); in ad4130_probe()
2010 st->fifo_xfer[1].rx_buf = st->fifo_rx_buf; in ad4130_probe()
2011 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, in ad4130_probe()
2012 ARRAY_SIZE(st->fifo_xfer)); in ad4130_probe()
2018 st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config); in ad4130_probe()
2019 if (IS_ERR(st->regmap)) in ad4130_probe()
2020 return PTR_ERR(st->regmap); in ad4130_probe()
2022 st->regulators[0].supply = "avdd"; in ad4130_probe()
2023 st->regulators[1].supply = "iovdd"; in ad4130_probe()
2024 st->regulators[2].supply = "refin1"; in ad4130_probe()
2025 st->regulators[3].supply = "refin2"; in ad4130_probe()
2027 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), in ad4130_probe()
2028 st->regulators); in ad4130_probe()
2032 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); in ad4130_probe()
2036 ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st); in ad4130_probe()
2041 ret = ad4130_soft_reset(st); in ad4130_probe()
2053 ret = ad4130_setup_int_clk(st); in ad4130_probe()
2057 ad4130_fill_scale_tbls(st); in ad4130_probe()
2059 st->gc.owner = THIS_MODULE; in ad4130_probe()
2060 st->gc.label = AD4130_NAME; in ad4130_probe()
2061 st->gc.base = -1; in ad4130_probe()
2062 st->gc.ngpio = AD4130_MAX_GPIOS; in ad4130_probe()
2063 st->gc.parent = dev; in ad4130_probe()
2064 st->gc.can_sleep = true; in ad4130_probe()
2065 st->gc.init_valid_mask = ad4130_gpio_init_valid_mask; in ad4130_probe()
2066 st->gc.get_direction = ad4130_gpio_get_direction; in ad4130_probe()
2067 st->gc.set = ad4130_gpio_set; in ad4130_probe()
2069 ret = devm_gpiochip_add_data(dev, &st->gc, st); in ad4130_probe()
2093 st->irq_trigger = irq_get_trigger_type(spi->irq); in ad4130_probe()
2094 if (st->irq_trigger & IRQF_TRIGGER_RISING) in ad4130_probe()
2095 st->inv_irq_trigger = IRQF_TRIGGER_FALLING; in ad4130_probe()
2096 else if (st->irq_trigger & IRQF_TRIGGER_FALLING) in ad4130_probe()
2097 st->inv_irq_trigger = IRQF_TRIGGER_RISING; in ad4130_probe()
2100 st->irq_trigger); in ad4130_probe()