271 static int adxl367_set_measure_en(struct adxl367_state *st, bool en)  in adxl367_set_measure_en()  argument
277 	ret = regmap_update_bits(st->regmap, ADXL367_REG_POWER_CTL,  in adxl367_set_measure_en()
294 static void adxl367_scale_act_thresholds(struct adxl367_state *st,  in adxl367_scale_act_thresholds()  argument
298 	st->act_threshold = st->act_threshold  in adxl367_scale_act_thresholds()
301 	st->inact_threshold = st->inact_threshold  in adxl367_scale_act_thresholds()
306 static int _adxl367_set_act_threshold(struct adxl367_state *st,  in _adxl367_set_act_threshold()  argument
316 	st->act_threshold_buf[0] = FIELD_PREP(ADXL367_THRESH_H_MASK,  in _adxl367_set_act_threshold()
319 	st->act_threshold_buf[1] = FIELD_PREP(ADXL367_THRESH_L_MASK,  in _adxl367_set_act_threshold()
323 	ret = regmap_bulk_write(st->regmap, reg, st->act_threshold_buf,  in _adxl367_set_act_threshold()
324 				sizeof(st->act_threshold_buf));  in _adxl367_set_act_threshold()
329 		st->act_threshold = threshold;  in _adxl367_set_act_threshold()
331 		st->inact_threshold = threshold;  in _adxl367_set_act_threshold()
336 static int adxl367_set_act_threshold(struct adxl367_state *st,  in adxl367_set_act_threshold()  argument
342 	guard(mutex)(&st->lock);  in adxl367_set_act_threshold()
344 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_act_threshold()
348 	ret = _adxl367_set_act_threshold(st, act, threshold);  in adxl367_set_act_threshold()
352 	return adxl367_set_measure_en(st, true);  in adxl367_set_act_threshold()
355 static int adxl367_set_act_proc_mode(struct adxl367_state *st,  in adxl367_set_act_proc_mode()  argument
358 	return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,  in adxl367_set_act_proc_mode()
364 static int adxl367_set_act_interrupt_en(struct adxl367_state *st,  in adxl367_set_act_interrupt_en()  argument
370 	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,  in adxl367_set_act_interrupt_en()
374 static int adxl367_get_act_interrupt_en(struct adxl367_state *st,  in adxl367_get_act_interrupt_en()  argument
382 	ret = regmap_read(st->regmap, ADXL367_REG_INT1_MAP, &val);  in adxl367_get_act_interrupt_en()
391 static int adxl367_set_act_en(struct adxl367_state *st,  in adxl367_set_act_en()  argument
397 	return regmap_update_bits(st->regmap, ADXL367_REG_ACT_INACT_CTL,  in adxl367_set_act_en()
402 static int adxl367_set_fifo_watermark_interrupt_en(struct adxl367_state *st,  in adxl367_set_fifo_watermark_interrupt_en()  argument
405 	return regmap_update_bits(st->regmap, ADXL367_REG_INT1_MAP,  in adxl367_set_fifo_watermark_interrupt_en()
410 static int adxl367_get_fifo_mode(struct adxl367_state *st,  in adxl367_get_fifo_mode()  argument
416 	ret = regmap_read(st->regmap, ADXL367_REG_FIFO_CTL, &val);  in adxl367_get_fifo_mode()
425 static int adxl367_set_fifo_mode(struct adxl367_state *st,  in adxl367_set_fifo_mode()  argument
428 	return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_mode()
434 static int adxl367_set_fifo_format(struct adxl367_state *st,  in adxl367_set_fifo_format()  argument
437 	return regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_format()
443 static int adxl367_set_fifo_watermark(struct adxl367_state *st,  in adxl367_set_fifo_watermark()  argument
446 	unsigned int fifo_samples = fifo_watermark * st->fifo_set_size;  in adxl367_set_fifo_watermark()
453 	fifo_samples /= st->fifo_set_size;  in adxl367_set_fifo_watermark()
462 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_CTL,  in adxl367_set_fifo_watermark()
467 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FIFO_SAMPLES,  in adxl367_set_fifo_watermark()
472 	st->fifo_watermark = fifo_watermark;  in adxl367_set_fifo_watermark()
480 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_set_range()  local
483 	guard(mutex)(&st->lock);  in adxl367_set_range()
485 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_range()
489 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,  in adxl367_set_range()
496 	adxl367_scale_act_thresholds(st, st->range, range);  in adxl367_set_range()
499 	ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,  in adxl367_set_range()
500 					 st->act_threshold);  in adxl367_set_range()
504 	ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,  in adxl367_set_range()
505 					 st->inact_threshold);  in adxl367_set_range()
509 	ret = adxl367_set_measure_en(st, true);  in adxl367_set_range()
513 	st->range = range;  in adxl367_set_range()
518 static int adxl367_time_ms_to_samples(struct adxl367_state *st, unsigned int ms)  in adxl367_time_ms_to_samples()  argument
520 	int freq_hz = adxl367_samp_freq_tbl[st->odr][0];  in adxl367_time_ms_to_samples()
521 	int freq_microhz = adxl367_samp_freq_tbl[st->odr][1];  in adxl367_time_ms_to_samples()
528 static int _adxl367_set_act_time_ms(struct adxl367_state *st, unsigned int ms)  in _adxl367_set_act_time_ms()  argument
530 	unsigned int val = adxl367_time_ms_to_samples(st, ms);  in _adxl367_set_act_time_ms()
536 	ret = regmap_write(st->regmap, ADXL367_REG_TIME_ACT, val);  in _adxl367_set_act_time_ms()
540 	st->act_time_ms = ms;  in _adxl367_set_act_time_ms()
545 static int _adxl367_set_inact_time_ms(struct adxl367_state *st, unsigned int ms)  in _adxl367_set_inact_time_ms()  argument
547 	unsigned int val = adxl367_time_ms_to_samples(st, ms);  in _adxl367_set_inact_time_ms()
553 	st->inact_time_buf[0] = FIELD_PREP(ADXL367_TIME_INACT_H_MASK,  in _adxl367_set_inact_time_ms()
556 	st->inact_time_buf[1] = FIELD_PREP(ADXL367_TIME_INACT_L_MASK,  in _adxl367_set_inact_time_ms()
560 	ret = regmap_bulk_write(st->regmap, ADXL367_REG_TIME_INACT_H,  in _adxl367_set_inact_time_ms()
561 				st->inact_time_buf, sizeof(st->inact_time_buf));  in _adxl367_set_inact_time_ms()
565 	st->inact_time_ms = ms;  in _adxl367_set_inact_time_ms()
570 static int adxl367_set_act_time_ms(struct adxl367_state *st,  in adxl367_set_act_time_ms()  argument
576 	guard(mutex)(&st->lock);  in adxl367_set_act_time_ms()
578 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_act_time_ms()
583 		ret = _adxl367_set_act_time_ms(st, ms);  in adxl367_set_act_time_ms()
585 		ret = _adxl367_set_inact_time_ms(st, ms);  in adxl367_set_act_time_ms()
590 	return adxl367_set_measure_en(st, true);  in adxl367_set_act_time_ms()
593 static int _adxl367_set_odr(struct adxl367_state *st, enum adxl367_odr odr)  in _adxl367_set_odr()  argument
597 	ret = regmap_update_bits(st->regmap, ADXL367_REG_FILTER_CTL,  in _adxl367_set_odr()
604 	st->odr = odr;  in _adxl367_set_odr()
607 	ret = _adxl367_set_act_time_ms(st, st->act_time_ms);  in _adxl367_set_odr()
611 	return _adxl367_set_inact_time_ms(st, st->inact_time_ms);  in _adxl367_set_odr()
616 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_set_odr()  local
619 	guard(mutex)(&st->lock);  in adxl367_set_odr()
621 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_odr()
625 	ret = _adxl367_set_odr(st, odr);  in adxl367_set_odr()
629 	return adxl367_set_measure_en(st, true);  in adxl367_set_odr()
632 static int adxl367_set_temp_adc_en(struct adxl367_state *st, unsigned int reg,  in adxl367_set_temp_adc_en()  argument
635 	return regmap_update_bits(st->regmap, reg, ADXL367_ADC_EN_MASK,  in adxl367_set_temp_adc_en()
639 static int adxl367_set_temp_adc_reg_en(struct adxl367_state *st,  in adxl367_set_temp_adc_reg_en()  argument
646 		ret = adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);  in adxl367_set_temp_adc_reg_en()
649 		ret = adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);  in adxl367_set_temp_adc_reg_en()
664 static int adxl367_set_temp_adc_mask_en(struct adxl367_state *st,  in adxl367_set_temp_adc_mask_en()  argument
669 		return adxl367_set_temp_adc_en(st, ADXL367_REG_TEMP_CTL, en);  in adxl367_set_temp_adc_mask_en()
671 		return adxl367_set_temp_adc_en(st, ADXL367_REG_ADC_CTL, en);  in adxl367_set_temp_adc_mask_en()
676 static int adxl367_find_odr(struct adxl367_state *st, int val, int val2,  in adxl367_find_odr()  argument
695 static int adxl367_find_range(struct adxl367_state *st, int val, int val2,  in adxl367_find_range()  argument
718 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_sample()  local
722 	guard(mutex)(&st->lock);  in adxl367_read_sample()
724 	ret = adxl367_set_temp_adc_reg_en(st, chan->address, true);  in adxl367_read_sample()
728 	ret = regmap_bulk_read(st->regmap, chan->address, &st->sample_buf,  in adxl367_read_sample()
729 			       sizeof(st->sample_buf));  in adxl367_read_sample()
733 	sample = FIELD_GET(ADXL367_DATA_MASK, be16_to_cpu(st->sample_buf));  in adxl367_read_sample()
736 	ret = adxl367_set_temp_adc_reg_en(st, chan->address, false);  in adxl367_read_sample()
743 static int adxl367_get_status(struct adxl367_state *st, u8 *status,  in adxl367_get_status()  argument
749 	ret = regmap_bulk_read(st->regmap, ADXL367_REG_STATUS,  in adxl367_get_status()
750 			       st->status_buf, sizeof(st->status_buf));  in adxl367_get_status()
754 	st->status_buf[2] &= ADXL367_FIFO_ENT_H_MASK;  in adxl367_get_status()
756 	*status = st->status_buf[0];  in adxl367_get_status()
757 	*fifo_entries = get_unaligned_le16(&st->status_buf[1]);  in adxl367_get_status()
784 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_push_fifo_data()  local
791 	fifo_entries -= fifo_entries % st->fifo_set_size;  in adxl367_push_fifo_data()
793 	ret = st->ops->read_fifo(st->context, st->fifo_buf, fifo_entries);  in adxl367_push_fifo_data()
795 		dev_err(st->dev, "Failed to read FIFO: %d\n", ret);  in adxl367_push_fifo_data()
799 	for (i = 0; i < fifo_entries; i += st->fifo_set_size)  in adxl367_push_fifo_data()
800 		iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);  in adxl367_push_fifo_data()
808 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_irq_handler()  local
814 	ret = adxl367_get_status(st, &status, &fifo_entries);  in adxl367_irq_handler()
829 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_reg_access()  local
832 		return regmap_read(st->regmap, reg, readval);  in adxl367_reg_access()
834 		return regmap_write(st->regmap, reg, writeval);  in adxl367_reg_access()
841 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_raw()  local
854 			guard(mutex)(&st->lock);  in adxl367_read_raw()
855 			*val = adxl367_range_scale_tbl[st->range][0];  in adxl367_read_raw()
856 			*val2 = adxl367_range_scale_tbl[st->range][1];  in adxl367_read_raw()
882 		guard(mutex)(&st->lock);  in adxl367_read_raw()
883 		*val = adxl367_samp_freq_tbl[st->odr][0];  in adxl367_read_raw()
884 		*val2 = adxl367_samp_freq_tbl[st->odr][1];  in adxl367_read_raw()
896 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_write_raw()  local
903 		ret = adxl367_find_odr(st, val, val2, &odr);  in adxl367_write_raw()
917 		ret = adxl367_find_range(st, val, val2, &range);  in adxl367_write_raw()
979 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_event_value()  local
981 	guard(mutex)(&st->lock);  in adxl367_read_event_value()
986 			*val = st->act_threshold;  in adxl367_read_event_value()
989 			*val = st->inact_threshold;  in adxl367_read_event_value()
998 			*val = st->act_time_ms;  in adxl367_read_event_value()
1002 			*val = st->inact_time_ms;  in adxl367_read_event_value()
1020 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_write_event_value()  local
1029 			return adxl367_set_act_threshold(st, ADXL367_ACTIVITY, val);  in adxl367_write_event_value()
1031 			return adxl367_set_act_threshold(st, ADXL367_INACTIVITY, val);  in adxl367_write_event_value()
1042 			return adxl367_set_act_time_ms(st, ADXL367_ACTIVITY, val);  in adxl367_write_event_value()
1044 			return adxl367_set_act_time_ms(st, ADXL367_INACTIVITY, val);  in adxl367_write_event_value()
1058 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_read_event_config()  local
1064 		ret = adxl367_get_act_interrupt_en(st, ADXL367_ACTIVITY, &en);  in adxl367_read_event_config()
1067 		ret = adxl367_get_act_interrupt_en(st, ADXL367_INACTIVITY, &en);  in adxl367_read_event_config()
1080 	struct adxl367_state *st = iio_priv(indio_dev);  in __adxl367_write_event_config()  local
1095 	guard(mutex)(&st->lock);  in __adxl367_write_event_config()
1097 	ret = adxl367_set_measure_en(st, false);  in __adxl367_write_event_config()
1101 	ret = adxl367_set_act_interrupt_en(st, act, state);  in __adxl367_write_event_config()
1105 	ret = adxl367_set_act_en(st, act, state ? ADCL367_ACT_REF_ENABLED  in __adxl367_write_event_config()
1110 	return adxl367_set_measure_en(st, true);  in __adxl367_write_event_config()
1133 	struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));  in adxl367_get_fifo_enabled()  local
1137 	ret = adxl367_get_fifo_mode(st, &fifo_mode);  in adxl367_get_fifo_enabled()
1148 	struct adxl367_state *st = iio_priv(dev_to_iio_dev(dev));  in adxl367_get_fifo_watermark()  local
1151 	guard(mutex)(&st->lock);  in adxl367_get_fifo_watermark()
1152 	fifo_watermark = st->fifo_watermark;  in adxl367_get_fifo_watermark()
1175 	struct adxl367_state *st  = iio_priv(indio_dev);  in adxl367_set_watermark()  local
1181 	guard(mutex)(&st->lock);  in adxl367_set_watermark()
1183 	ret = adxl367_set_measure_en(st, false);  in adxl367_set_watermark()
1187 	ret = adxl367_set_fifo_watermark(st, val);  in adxl367_set_watermark()
1191 	return adxl367_set_measure_en(st, true);  in adxl367_set_watermark()
1215 	struct adxl367_state *st  = iio_priv(indio_dev);  in adxl367_update_scan_mode()  local
1222 	guard(mutex)(&st->lock);  in adxl367_update_scan_mode()
1224 	ret = adxl367_set_measure_en(st, false);  in adxl367_update_scan_mode()
1228 	ret = adxl367_set_fifo_format(st, fifo_format);  in adxl367_update_scan_mode()
1232 	ret = adxl367_set_measure_en(st, true);  in adxl367_update_scan_mode()
1236 	st->fifo_set_size = bitmap_weight(active_scan_mask,  in adxl367_update_scan_mode()
1244 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_buffer_postenable()  local
1247 	guard(mutex)(&st->lock);  in adxl367_buffer_postenable()
1249 	ret = adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,  in adxl367_buffer_postenable()
1254 	ret = adxl367_set_measure_en(st, false);  in adxl367_buffer_postenable()
1258 	ret = adxl367_set_fifo_watermark_interrupt_en(st, true);  in adxl367_buffer_postenable()
1262 	ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_STREAM);  in adxl367_buffer_postenable()
1266 	return adxl367_set_measure_en(st, true);  in adxl367_buffer_postenable()
1271 	struct adxl367_state *st = iio_priv(indio_dev);  in adxl367_buffer_predisable()  local
1274 	guard(mutex)(&st->lock);  in adxl367_buffer_predisable()
1276 	ret = adxl367_set_measure_en(st, false);  in adxl367_buffer_predisable()
1280 	ret = adxl367_set_fifo_mode(st, ADXL367_FIFO_MODE_DISABLED);  in adxl367_buffer_predisable()
1284 	ret = adxl367_set_fifo_watermark_interrupt_en(st, false);  in adxl367_buffer_predisable()
1288 	ret = adxl367_set_measure_en(st, true);  in adxl367_buffer_predisable()
1292 	return adxl367_set_temp_adc_mask_en(st, indio_dev->active_scan_mask,  in adxl367_buffer_predisable()
1380 static int adxl367_verify_devid(struct adxl367_state *st)  in adxl367_verify_devid()  argument
1385 	ret = regmap_read(st->regmap, ADXL367_REG_DEVID, &val);  in adxl367_verify_devid()
1387 		return dev_err_probe(st->dev, ret, "Failed to read dev id\n");  in adxl367_verify_devid()
1390 		return dev_err_probe(st->dev, -ENODEV,  in adxl367_verify_devid()
1397 static int adxl367_setup(struct adxl367_state *st)  in adxl367_setup()  argument
1401 	ret = _adxl367_set_act_threshold(st, ADXL367_ACTIVITY,  in adxl367_setup()
1406 	ret = _adxl367_set_act_threshold(st, ADXL367_INACTIVITY,  in adxl367_setup()
1411 	ret = adxl367_set_act_proc_mode(st, ADXL367_LOOPED);  in adxl367_setup()
1415 	ret = _adxl367_set_odr(st, ADXL367_ODR_400HZ);  in adxl367_setup()
1419 	ret = _adxl367_set_act_time_ms(st, 10);  in adxl367_setup()
1423 	ret = _adxl367_set_inact_time_ms(st, 10000);  in adxl367_setup()
1427 	return adxl367_set_measure_en(st, true);  in adxl367_setup()
1435 	struct adxl367_state *st;  in adxl367_probe()  local
1438 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));  in adxl367_probe()
1442 	st = iio_priv(indio_dev);  in adxl367_probe()
1443 	st->dev = dev;  in adxl367_probe()
1444 	st->regmap = regmap;  in adxl367_probe()
1445 	st->context = context;  in adxl367_probe()
1446 	st->ops = ops;  in adxl367_probe()
1448 	mutex_init(&st->lock);  in adxl367_probe()
1457 	ret = devm_regulator_bulk_get_enable(st->dev,  in adxl367_probe()
1461 		return dev_err_probe(st->dev, ret,  in adxl367_probe()
1464 	ret = regmap_write(st->regmap, ADXL367_REG_RESET, ADXL367_RESET_CODE);  in adxl367_probe()
1470 	ret = adxl367_verify_devid(st);  in adxl367_probe()
1474 	ret = adxl367_setup(st);  in adxl367_probe()
1478 	ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev,  in adxl367_probe()
1484 	ret = devm_request_threaded_irq(st->dev, irq, NULL,  in adxl367_probe()
1488 		return dev_err_probe(st->dev, ret, "Failed to request irq\n");  in adxl367_probe()