Lines Matching +full:i3c +full:- +full:master
1 // SPDX-License-Identifier: GPL-2.0
3 * Silvaco dual-role I3C master driver
14 #include <linux/i3c/master.h>
24 /* Master Mode Registers */
141 * I3C HW stalls the write transfer if the transmit FIFO becomes empty,
142 * when new data is written to FIFO, I3C HW resumes the transfer but
150 * I3C HW may generate an invalid SlvStart event when emitting a STOP.
157 * corrupted and results in a no repeated-start condition at the end of
195 * struct svc_i3c_master - Silvaco I3C Master structure
196 * @base: I3C master controller
203 * @hj_work: Hot-join work
218 * @lock: Transfer lock, protect between IBI work thread and callbacks from master
257 * struct svc_i3c_i2c_dev_data - Device specific data
258 * @index: Index in the master tables corresponding to this device
259 * @ibi: IBI slot index in the master structure
268 static inline bool svc_has_quirk(struct svc_i3c_master *master, u32 quirk) in svc_has_quirk() argument
270 return (master->drvdata->quirks & quirk); in svc_has_quirk()
273 static inline bool svc_has_daa_corrupt(struct svc_i3c_master *master) in svc_has_daa_corrupt() argument
275 return ((master->drvdata->quirks & SVC_I3C_QUIRK_DAA_CORRUPT) && in svc_has_daa_corrupt()
276 !(master->mctrl_config & in svc_has_daa_corrupt()
280 static inline bool is_events_enabled(struct svc_i3c_master *master, u32 mask) in is_events_enabled() argument
282 return !!(master->enabled_events & mask); in is_events_enabled()
285 static bool svc_i3c_master_error(struct svc_i3c_master *master) in svc_i3c_master_error() argument
289 mstatus = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_error()
291 merrwarn = readl(master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_error()
292 writel(merrwarn, master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_error()
296 dev_dbg(master->dev, "Warning condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n", in svc_i3c_master_error()
301 dev_err(master->dev, in svc_i3c_master_error()
311 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask) in svc_i3c_master_enable_interrupts() argument
313 writel(mask, master->regs + SVC_I3C_MINTSET); in svc_i3c_master_enable_interrupts()
316 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master) in svc_i3c_master_disable_interrupts() argument
318 u32 mask = readl(master->regs + SVC_I3C_MINTSET); in svc_i3c_master_disable_interrupts()
320 writel(mask, master->regs + SVC_I3C_MINTCLR); in svc_i3c_master_disable_interrupts()
323 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master) in svc_i3c_master_clear_merrwarn() argument
326 writel(readl(master->regs + SVC_I3C_MERRWARN), in svc_i3c_master_clear_merrwarn()
327 master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_clear_merrwarn()
330 static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master) in svc_i3c_master_flush_fifo() argument
334 master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_flush_fifo()
337 static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master) in svc_i3c_master_reset_fifo_trigger() argument
347 writel(reg, master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_reset_fifo_trigger()
350 static void svc_i3c_master_reset(struct svc_i3c_master *master) in svc_i3c_master_reset() argument
352 svc_i3c_master_clear_merrwarn(master); in svc_i3c_master_reset()
353 svc_i3c_master_reset_fifo_trigger(master); in svc_i3c_master_reset()
354 svc_i3c_master_disable_interrupts(master); in svc_i3c_master_reset()
358 to_svc_i3c_master(struct i3c_master_controller *master) in to_svc_i3c_master() argument
360 return container_of(master, struct svc_i3c_master, base); in to_svc_i3c_master()
365 struct svc_i3c_master *master; in svc_i3c_master_hj_work() local
367 master = container_of(work, struct svc_i3c_master, hj_work); in svc_i3c_master_hj_work()
368 i3c_master_do_daa(&master->base); in svc_i3c_master_hj_work()
372 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master, in svc_i3c_master_dev_from_addr() argument
378 if (master->addrs[i] == ibiaddr) in svc_i3c_master_dev_from_addr()
384 return master->descs[i]; in svc_i3c_master_dev_from_addr()
387 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master) in svc_i3c_master_emit_stop() argument
389 writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL); in svc_i3c_master_emit_stop()
400 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master, in svc_i3c_master_handle_ibi() argument
410 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); in svc_i3c_master_handle_ibi()
412 return -ENOSPC; in svc_i3c_master_handle_ibi()
414 slot->len = 0; in svc_i3c_master_handle_ibi()
415 buf = slot->data; in svc_i3c_master_handle_ibi()
417 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, in svc_i3c_master_handle_ibi()
420 dev_err(master->dev, "Timeout when polling for COMPLETE\n"); in svc_i3c_master_handle_ibi()
424 while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) && in svc_i3c_master_handle_ibi()
425 slot->len < SVC_I3C_FIFO_SIZE) { in svc_i3c_master_handle_ibi()
426 mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_handle_ibi()
428 readsb(master->regs + SVC_I3C_MRDATAB, buf, count); in svc_i3c_master_handle_ibi()
429 slot->len += count; in svc_i3c_master_handle_ibi()
433 master->ibi.tbq_slot = slot; in svc_i3c_master_handle_ibi()
438 static int svc_i3c_master_ack_ibi(struct svc_i3c_master *master, in svc_i3c_master_ack_ibi() argument
450 writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL); in svc_i3c_master_ack_ibi()
452 return readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_ack_ibi()
457 static int svc_i3c_master_nack_ibi(struct svc_i3c_master *master) in svc_i3c_master_nack_ibi() argument
464 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_nack_ibi()
466 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_nack_ibi()
471 static int svc_i3c_master_handle_ibi_won(struct svc_i3c_master *master, u32 mstatus) in svc_i3c_master_handle_ibi_won() argument
478 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_handle_ibi_won()
480 /* Hardware can't auto emit NACK for hot join and master request */ in svc_i3c_master_handle_ibi_won()
484 ret = svc_i3c_master_nack_ibi(master); in svc_i3c_master_handle_ibi_won()
492 struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work); in svc_i3c_master_ibi_work() local
500 * According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5: in svc_i3c_master_ibi_work()
502 * The I3C Controller shall hold SCL low while the Bus is in ACK/NACK Phase of I3C/I2C in svc_i3c_master_ibi_work()
504 * schedule during the whole I3C transaction, otherwise, the I3C bus timeout may happen if in svc_i3c_master_ibi_work()
507 guard(spinlock_irqsave)(&master->xferqueue.lock); in svc_i3c_master_ibi_work()
520 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_ibi_work()
525 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_ibi_work()
528 ret = readl_relaxed_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, val, in svc_i3c_master_ibi_work()
531 dev_err(master->dev, "Timeout when polling for IBIWON\n"); in svc_i3c_master_ibi_work()
532 svc_i3c_master_emit_stop(master); in svc_i3c_master_ibi_work()
536 status = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_ibi_work()
543 dev = svc_i3c_master_dev_from_addr(master, ibiaddr); in svc_i3c_master_ibi_work()
544 if (!dev || !is_events_enabled(master, SVC_I3C_EVENT_IBI)) in svc_i3c_master_ibi_work()
545 svc_i3c_master_nack_ibi(master); in svc_i3c_master_ibi_work()
547 svc_i3c_master_handle_ibi(master, dev); in svc_i3c_master_ibi_work()
550 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN)) in svc_i3c_master_ibi_work()
551 svc_i3c_master_ack_ibi(master, false); in svc_i3c_master_ibi_work()
553 svc_i3c_master_nack_ibi(master); in svc_i3c_master_ibi_work()
556 svc_i3c_master_nack_ibi(master); in svc_i3c_master_ibi_work()
567 if (svc_i3c_master_error(master)) { in svc_i3c_master_ibi_work()
568 if (master->ibi.tbq_slot) { in svc_i3c_master_ibi_work()
570 i3c_generic_ibi_recycle_slot(data->ibi_pool, in svc_i3c_master_ibi_work()
571 master->ibi.tbq_slot); in svc_i3c_master_ibi_work()
572 master->ibi.tbq_slot = NULL; in svc_i3c_master_ibi_work()
575 svc_i3c_master_emit_stop(master); in svc_i3c_master_ibi_work()
584 i3c_master_queue_ibi(dev, master->ibi.tbq_slot); in svc_i3c_master_ibi_work()
585 master->ibi.tbq_slot = NULL; in svc_i3c_master_ibi_work()
587 svc_i3c_master_emit_stop(master); in svc_i3c_master_ibi_work()
590 svc_i3c_master_emit_stop(master); in svc_i3c_master_ibi_work()
591 if (is_events_enabled(master, SVC_I3C_EVENT_HOTJOIN)) in svc_i3c_master_ibi_work()
592 queue_work(master->base.wq, &master->hj_work); in svc_i3c_master_ibi_work()
595 svc_i3c_master_emit_stop(master); in svc_i3c_master_ibi_work()
602 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); in svc_i3c_master_ibi_work()
607 struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id; in svc_i3c_master_irq_handler() local
608 u32 active = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_irq_handler()
614 writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_irq_handler()
617 if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART) && in svc_i3c_master_irq_handler()
621 svc_i3c_master_disable_interrupts(master); in svc_i3c_master_irq_handler()
624 queue_work(master->base.wq, &master->ibi_work); in svc_i3c_master_irq_handler()
632 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_set_speed() local
633 struct i3c_bus *bus = i3c_master_get_bus(&master->base); in svc_i3c_master_set_speed()
638 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_set_speed()
640 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_set_speed()
646 fclk_rate = clk_get_rate(master->fclk); in svc_i3c_master_set_speed()
648 ret = -EINVAL; in svc_i3c_master_set_speed()
652 * Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first in svc_i3c_master_set_speed()
653 * broadcast address is visible to all I2C/I3C devices on the I3C bus. in svc_i3c_master_set_speed()
654 * I3C device working as a I2C device will turn off its 50ns Spike in svc_i3c_master_set_speed()
655 * Filter to change to I3C mode. in svc_i3c_master_set_speed()
657 mconfig = master->mctrl_config; in svc_i3c_master_set_speed()
660 odbaud = DIV_ROUND_UP(fclk_rate, bus->scl_rate.i2c * (2 + 2 * ppbaud)) - 1; in svc_i3c_master_set_speed()
663 writel(mconfig, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_set_speed()
666 writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_set_speed()
671 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_set_speed()
672 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_set_speed()
679 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_bus_init() local
688 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_bus_init()
690 dev_err(master->dev, in svc_i3c_master_bus_init()
691 "<%s> cannot resume i3c bus master, err: %d\n", in svc_i3c_master_bus_init()
697 fclk_rate = clk_get_rate(master->fclk); in svc_i3c_master_bus_init()
699 ret = -EINVAL; in svc_i3c_master_bus_init()
704 i2c_period_ns = DIV_ROUND_UP(1000000000, bus->scl_rate.i2c); in svc_i3c_master_bus_init()
705 i2c_scl_rate = bus->scl_rate.i2c; in svc_i3c_master_bus_init()
706 i3c_scl_rate = bus->scl_rate.i3c; in svc_i3c_master_bus_init()
709 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period. in svc_i3c_master_bus_init()
710 * Simplest configuration is using a 50% duty-cycle of 40ns. in svc_i3c_master_bus_init()
712 ppbaud = DIV_ROUND_UP(fclk_rate / 2, i3c_scl_rate) - 1; in svc_i3c_master_bus_init()
716 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a in svc_i3c_master_bus_init()
717 * duty-cycle tuned so that high levels are filetered out by in svc_i3c_master_bus_init()
722 odbaud = DIV_ROUND_UP(fclk_rate, SVC_I3C_QUICK_I2C_CLK * (1 + ppbaud)) - 2; in svc_i3c_master_bus_init()
725 switch (bus->mode) { in svc_i3c_master_bus_init()
735 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2; in svc_i3c_master_bus_init()
740 /* I3C PP + I3C OP + I2C OP both use i2c clk rate */ in svc_i3c_master_bus_init()
743 pplow = DIV_ROUND_UP(fclk_rate, i3c_scl_rate) - (2 + 2 * ppbaud); in svc_i3c_master_bus_init()
748 odbaud = DIV_ROUND_UP(fclk_rate, i2c_scl_rate * (2 + 2 * ppbaud)) - 1; in svc_i3c_master_bus_init()
751 i2cbaud = DIV_ROUND_UP(i2c_period_ns, od_low_period_ns) - 2; in svc_i3c_master_bus_init()
768 writel(reg, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_bus_init()
770 master->mctrl_config = reg; in svc_i3c_master_bus_init()
771 /* Master core's registration */ in svc_i3c_master_bus_init()
779 master->regs + SVC_I3C_MDYNADDR); in svc_i3c_master_bus_init()
781 ret = i3c_master_set_info(&master->base, &info); in svc_i3c_master_bus_init()
786 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_bus_init()
787 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_bus_init()
794 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_bus_cleanup() local
797 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_bus_cleanup()
799 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_bus_cleanup()
803 svc_i3c_master_disable_interrupts(master); in svc_i3c_master_bus_cleanup()
805 /* Disable master */ in svc_i3c_master_bus_cleanup()
806 writel(0, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_bus_cleanup()
808 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_bus_cleanup()
809 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_bus_cleanup()
812 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master) in svc_i3c_master_reserve_slot() argument
816 if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0))) in svc_i3c_master_reserve_slot()
817 return -ENOSPC; in svc_i3c_master_reserve_slot()
819 slot = ffs(master->free_slots) - 1; in svc_i3c_master_reserve_slot()
821 master->free_slots &= ~BIT(slot); in svc_i3c_master_reserve_slot()
826 static void svc_i3c_master_release_slot(struct svc_i3c_master *master, in svc_i3c_master_release_slot() argument
829 master->free_slots |= BIT(slot); in svc_i3c_master_release_slot()
835 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_attach_i3c_dev() local
839 slot = svc_i3c_master_reserve_slot(master); in svc_i3c_master_attach_i3c_dev()
845 svc_i3c_master_release_slot(master, slot); in svc_i3c_master_attach_i3c_dev()
846 return -ENOMEM; in svc_i3c_master_attach_i3c_dev()
849 data->ibi = -1; in svc_i3c_master_attach_i3c_dev()
850 data->index = slot; in svc_i3c_master_attach_i3c_dev()
851 master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr : in svc_i3c_master_attach_i3c_dev()
852 dev->info.static_addr; in svc_i3c_master_attach_i3c_dev()
853 master->descs[slot] = dev; in svc_i3c_master_attach_i3c_dev()
864 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_reattach_i3c_dev() local
867 master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr : in svc_i3c_master_reattach_i3c_dev()
868 dev->info.static_addr; in svc_i3c_master_reattach_i3c_dev()
877 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_detach_i3c_dev() local
879 master->addrs[data->index] = 0; in svc_i3c_master_detach_i3c_dev()
880 svc_i3c_master_release_slot(master, data->index); in svc_i3c_master_detach_i3c_dev()
888 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_attach_i2c_dev() local
892 slot = svc_i3c_master_reserve_slot(master); in svc_i3c_master_attach_i2c_dev()
898 svc_i3c_master_release_slot(master, slot); in svc_i3c_master_attach_i2c_dev()
899 return -ENOMEM; in svc_i3c_master_attach_i2c_dev()
902 data->index = slot; in svc_i3c_master_attach_i2c_dev()
903 master->addrs[slot] = dev->addr; in svc_i3c_master_attach_i2c_dev()
914 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_detach_i2c_dev() local
916 svc_i3c_master_release_slot(master, data->index); in svc_i3c_master_detach_i2c_dev()
921 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst, in svc_i3c_master_readb() argument
928 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, in svc_i3c_master_readb()
935 dst[i] = readl(master->regs + SVC_I3C_MRDATAB); in svc_i3c_master_readb()
941 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master, in svc_i3c_master_do_daa_locked() argument
949 svc_i3c_master_flush_fifo(master); in svc_i3c_master_do_daa_locked()
953 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_do_daa_locked()
973 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_do_daa_locked()
979 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, in svc_i3c_master_do_daa_locked()
1003 ret = i3c_master_get_free_addr(&master->base, last_addr + 1); in svc_i3c_master_do_daa_locked()
1008 writel(dyn_addr, master->regs + SVC_I3C_MWDATAB); in svc_i3c_master_do_daa_locked()
1011 * We only care about the 48-bit provisioned ID yet to in svc_i3c_master_do_daa_locked()
1015 ret = svc_i3c_master_readb(master, data, 6); in svc_i3c_master_do_daa_locked()
1020 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i)); in svc_i3c_master_do_daa_locked()
1023 ret = svc_i3c_master_readb(master, data, 2); in svc_i3c_master_do_daa_locked()
1027 ret = svc_i3c_master_handle_ibi_won(master, reg); in svc_i3c_master_do_daa_locked()
1045 /* No I3C devices attached */ in svc_i3c_master_do_daa_locked()
1064 ret = -EIO; in svc_i3c_master_do_daa_locked()
1068 dev_nb--; in svc_i3c_master_do_daa_locked()
1070 svc_i3c_master_emit_stop(master); in svc_i3c_master_do_daa_locked()
1079 ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS, in svc_i3c_master_do_daa_locked()
1089 dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n", in svc_i3c_master_do_daa_locked()
1095 svc_i3c_master_emit_stop(master); in svc_i3c_master_do_daa_locked()
1096 svc_i3c_master_flush_fifo(master); in svc_i3c_master_do_daa_locked()
1101 static int svc_i3c_update_ibirules(struct svc_i3c_master *master) in svc_i3c_update_ibirules() argument
1110 i3c_bus_for_each_i3cdev(&master->base.bus, dev) { in svc_i3c_update_ibirules()
1111 if (!(dev->info.bcr & I3C_BCR_IBI_REQ_CAP)) in svc_i3c_update_ibirules()
1114 if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) { in svc_i3c_update_ibirules()
1116 dev->info.dyn_addr); in svc_i3c_update_ibirules()
1119 if (dev->info.dyn_addr & BIT(7)) in svc_i3c_update_ibirules()
1125 dev->info.dyn_addr); in svc_i3c_update_ibirules()
1128 if (dev->info.dyn_addr & BIT(7)) in svc_i3c_update_ibirules()
1144 return -ERANGE; in svc_i3c_update_ibirules()
1148 writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES); in svc_i3c_update_ibirules()
1150 writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES); in svc_i3c_update_ibirules()
1157 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_do_daa() local
1163 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_do_daa()
1165 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_do_daa()
1169 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_do_daa()
1171 if (svc_has_daa_corrupt(master)) in svc_i3c_master_do_daa()
1172 writel(master->mctrl_config | SVC_I3C_MCONFIG_SKEW(1), in svc_i3c_master_do_daa()
1173 master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_do_daa()
1175 ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb); in svc_i3c_master_do_daa()
1177 if (svc_has_daa_corrupt(master)) in svc_i3c_master_do_daa()
1178 writel(master->mctrl_config, master->regs + SVC_I3C_MCONFIG); in svc_i3c_master_do_daa()
1180 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_do_daa()
1182 svc_i3c_master_clear_merrwarn(master); in svc_i3c_master_do_daa()
1192 * registered on the bus. The I3C stack might still consider 0xb a free in svc_i3c_master_do_daa()
1194 * causing both devices A and B to use the same address 0xb, violating the I3C in svc_i3c_master_do_daa()
1198 * because subsequent steps will scan the entire I3C bus, independent of in svc_i3c_master_do_daa()
1208 /* Configure IBI auto-rules */ in svc_i3c_master_do_daa()
1209 ret = svc_i3c_update_ibirules(master); in svc_i3c_master_do_daa()
1211 dev_err(master->dev, "Cannot handle such a list of devices"); in svc_i3c_master_do_daa()
1214 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_do_daa()
1215 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_do_daa()
1220 static int svc_i3c_master_read(struct svc_i3c_master *master, in svc_i3c_master_read() argument
1230 mstatus = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_read()
1235 dev_dbg(master->dev, "I3C read timeout\n"); in svc_i3c_master_read()
1236 return -ETIMEDOUT; in svc_i3c_master_read()
1239 mdctrl = readl(master->regs + SVC_I3C_MDATACTRL); in svc_i3c_master_read()
1242 dev_err(master->dev, "I3C receive length too long!\n"); in svc_i3c_master_read()
1243 return -EINVAL; in svc_i3c_master_read()
1246 in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB); in svc_i3c_master_read()
1254 static int svc_i3c_master_write(struct svc_i3c_master *master, in svc_i3c_master_write() argument
1261 ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL, in svc_i3c_master_write()
1272 if (likely(offset < (len - 1))) in svc_i3c_master_write()
1273 writel(out[offset++], master->regs + SVC_I3C_MWDATAB); in svc_i3c_master_write()
1275 writel(out[offset++], master->regs + SVC_I3C_MWDATABE); in svc_i3c_master_write()
1281 static int svc_i3c_master_xfer(struct svc_i3c_master *master, in svc_i3c_master_xfer() argument
1291 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_xfer()
1294 while (retry--) { in svc_i3c_master_xfer()
1301 master->regs + SVC_I3C_MCTRL); in svc_i3c_master_xfer()
1310 if (svc_has_quirk(master, SVC_I3C_QUIRK_FIFO_EMPTY) && !rnw && xfer_len) { in svc_i3c_master_xfer()
1314 writesb(master->regs + SVC_I3C_MWDATAB1, out, len - 1); in svc_i3c_master_xfer()
1316 writel(out[len - 1] | end, master->regs + SVC_I3C_MWDATAB); in svc_i3c_master_xfer()
1317 xfer_len -= len; in svc_i3c_master_xfer()
1321 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_xfer()
1327 * According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a in svc_i3c_master_xfer()
1328 * Frame with I3C Target Address. in svc_i3c_master_xfer()
1330 * The I3C Controller normally should start a Frame, the Address may be arbitrated, in svc_i3c_master_xfer()
1331 * and so the Controller shall monitor to see whether an In-Band Interrupt request, in svc_i3c_master_xfer()
1333 * Active Controller), or a Hot-Join Request has been made. in svc_i3c_master_xfer()
1340 ret = svc_i3c_master_handle_ibi_won(master, reg); in svc_i3c_master_xfer()
1346 if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) { in svc_i3c_master_xfer()
1348 * According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3. in svc_i3c_master_xfer()
1349 * If the Controller chooses to start an I3C Message with an I3C Dynamic in svc_i3c_master_xfer()
1350 * Address, then special provisions shall be made because that same I3C in svc_i3c_master_xfer()
1368 writel(SVC_I3C_MERRWARN_NACK, master->regs + SVC_I3C_MERRWARN); in svc_i3c_master_xfer()
1370 ret = -ENXIO; in svc_i3c_master_xfer()
1380 ret = svc_i3c_master_read(master, in, xfer_len); in svc_i3c_master_xfer()
1382 ret = svc_i3c_master_write(master, out, xfer_len); in svc_i3c_master_xfer()
1389 ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_xfer()
1394 writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_xfer()
1397 svc_i3c_master_emit_stop(master); in svc_i3c_master_xfer()
1400 readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg, in svc_i3c_master_xfer()
1407 svc_i3c_master_emit_stop(master); in svc_i3c_master_xfer()
1408 svc_i3c_master_clear_merrwarn(master); in svc_i3c_master_xfer()
1409 svc_i3c_master_flush_fifo(master); in svc_i3c_master_xfer()
1415 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds) in svc_i3c_master_alloc_xfer() argument
1423 INIT_LIST_HEAD(&xfer->node); in svc_i3c_master_alloc_xfer()
1424 xfer->ncmds = ncmds; in svc_i3c_master_alloc_xfer()
1425 xfer->ret = -ETIMEDOUT; in svc_i3c_master_alloc_xfer()
1435 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master, in svc_i3c_master_dequeue_xfer_locked() argument
1438 if (master->xferqueue.cur == xfer) in svc_i3c_master_dequeue_xfer_locked()
1439 master->xferqueue.cur = NULL; in svc_i3c_master_dequeue_xfer_locked()
1441 list_del_init(&xfer->node); in svc_i3c_master_dequeue_xfer_locked()
1444 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master, in svc_i3c_master_dequeue_xfer() argument
1449 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_dequeue_xfer()
1450 svc_i3c_master_dequeue_xfer_locked(master, xfer); in svc_i3c_master_dequeue_xfer()
1451 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_dequeue_xfer()
1454 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master) in svc_i3c_master_start_xfer_locked() argument
1456 struct svc_i3c_xfer *xfer = master->xferqueue.cur; in svc_i3c_master_start_xfer_locked()
1462 svc_i3c_master_clear_merrwarn(master); in svc_i3c_master_start_xfer_locked()
1463 svc_i3c_master_flush_fifo(master); in svc_i3c_master_start_xfer_locked()
1465 for (i = 0; i < xfer->ncmds; i++) { in svc_i3c_master_start_xfer_locked()
1466 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_start_xfer_locked()
1468 ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type, in svc_i3c_master_start_xfer_locked()
1469 cmd->addr, cmd->in, cmd->out, in svc_i3c_master_start_xfer_locked()
1470 cmd->len, &cmd->actual_len, in svc_i3c_master_start_xfer_locked()
1471 cmd->continued); in svc_i3c_master_start_xfer_locked()
1472 /* cmd->xfer is NULL if I2C or CCC transfer */ in svc_i3c_master_start_xfer_locked()
1473 if (cmd->xfer) in svc_i3c_master_start_xfer_locked()
1474 cmd->xfer->actual_len = cmd->actual_len; in svc_i3c_master_start_xfer_locked()
1480 xfer->ret = ret; in svc_i3c_master_start_xfer_locked()
1481 complete(&xfer->comp); in svc_i3c_master_start_xfer_locked()
1484 svc_i3c_master_dequeue_xfer_locked(master, xfer); in svc_i3c_master_start_xfer_locked()
1486 xfer = list_first_entry_or_null(&master->xferqueue.list, in svc_i3c_master_start_xfer_locked()
1490 list_del_init(&xfer->node); in svc_i3c_master_start_xfer_locked()
1492 master->xferqueue.cur = xfer; in svc_i3c_master_start_xfer_locked()
1493 svc_i3c_master_start_xfer_locked(master); in svc_i3c_master_start_xfer_locked()
1496 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master, in svc_i3c_master_enqueue_xfer() argument
1502 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_enqueue_xfer()
1504 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_enqueue_xfer()
1508 init_completion(&xfer->comp); in svc_i3c_master_enqueue_xfer()
1509 spin_lock_irqsave(&master->xferqueue.lock, flags); in svc_i3c_master_enqueue_xfer()
1510 if (master->xferqueue.cur) { in svc_i3c_master_enqueue_xfer()
1511 list_add_tail(&xfer->node, &master->xferqueue.list); in svc_i3c_master_enqueue_xfer()
1513 master->xferqueue.cur = xfer; in svc_i3c_master_enqueue_xfer()
1514 svc_i3c_master_start_xfer_locked(master); in svc_i3c_master_enqueue_xfer()
1516 spin_unlock_irqrestore(&master->xferqueue.lock, flags); in svc_i3c_master_enqueue_xfer()
1518 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_enqueue_xfer()
1519 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_enqueue_xfer()
1523 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master, in svc_i3c_master_supports_ccc_cmd() argument
1527 return (cmd->ndests == 1); in svc_i3c_master_supports_ccc_cmd()
1530 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master, in svc_i3c_master_send_bdcast_ccc_cmd() argument
1533 unsigned int xfer_len = ccc->dests[0].payload.len + 1; in svc_i3c_master_send_bdcast_ccc_cmd()
1539 xfer = svc_i3c_master_alloc_xfer(master, 1); in svc_i3c_master_send_bdcast_ccc_cmd()
1541 return -ENOMEM; in svc_i3c_master_send_bdcast_ccc_cmd()
1546 return -ENOMEM; in svc_i3c_master_send_bdcast_ccc_cmd()
1549 buf[0] = ccc->id; in svc_i3c_master_send_bdcast_ccc_cmd()
1550 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); in svc_i3c_master_send_bdcast_ccc_cmd()
1552 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_send_bdcast_ccc_cmd()
1554 cmd = &xfer->cmds[0]; in svc_i3c_master_send_bdcast_ccc_cmd()
1555 cmd->addr = ccc->dests[0].addr; in svc_i3c_master_send_bdcast_ccc_cmd()
1556 cmd->rnw = ccc->rnw; in svc_i3c_master_send_bdcast_ccc_cmd()
1557 cmd->in = NULL; in svc_i3c_master_send_bdcast_ccc_cmd()
1558 cmd->out = buf; in svc_i3c_master_send_bdcast_ccc_cmd()
1559 cmd->len = xfer_len; in svc_i3c_master_send_bdcast_ccc_cmd()
1560 cmd->actual_len = 0; in svc_i3c_master_send_bdcast_ccc_cmd()
1561 cmd->continued = false; in svc_i3c_master_send_bdcast_ccc_cmd()
1563 mutex_lock(&master->lock); in svc_i3c_master_send_bdcast_ccc_cmd()
1564 svc_i3c_master_enqueue_xfer(master, xfer); in svc_i3c_master_send_bdcast_ccc_cmd()
1565 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_send_bdcast_ccc_cmd()
1566 svc_i3c_master_dequeue_xfer(master, xfer); in svc_i3c_master_send_bdcast_ccc_cmd()
1567 mutex_unlock(&master->lock); in svc_i3c_master_send_bdcast_ccc_cmd()
1569 ret = xfer->ret; in svc_i3c_master_send_bdcast_ccc_cmd()
1576 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master, in svc_i3c_master_send_direct_ccc_cmd() argument
1579 unsigned int xfer_len = ccc->dests[0].payload.len; in svc_i3c_master_send_direct_ccc_cmd()
1580 unsigned int actual_len = ccc->rnw ? xfer_len : 0; in svc_i3c_master_send_direct_ccc_cmd()
1585 xfer = svc_i3c_master_alloc_xfer(master, 2); in svc_i3c_master_send_direct_ccc_cmd()
1587 return -ENOMEM; in svc_i3c_master_send_direct_ccc_cmd()
1589 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_send_direct_ccc_cmd()
1592 cmd = &xfer->cmds[0]; in svc_i3c_master_send_direct_ccc_cmd()
1593 cmd->addr = I3C_BROADCAST_ADDR; in svc_i3c_master_send_direct_ccc_cmd()
1594 cmd->rnw = 0; in svc_i3c_master_send_direct_ccc_cmd()
1595 cmd->in = NULL; in svc_i3c_master_send_direct_ccc_cmd()
1596 cmd->out = &ccc->id; in svc_i3c_master_send_direct_ccc_cmd()
1597 cmd->len = 1; in svc_i3c_master_send_direct_ccc_cmd()
1598 cmd->actual_len = 0; in svc_i3c_master_send_direct_ccc_cmd()
1599 cmd->continued = true; in svc_i3c_master_send_direct_ccc_cmd()
1602 cmd = &xfer->cmds[1]; in svc_i3c_master_send_direct_ccc_cmd()
1603 cmd->addr = ccc->dests[0].addr; in svc_i3c_master_send_direct_ccc_cmd()
1604 cmd->rnw = ccc->rnw; in svc_i3c_master_send_direct_ccc_cmd()
1605 cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL; in svc_i3c_master_send_direct_ccc_cmd()
1606 cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data; in svc_i3c_master_send_direct_ccc_cmd()
1607 cmd->len = xfer_len; in svc_i3c_master_send_direct_ccc_cmd()
1608 cmd->actual_len = actual_len; in svc_i3c_master_send_direct_ccc_cmd()
1609 cmd->continued = false; in svc_i3c_master_send_direct_ccc_cmd()
1611 mutex_lock(&master->lock); in svc_i3c_master_send_direct_ccc_cmd()
1612 svc_i3c_master_enqueue_xfer(master, xfer); in svc_i3c_master_send_direct_ccc_cmd()
1613 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_send_direct_ccc_cmd()
1614 svc_i3c_master_dequeue_xfer(master, xfer); in svc_i3c_master_send_direct_ccc_cmd()
1615 mutex_unlock(&master->lock); in svc_i3c_master_send_direct_ccc_cmd()
1617 if (cmd->actual_len != xfer_len) in svc_i3c_master_send_direct_ccc_cmd()
1618 ccc->dests[0].payload.len = cmd->actual_len; in svc_i3c_master_send_direct_ccc_cmd()
1620 ret = xfer->ret; in svc_i3c_master_send_direct_ccc_cmd()
1629 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_send_ccc_cmd() local
1630 bool broadcast = cmd->id < 0x80; in svc_i3c_master_send_ccc_cmd()
1634 ret = svc_i3c_master_send_bdcast_ccc_cmd(master, cmd); in svc_i3c_master_send_ccc_cmd()
1636 ret = svc_i3c_master_send_direct_ccc_cmd(master, cmd); in svc_i3c_master_send_ccc_cmd()
1639 cmd->err = I3C_ERROR_M2; in svc_i3c_master_send_ccc_cmd()
1649 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_priv_xfers() local
1654 xfer = svc_i3c_master_alloc_xfer(master, nxfers); in svc_i3c_master_priv_xfers()
1656 return -ENOMEM; in svc_i3c_master_priv_xfers()
1658 xfer->type = SVC_I3C_MCTRL_TYPE_I3C; in svc_i3c_master_priv_xfers()
1661 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_priv_xfers()
1663 cmd->xfer = &xfers[i]; in svc_i3c_master_priv_xfers()
1664 cmd->addr = master->addrs[data->index]; in svc_i3c_master_priv_xfers()
1665 cmd->rnw = xfers[i].rnw; in svc_i3c_master_priv_xfers()
1666 cmd->in = xfers[i].rnw ? xfers[i].data.in : NULL; in svc_i3c_master_priv_xfers()
1667 cmd->out = xfers[i].rnw ? NULL : xfers[i].data.out; in svc_i3c_master_priv_xfers()
1668 cmd->len = xfers[i].len; in svc_i3c_master_priv_xfers()
1669 cmd->actual_len = xfers[i].rnw ? xfers[i].len : 0; in svc_i3c_master_priv_xfers()
1670 cmd->continued = (i + 1) < nxfers; in svc_i3c_master_priv_xfers()
1673 mutex_lock(&master->lock); in svc_i3c_master_priv_xfers()
1674 svc_i3c_master_enqueue_xfer(master, xfer); in svc_i3c_master_priv_xfers()
1675 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_priv_xfers()
1676 svc_i3c_master_dequeue_xfer(master, xfer); in svc_i3c_master_priv_xfers()
1677 mutex_unlock(&master->lock); in svc_i3c_master_priv_xfers()
1679 ret = xfer->ret; in svc_i3c_master_priv_xfers()
1690 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_i2c_xfers() local
1695 xfer = svc_i3c_master_alloc_xfer(master, nxfers); in svc_i3c_master_i2c_xfers()
1697 return -ENOMEM; in svc_i3c_master_i2c_xfers()
1699 xfer->type = SVC_I3C_MCTRL_TYPE_I2C; in svc_i3c_master_i2c_xfers()
1702 struct svc_i3c_cmd *cmd = &xfer->cmds[i]; in svc_i3c_master_i2c_xfers()
1704 cmd->addr = master->addrs[data->index]; in svc_i3c_master_i2c_xfers()
1705 cmd->rnw = xfers[i].flags & I2C_M_RD; in svc_i3c_master_i2c_xfers()
1706 cmd->in = cmd->rnw ? xfers[i].buf : NULL; in svc_i3c_master_i2c_xfers()
1707 cmd->out = cmd->rnw ? NULL : xfers[i].buf; in svc_i3c_master_i2c_xfers()
1708 cmd->len = xfers[i].len; in svc_i3c_master_i2c_xfers()
1709 cmd->actual_len = cmd->rnw ? xfers[i].len : 0; in svc_i3c_master_i2c_xfers()
1710 cmd->continued = (i + 1 < nxfers); in svc_i3c_master_i2c_xfers()
1713 mutex_lock(&master->lock); in svc_i3c_master_i2c_xfers()
1714 svc_i3c_master_enqueue_xfer(master, xfer); in svc_i3c_master_i2c_xfers()
1715 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) in svc_i3c_master_i2c_xfers()
1716 svc_i3c_master_dequeue_xfer(master, xfer); in svc_i3c_master_i2c_xfers()
1717 mutex_unlock(&master->lock); in svc_i3c_master_i2c_xfers()
1719 ret = xfer->ret; in svc_i3c_master_i2c_xfers()
1729 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_request_ibi() local
1734 if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) { in svc_i3c_master_request_ibi()
1735 dev_err(master->dev, "IBI max payload %d should be < %d\n", in svc_i3c_master_request_ibi()
1736 dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE); in svc_i3c_master_request_ibi()
1737 return -ERANGE; in svc_i3c_master_request_ibi()
1740 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); in svc_i3c_master_request_ibi()
1741 if (IS_ERR(data->ibi_pool)) in svc_i3c_master_request_ibi()
1742 return PTR_ERR(data->ibi_pool); in svc_i3c_master_request_ibi()
1744 spin_lock_irqsave(&master->ibi.lock, flags); in svc_i3c_master_request_ibi()
1745 for (i = 0; i < master->ibi.num_slots; i++) { in svc_i3c_master_request_ibi()
1746 if (!master->ibi.slots[i]) { in svc_i3c_master_request_ibi()
1747 data->ibi = i; in svc_i3c_master_request_ibi()
1748 master->ibi.slots[i] = dev; in svc_i3c_master_request_ibi()
1752 spin_unlock_irqrestore(&master->ibi.lock, flags); in svc_i3c_master_request_ibi()
1754 if (i < master->ibi.num_slots) in svc_i3c_master_request_ibi()
1757 i3c_generic_ibi_free_pool(data->ibi_pool); in svc_i3c_master_request_ibi()
1758 data->ibi_pool = NULL; in svc_i3c_master_request_ibi()
1760 return -ENOSPC; in svc_i3c_master_request_ibi()
1766 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_free_ibi() local
1770 spin_lock_irqsave(&master->ibi.lock, flags); in svc_i3c_master_free_ibi()
1771 master->ibi.slots[data->ibi] = NULL; in svc_i3c_master_free_ibi()
1772 data->ibi = -1; in svc_i3c_master_free_ibi()
1773 spin_unlock_irqrestore(&master->ibi.lock, flags); in svc_i3c_master_free_ibi()
1775 i3c_generic_ibi_free_pool(data->ibi_pool); in svc_i3c_master_free_ibi()
1781 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_enable_ibi() local
1784 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_enable_ibi()
1786 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_enable_ibi()
1790 master->enabled_events++; in svc_i3c_master_enable_ibi()
1791 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); in svc_i3c_master_enable_ibi()
1793 return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); in svc_i3c_master_enable_ibi()
1799 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_disable_ibi() local
1802 master->enabled_events--; in svc_i3c_master_disable_ibi()
1803 if (!master->enabled_events) in svc_i3c_master_disable_ibi()
1804 svc_i3c_master_disable_interrupts(master); in svc_i3c_master_disable_ibi()
1806 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); in svc_i3c_master_disable_ibi()
1808 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_disable_ibi()
1809 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_disable_ibi()
1816 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_enable_hotjoin() local
1819 ret = pm_runtime_resume_and_get(master->dev); in svc_i3c_master_enable_hotjoin()
1821 dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__); in svc_i3c_master_enable_hotjoin()
1825 master->enabled_events |= SVC_I3C_EVENT_HOTJOIN; in svc_i3c_master_enable_hotjoin()
1827 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); in svc_i3c_master_enable_hotjoin()
1834 struct svc_i3c_master *master = to_svc_i3c_master(m); in svc_i3c_master_disable_hotjoin() local
1836 master->enabled_events &= ~SVC_I3C_EVENT_HOTJOIN; in svc_i3c_master_disable_hotjoin()
1838 if (!master->enabled_events) in svc_i3c_master_disable_hotjoin()
1839 svc_i3c_master_disable_interrupts(master); in svc_i3c_master_disable_hotjoin()
1841 pm_runtime_mark_last_busy(master->dev); in svc_i3c_master_disable_hotjoin()
1842 pm_runtime_put_autosuspend(master->dev); in svc_i3c_master_disable_hotjoin()
1852 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); in svc_i3c_master_recycle_ibi_slot()
1878 static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master) in svc_i3c_master_prepare_clks() argument
1882 ret = clk_prepare_enable(master->pclk); in svc_i3c_master_prepare_clks()
1886 ret = clk_prepare_enable(master->fclk); in svc_i3c_master_prepare_clks()
1888 clk_disable_unprepare(master->pclk); in svc_i3c_master_prepare_clks()
1892 ret = clk_prepare_enable(master->sclk); in svc_i3c_master_prepare_clks()
1894 clk_disable_unprepare(master->pclk); in svc_i3c_master_prepare_clks()
1895 clk_disable_unprepare(master->fclk); in svc_i3c_master_prepare_clks()
1902 static void svc_i3c_master_unprepare_clks(struct svc_i3c_master *master) in svc_i3c_master_unprepare_clks() argument
1904 clk_disable_unprepare(master->pclk); in svc_i3c_master_unprepare_clks()
1905 clk_disable_unprepare(master->fclk); in svc_i3c_master_unprepare_clks()
1906 clk_disable_unprepare(master->sclk); in svc_i3c_master_unprepare_clks()
1911 struct device *dev = &pdev->dev; in svc_i3c_master_probe()
1912 struct svc_i3c_master *master; in svc_i3c_master_probe() local
1915 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); in svc_i3c_master_probe()
1916 if (!master) in svc_i3c_master_probe()
1917 return -ENOMEM; in svc_i3c_master_probe()
1919 master->drvdata = of_device_get_match_data(dev); in svc_i3c_master_probe()
1920 if (!master->drvdata) in svc_i3c_master_probe()
1921 return -EINVAL; in svc_i3c_master_probe()
1923 master->regs = devm_platform_ioremap_resource(pdev, 0); in svc_i3c_master_probe()
1924 if (IS_ERR(master->regs)) in svc_i3c_master_probe()
1925 return PTR_ERR(master->regs); in svc_i3c_master_probe()
1927 master->pclk = devm_clk_get(dev, "pclk"); in svc_i3c_master_probe()
1928 if (IS_ERR(master->pclk)) in svc_i3c_master_probe()
1929 return PTR_ERR(master->pclk); in svc_i3c_master_probe()
1931 master->fclk = devm_clk_get(dev, "fast_clk"); in svc_i3c_master_probe()
1932 if (IS_ERR(master->fclk)) in svc_i3c_master_probe()
1933 return PTR_ERR(master->fclk); in svc_i3c_master_probe()
1935 master->sclk = devm_clk_get(dev, "slow_clk"); in svc_i3c_master_probe()
1936 if (IS_ERR(master->sclk)) in svc_i3c_master_probe()
1937 return PTR_ERR(master->sclk); in svc_i3c_master_probe()
1939 master->irq = platform_get_irq(pdev, 0); in svc_i3c_master_probe()
1940 if (master->irq < 0) in svc_i3c_master_probe()
1941 return master->irq; in svc_i3c_master_probe()
1943 master->dev = dev; in svc_i3c_master_probe()
1945 ret = svc_i3c_master_prepare_clks(master); in svc_i3c_master_probe()
1949 INIT_WORK(&master->hj_work, svc_i3c_master_hj_work); in svc_i3c_master_probe()
1950 INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work); in svc_i3c_master_probe()
1951 mutex_init(&master->lock); in svc_i3c_master_probe()
1953 ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler, in svc_i3c_master_probe()
1954 IRQF_NO_SUSPEND, "svc-i3c-irq", master); in svc_i3c_master_probe()
1958 master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0); in svc_i3c_master_probe()
1960 spin_lock_init(&master->xferqueue.lock); in svc_i3c_master_probe()
1961 INIT_LIST_HEAD(&master->xferqueue.list); in svc_i3c_master_probe()
1963 spin_lock_init(&master->ibi.lock); in svc_i3c_master_probe()
1964 master->ibi.num_slots = SVC_I3C_MAX_DEVS; in svc_i3c_master_probe()
1965 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, in svc_i3c_master_probe()
1966 sizeof(*master->ibi.slots), in svc_i3c_master_probe()
1968 if (!master->ibi.slots) { in svc_i3c_master_probe()
1969 ret = -ENOMEM; in svc_i3c_master_probe()
1973 platform_set_drvdata(pdev, master); in svc_i3c_master_probe()
1975 pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS); in svc_i3c_master_probe()
1976 pm_runtime_use_autosuspend(&pdev->dev); in svc_i3c_master_probe()
1977 pm_runtime_get_noresume(&pdev->dev); in svc_i3c_master_probe()
1978 pm_runtime_set_active(&pdev->dev); in svc_i3c_master_probe()
1979 pm_runtime_enable(&pdev->dev); in svc_i3c_master_probe()
1981 svc_i3c_master_reset(master); in svc_i3c_master_probe()
1983 /* Register the master */ in svc_i3c_master_probe()
1984 ret = i3c_master_register(&master->base, &pdev->dev, in svc_i3c_master_probe()
1989 pm_runtime_mark_last_busy(&pdev->dev); in svc_i3c_master_probe()
1990 pm_runtime_put_autosuspend(&pdev->dev); in svc_i3c_master_probe()
1995 pm_runtime_dont_use_autosuspend(&pdev->dev); in svc_i3c_master_probe()
1996 pm_runtime_put_noidle(&pdev->dev); in svc_i3c_master_probe()
1997 pm_runtime_disable(&pdev->dev); in svc_i3c_master_probe()
1998 pm_runtime_set_suspended(&pdev->dev); in svc_i3c_master_probe()
2001 svc_i3c_master_unprepare_clks(master); in svc_i3c_master_probe()
2008 struct svc_i3c_master *master = platform_get_drvdata(pdev); in svc_i3c_master_remove() local
2010 cancel_work_sync(&master->hj_work); in svc_i3c_master_remove()
2011 i3c_master_unregister(&master->base); in svc_i3c_master_remove()
2013 pm_runtime_dont_use_autosuspend(&pdev->dev); in svc_i3c_master_remove()
2014 pm_runtime_disable(&pdev->dev); in svc_i3c_master_remove()
2017 static void svc_i3c_save_regs(struct svc_i3c_master *master) in svc_i3c_save_regs() argument
2019 master->saved_regs.mconfig = readl(master->regs + SVC_I3C_MCONFIG); in svc_i3c_save_regs()
2020 master->saved_regs.mdynaddr = readl(master->regs + SVC_I3C_MDYNADDR); in svc_i3c_save_regs()
2023 static void svc_i3c_restore_regs(struct svc_i3c_master *master) in svc_i3c_restore_regs() argument
2025 if (readl(master->regs + SVC_I3C_MDYNADDR) != in svc_i3c_restore_regs()
2026 master->saved_regs.mdynaddr) { in svc_i3c_restore_regs()
2027 writel(master->saved_regs.mconfig, in svc_i3c_restore_regs()
2028 master->regs + SVC_I3C_MCONFIG); in svc_i3c_restore_regs()
2029 writel(master->saved_regs.mdynaddr, in svc_i3c_restore_regs()
2030 master->regs + SVC_I3C_MDYNADDR); in svc_i3c_restore_regs()
2036 struct svc_i3c_master *master = dev_get_drvdata(dev); in svc_i3c_runtime_suspend() local
2038 svc_i3c_save_regs(master); in svc_i3c_runtime_suspend()
2039 svc_i3c_master_unprepare_clks(master); in svc_i3c_runtime_suspend()
2047 struct svc_i3c_master *master = dev_get_drvdata(dev); in svc_i3c_runtime_resume() local
2050 svc_i3c_master_prepare_clks(master); in svc_i3c_runtime_resume()
2052 svc_i3c_restore_regs(master); in svc_i3c_runtime_resume()
2073 { .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata },
2074 { .compatible = "silvaco,i3c-master-v1", .data = &svc_default_drvdata },
2083 .name = "silvaco-i3c-master",
2092 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");