3  * Silvaco dual-role I3C master driver
14 #include <linux/i3c/master.h>
141  * I3C HW stalls the write transfer if the transmit FIFO becomes empty,
142  * when new data is written to FIFO, I3C HW resumes the transfer but
150  * I3C HW may generate an invalid SlvStart event when emitting a STOP.
195  * struct svc_i3c_master - Silvaco I3C Master structure
196  * @base: I3C master controller
500 	 * According to I3C spec ver 1.1, 09-Jun-2021, section 5.1.2.5:  in svc_i3c_master_ibi_work()
502 	 * The I3C Controller shall hold SCL low while the Bus is in ACK/NACK Phase of I3C/I2C  in svc_i3c_master_ibi_work()
504 	 * schedule during the whole I3C transaction, otherwise, the I3C bus timeout may happen if  in svc_i3c_master_ibi_work()
652 		 * Set 50% duty-cycle I2C speed to I3C OPEN-DRAIN mode, so the first  in svc_i3c_master_set_speed()
653 		 * broadcast address is visible to all I2C/I3C devices on the I3C bus.  in svc_i3c_master_set_speed()
654 		 * I3C device working as a I2C device will turn off its 50ns Spike  in svc_i3c_master_set_speed()
655 		 * Filter to change to I3C mode.  in svc_i3c_master_set_speed()
691 			"<%s> cannot resume i3c bus master, err: %d\n",  in svc_i3c_master_bus_init()
706 	i3c_scl_rate = bus->scl_rate.i3c;  in svc_i3c_master_bus_init()
709 	 * Using I3C Push-Pull mode, target is 12.5MHz/80ns period.  in svc_i3c_master_bus_init()
716 	 * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a  in svc_i3c_master_bus_init()
740 		/* I3C PP + I3C OP + I2C OP both use i2c clk rate */  in svc_i3c_master_bus_init()
1045 				/* No I3C devices attached */  in svc_i3c_master_do_daa_locked()
1192 	 * registered on the bus. The I3C stack might still consider 0xb a free  in svc_i3c_master_do_daa()
1194 	 * causing both devices A and B to use the same address 0xb, violating the I3C  in svc_i3c_master_do_daa()
1198 	 * because subsequent steps will scan the entire I3C bus, independent of  in svc_i3c_master_do_daa()
1235 			dev_dbg(master->dev, "I3C read timeout\n");  in svc_i3c_master_read()
1242 			dev_err(master->dev, "I3C receive length too long!\n");  in svc_i3c_master_read()
1327 		 * According to I3C spec ver 1.1.1, 5.1.2.2.3 Consequence of Controller Starting a  in svc_i3c_master_xfer()
1328 		 * Frame with I3C Target Address.  in svc_i3c_master_xfer()
1330 		 * The I3C Controller normally should start a Frame, the Address may be arbitrated,  in svc_i3c_master_xfer()
1348 			 * According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3.  in svc_i3c_master_xfer()
1349 			 * If the Controller chooses to start an I3C Message with an I3C Dynamic  in svc_i3c_master_xfer()
1350 			 * Address, then special provisions shall be made because that same I3C  in svc_i3c_master_xfer()
1954 			       IRQF_NO_SUSPEND, "svc-i3c-irq", master);  in svc_i3c_master_probe()
2073 	{ .compatible = "nuvoton,npcm845-i3c", .data = &npcm845_drvdata },
2074 	{ .compatible = "silvaco,i3c-master-v1", .data = &svc_default_drvdata },
2083 		.name = "silvaco-i3c-master",
2092 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");