140 /* I2C SCL time value when Master */
150 #define OMAP_I2C_SYSTEST_SCL_I_FUNC	(1 << 8)	/* SCL line input value */
151 #define OMAP_I2C_SYSTEST_SCL_O_FUNC	(1 << 7)	/* SCL line output value */
154 /* SDA/SCL IO mode */
155 #define OMAP_I2C_SYSTEST_SCL_I		(1 << 3)	/* SCL line sense in */
156 #define OMAP_I2C_SYSTEST_SCL_O		(1 << 2)	/* SCL line drive out */
288 	/* SCL low and high time values */  in __omap_i2c_init()
431 			unsigned long scl;  in omap_i2c_init()  local
434 			scl = internal_clk / 400;  in omap_i2c_init()
435 			fsscll = scl - (scl / 3) - 7;  in omap_i2c_init()
436 			fssclh = (scl / 3) - 5;  in omap_i2c_init()
439 			scl = fclk_rate / omap->speed;  in omap_i2c_init()
440 			hsscll = scl - (scl / 3) - 7;  in omap_i2c_init()
441 			hssclh = (scl / 3) - 5;  in omap_i2c_init()
443 			unsigned long scl;  in omap_i2c_init()  local
446 			scl = internal_clk / omap->speed;  in omap_i2c_init()
447 			fsscll = scl - (scl / 3) - 7;  in omap_i2c_init()
448 			fssclh = (scl / 3) - 5;  in omap_i2c_init()
496 		return -EBUSY; /* recovery would not fix SCL */  in omap_i2c_recover_bus()
524  *     SDA   SCL   BB   NOTES
529  * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
531  * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
539  * 2. Any transfer started when BB=0 and SCL=0 results in IP
580 			 * SDA and SCL lines was high for 10 ms without bus  in omap_i2c_wait_for_bb_valid()
592 			 * SDA or SCL were low for the entire timeout without  in omap_i2c_wait_for_bb_valid()
1310 	/* select SDA/SCL IO mode */  in omap_i2c_prepare_recovery()
1312 	/* set SCL to high-impedance state (reset value is 0) */  in omap_i2c_prepare_recovery()