Lines Matching full:ipu
26 #include <video/imx-ipu-v3.h>
27 #include "ipu-prv.h"
29 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) in ipu_cm_read() argument
31 return readl(ipu->cm_reg + offset); in ipu_cm_read()
34 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) in ipu_cm_write() argument
36 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
39 int ipu_get_num(struct ipu_soc *ipu) in ipu_get_num() argument
41 return ipu->id; in ipu_get_num()
45 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync) in ipu_srm_dp_update() argument
49 val = ipu_cm_read(ipu, IPU_SRM_PRI2); in ipu_srm_dp_update()
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2); in ipu_srm_dp_update()
168 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) in ipu_idmac_get() argument
172 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
177 mutex_lock(&ipu->channel_lock); in ipu_idmac_get()
179 list_for_each_entry(channel, &ipu->channels, list) { in ipu_idmac_get()
193 channel->ipu = ipu; in ipu_idmac_get()
194 list_add(&channel->list, &ipu->channels); in ipu_idmac_get()
197 mutex_unlock(&ipu->channel_lock); in ipu_idmac_get()
205 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_put() local
207 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); in ipu_idmac_put()
209 mutex_lock(&ipu->channel_lock); in ipu_idmac_put()
214 mutex_unlock(&ipu->channel_lock); in ipu_idmac_put()
233 struct ipu_soc *ipu = channel->ipu; in __ipu_idmac_reset_current_buffer() local
236 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); in __ipu_idmac_reset_current_buffer()
242 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_set_double_buffer() local
246 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
248 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
253 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
257 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
287 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_lock_enable() local
315 if (bursts && ipu->ipu_type != IPUV3H) in ipu_idmac_lock_enable()
325 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_lock_enable()
327 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
330 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
332 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_lock_enable()
338 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) in ipu_module_enable() argument
343 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_enable()
345 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_enable()
352 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_enable()
354 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_enable()
356 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_enable()
358 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_enable()
364 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) in ipu_module_disable() argument
369 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_disable()
371 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_disable()
373 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_disable()
375 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_disable()
382 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_disable()
384 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_disable()
392 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_get_current_buffer() local
395 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; in ipu_idmac_get_current_buffer()
401 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_buffer_is_ready() local
405 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
408 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
411 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
414 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
417 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
425 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_select_buffer() local
429 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_select_buffer()
433 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_select_buffer()
435 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_select_buffer()
437 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_select_buffer()
443 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_clear_buffer() local
447 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_clear_buffer()
449 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ in ipu_idmac_clear_buffer()
452 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_clear_buffer()
455 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_clear_buffer()
458 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); in ipu_idmac_clear_buffer()
463 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_clear_buffer()
465 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_clear_buffer()
471 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_channel() local
475 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_channel()
477 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
479 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
481 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_channel()
489 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_wait_busy() local
493 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & in ipu_idmac_wait_busy()
506 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_disable_channel() local
510 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_disable_channel()
513 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
515 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
520 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ in ipu_idmac_disable_channel()
522 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & in ipu_idmac_disable_channel()
524 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
528 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & in ipu_idmac_disable_channel()
530 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
534 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_disable_channel()
537 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
539 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
541 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_disable_channel()
555 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_watermark() local
559 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_watermark()
561 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
566 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
568 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_watermark()
572 static int ipu_memory_reset(struct ipu_soc *ipu) in ipu_memory_reset() argument
576 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); in ipu_memory_reset()
579 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { in ipu_memory_reset()
592 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) in ipu_set_csi_src_mux() argument
600 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_csi_src_mux()
602 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_csi_src_mux()
607 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_csi_src_mux()
609 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_csi_src_mux()
616 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) in ipu_set_ic_src_mux() argument
621 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_ic_src_mux()
623 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_ic_src_mux()
634 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_ic_src_mux()
636 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_ic_src_mux()
694 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch) in ipu_fsu_link() argument
704 spin_lock_irqsave(&ipu->lock, flags); in ipu_fsu_link()
707 src_reg = ipu_cm_read(ipu, link->src.reg); in ipu_fsu_link()
710 ipu_cm_write(ipu, src_reg, link->src.reg); in ipu_fsu_link()
714 sink_reg = ipu_cm_read(ipu, link->sink.reg); in ipu_fsu_link()
717 ipu_cm_write(ipu, sink_reg, link->sink.reg); in ipu_fsu_link()
720 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_fsu_link()
728 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch) in ipu_fsu_unlink() argument
738 spin_lock_irqsave(&ipu->lock, flags); in ipu_fsu_unlink()
741 src_reg = ipu_cm_read(ipu, link->src.reg); in ipu_fsu_unlink()
743 ipu_cm_write(ipu, src_reg, link->src.reg); in ipu_fsu_unlink()
747 sink_reg = ipu_cm_read(ipu, link->sink.reg); in ipu_fsu_unlink()
749 ipu_cm_write(ipu, sink_reg, link->sink.reg); in ipu_fsu_unlink()
752 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_fsu_unlink()
760 return ipu_fsu_link(src->ipu, src->num, sink->num); in ipu_idmac_link()
767 return ipu_fsu_unlink(src->ipu, src->num, sink->num); in ipu_idmac_unlink()
836 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
837 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
838 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
839 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, },
844 static int ipu_submodules_init(struct ipu_soc *ipu, in ipu_submodules_init() argument
851 const struct ipu_devtype *devtype = ipu->devtype; in ipu_submodules_init()
853 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); in ipu_submodules_init()
859 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, in ipu_submodules_init()
866 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, in ipu_submodules_init()
873 ret = ipu_ic_init(ipu, dev, in ipu_submodules_init()
881 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs, in ipu_submodules_init()
889 ret = ipu_image_convert_init(ipu, dev); in ipu_submodules_init()
895 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, in ipu_submodules_init()
902 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, in ipu_submodules_init()
909 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + in ipu_submodules_init()
916 ret = ipu_dmfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
923 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); in ipu_submodules_init()
929 ret = ipu_smfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
939 ipu_dp_exit(ipu); in ipu_submodules_init()
941 ipu_dmfc_exit(ipu); in ipu_submodules_init()
943 ipu_dc_exit(ipu); in ipu_submodules_init()
945 ipu_di_exit(ipu, 1); in ipu_submodules_init()
947 ipu_di_exit(ipu, 0); in ipu_submodules_init()
949 ipu_image_convert_exit(ipu); in ipu_submodules_init()
951 ipu_vdi_exit(ipu); in ipu_submodules_init()
953 ipu_ic_exit(ipu); in ipu_submodules_init()
955 ipu_csi_exit(ipu, 1); in ipu_submodules_init()
957 ipu_csi_exit(ipu, 0); in ipu_submodules_init()
959 ipu_cpmem_exit(ipu); in ipu_submodules_init()
965 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) in ipu_irq_handle() argument
972 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); in ipu_irq_handle()
973 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); in ipu_irq_handle()
976 generic_handle_domain_irq(ipu->domain, in ipu_irq_handle()
983 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_irq_handler() local
989 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_irq_handler()
996 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_err_irq_handler() local
1002 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_err_irq_handler()
1007 int ipu_map_irq(struct ipu_soc *ipu, int irq) in ipu_map_irq() argument
1011 virq = irq_linear_revmap(ipu->domain, irq); in ipu_map_irq()
1013 virq = irq_create_mapping(ipu->domain, irq); in ipu_map_irq()
1019 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, in ipu_idmac_channel_irq() argument
1022 return ipu_map_irq(ipu, irq_type + channel->num); in ipu_idmac_channel_irq()
1026 static void ipu_submodules_exit(struct ipu_soc *ipu) in ipu_submodules_exit() argument
1028 ipu_smfc_exit(ipu); in ipu_submodules_exit()
1029 ipu_dp_exit(ipu); in ipu_submodules_exit()
1030 ipu_dmfc_exit(ipu); in ipu_submodules_exit()
1031 ipu_dc_exit(ipu); in ipu_submodules_exit()
1032 ipu_di_exit(ipu, 1); in ipu_submodules_exit()
1033 ipu_di_exit(ipu, 0); in ipu_submodules_exit()
1034 ipu_image_convert_exit(ipu); in ipu_submodules_exit()
1035 ipu_vdi_exit(ipu); in ipu_submodules_exit()
1036 ipu_ic_exit(ipu); in ipu_submodules_exit()
1037 ipu_csi_exit(ipu, 1); in ipu_submodules_exit()
1038 ipu_csi_exit(ipu, 0); in ipu_submodules_exit()
1039 ipu_cpmem_exit(ipu); in ipu_submodules_exit()
1101 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) in ipu_add_client_devices() argument
1103 struct device *dev = ipu->dev; in ipu_add_client_devices()
1156 static int ipu_irq_init(struct ipu_soc *ipu) in ipu_irq_init() argument
1172 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, in ipu_irq_init()
1173 &irq_generic_chip_ops, ipu); in ipu_irq_init()
1174 if (!ipu->domain) { in ipu_irq_init()
1175 dev_err(ipu->dev, "failed to add irq domain\n"); in ipu_irq_init()
1179 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", in ipu_irq_init()
1182 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); in ipu_irq_init()
1183 irq_domain_remove(ipu->domain); in ipu_irq_init()
1189 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); in ipu_irq_init()
1190 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32)); in ipu_irq_init()
1194 gc = irq_get_domain_generic_chip(ipu->domain, i); in ipu_irq_init()
1195 gc->reg_base = ipu->cm_reg; in ipu_irq_init()
1205 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); in ipu_irq_init()
1206 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, in ipu_irq_init()
1207 ipu); in ipu_irq_init()
1212 static void ipu_irq_exit(struct ipu_soc *ipu) in ipu_irq_exit() argument
1216 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); in ipu_irq_exit()
1217 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); in ipu_irq_exit()
1222 irq = irq_linear_revmap(ipu->domain, i); in ipu_irq_exit()
1227 irq_domain_remove(ipu->domain); in ipu_irq_exit()
1230 void ipu_dump(struct ipu_soc *ipu) in ipu_dump() argument
1234 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", in ipu_dump()
1235 ipu_cm_read(ipu, IPU_CONF)); in ipu_dump()
1236 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", in ipu_dump()
1237 ipu_idmac_read(ipu, IDMAC_CONF)); in ipu_dump()
1238 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", in ipu_dump()
1239 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); in ipu_dump()
1240 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", in ipu_dump()
1241 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); in ipu_dump()
1242 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", in ipu_dump()
1243 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); in ipu_dump()
1244 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", in ipu_dump()
1245 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); in ipu_dump()
1246 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", in ipu_dump()
1247 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); in ipu_dump()
1248 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", in ipu_dump()
1249 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); in ipu_dump()
1250 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", in ipu_dump()
1251 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); in ipu_dump()
1252 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", in ipu_dump()
1253 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); in ipu_dump()
1254 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", in ipu_dump()
1255 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); in ipu_dump()
1256 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", in ipu_dump()
1257 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); in ipu_dump()
1258 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", in ipu_dump()
1259 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); in ipu_dump()
1260 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", in ipu_dump()
1261 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); in ipu_dump()
1263 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, in ipu_dump()
1264 ipu_cm_read(ipu, IPU_INT_CTRL(i))); in ipu_dump()
1271 struct ipu_soc *ipu; in ipu_probe() local
1293 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); in ipu_probe()
1294 if (!ipu) in ipu_probe()
1297 ipu->id = of_alias_get_id(np, "ipu"); in ipu_probe()
1298 if (ipu->id < 0) in ipu_probe()
1299 ipu->id = 0; in ipu_probe()
1301 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") && in ipu_probe()
1303 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev, in ipu_probe()
1304 "fsl,prg", ipu->id); in ipu_probe()
1305 if (!ipu->prg_priv) in ipu_probe()
1309 ipu->devtype = devtype; in ipu_probe()
1310 ipu->ipu_type = devtype->type; in ipu_probe()
1312 spin_lock_init(&ipu->lock); in ipu_probe()
1313 mutex_init(&ipu->channel_lock); in ipu_probe()
1314 INIT_LIST_HEAD(&ipu->channels); in ipu_probe()
1345 ipu->cm_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1347 ipu->idmac_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1351 if (!ipu->cm_reg || !ipu->idmac_reg) in ipu_probe()
1354 ipu->clk = devm_clk_get(&pdev->dev, "bus"); in ipu_probe()
1355 if (IS_ERR(ipu->clk)) { in ipu_probe()
1356 ret = PTR_ERR(ipu->clk); in ipu_probe()
1361 platform_set_drvdata(pdev, ipu); in ipu_probe()
1363 ret = clk_prepare_enable(ipu->clk); in ipu_probe()
1369 ipu->dev = &pdev->dev; in ipu_probe()
1370 ipu->irq_sync = irq_sync; in ipu_probe()
1371 ipu->irq_err = irq_err; in ipu_probe()
1378 ret = ipu_memory_reset(ipu); in ipu_probe()
1382 ret = ipu_irq_init(ipu); in ipu_probe()
1387 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), in ipu_probe()
1390 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); in ipu_probe()
1394 ret = ipu_add_client_devices(ipu, ipu_base); in ipu_probe()
1406 ipu_submodules_exit(ipu); in ipu_probe()
1408 ipu_irq_exit(ipu); in ipu_probe()
1411 clk_disable_unprepare(ipu->clk); in ipu_probe()
1417 struct ipu_soc *ipu = platform_get_drvdata(pdev); in ipu_remove() local
1420 ipu_submodules_exit(ipu); in ipu_remove()
1421 ipu_irq_exit(ipu); in ipu_remove()
1423 clk_disable_unprepare(ipu->clk); in ipu_remove()
1456 MODULE_DESCRIPTION("i.MX IPU v3 driver");