39 static void assert_iir_is_zero(struct xe_mmio *mmio, struct xe_reg reg)  in assert_iir_is_zero()  argument
41 	u32 val = xe_mmio_read32(mmio, reg);  in assert_iir_is_zero()
46 	drm_WARN(&mmio->tile->xe->drm, 1,  in assert_iir_is_zero()
49 	xe_mmio_write32(mmio, reg, 0xffffffff);  in assert_iir_is_zero()
50 	xe_mmio_read32(mmio, reg);  in assert_iir_is_zero()
51 	xe_mmio_write32(mmio, reg, 0xffffffff);  in assert_iir_is_zero()
52 	xe_mmio_read32(mmio, reg);  in assert_iir_is_zero()
61 	struct xe_mmio *mmio = &tile->mmio;  in unmask_and_enable()  local
67 	assert_iir_is_zero(mmio, IIR(irqregs));  in unmask_and_enable()
69 	xe_mmio_write32(mmio, IER(irqregs), bits);  in unmask_and_enable()
70 	xe_mmio_write32(mmio, IMR(irqregs), ~bits);  in unmask_and_enable()
73 	xe_mmio_read32(mmio, IMR(irqregs));  in unmask_and_enable()
79 	struct xe_mmio *mmio = &tile->mmio;  in mask_and_disable()  local
81 	xe_mmio_write32(mmio, IMR(irqregs), ~0);  in mask_and_disable()
83 	xe_mmio_read32(mmio, IMR(irqregs));  in mask_and_disable()
85 	xe_mmio_write32(mmio, IER(irqregs), 0);  in mask_and_disable()
88 	xe_mmio_write32(mmio, IIR(irqregs), ~0);  in mask_and_disable()
89 	xe_mmio_read32(mmio, IIR(irqregs));  in mask_and_disable()
90 	xe_mmio_write32(mmio, IIR(irqregs), ~0);  in mask_and_disable()
91 	xe_mmio_read32(mmio, IIR(irqregs));  in mask_and_disable()
96 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);  in xelp_intr_disable()  local
98 	xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);  in xelp_intr_disable()
106 	return xe_mmio_read32(mmio, GFX_MSTR_IRQ);  in xelp_intr_disable()
112 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);  in gu_misc_irq_ack()  local
118 	iir = xe_mmio_read32(mmio, IIR(GU_MISC_IRQ_OFFSET));  in gu_misc_irq_ack()
120 		xe_mmio_write32(mmio, IIR(GU_MISC_IRQ_OFFSET), iir);  in gu_misc_irq_ack()
127 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);  in xelp_intr_enable()  local
129 	xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);  in xelp_intr_enable()
131 		xe_mmio_read32(mmio, GFX_MSTR_IRQ);  in xelp_intr_enable()
138 	struct xe_mmio *mmio = &gt->mmio;  in xe_irq_enable_hwe()  local
165 		xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);  in xe_irq_enable_hwe()
167 			xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);  in xe_irq_enable_hwe()
170 		xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);  in xe_irq_enable_hwe()
171 		xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);  in xe_irq_enable_hwe()
173 			xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
175 			xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
177 			xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
179 			xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
181 			xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
183 			xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
188 		xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);  in xe_irq_enable_hwe()
191 		xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
192 		xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
193 		xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);  in xe_irq_enable_hwe()
207 			xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, gsc_mask | heci_mask);  in xe_irq_enable_hwe()
208 			xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~gsc_mask);  in xe_irq_enable_hwe()
211 			xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~(heci_mask << 16));  in xe_irq_enable_hwe()
218 			xe_mmio_write32(mmio, CRYPTO_RSVD_INTR_ENABLE, kcr_mask << 16);  in xe_irq_enable_hwe()
219 			xe_mmio_write32(mmio, CRYPTO_RSVD_INTR_MASK, ~(kcr_mask << 16));  in xe_irq_enable_hwe()
226 		   struct xe_mmio *mmio,  in gt_engine_identity()  argument
235 	xe_mmio_write32(mmio, IIR_REG_SELECTOR(bank), BIT(bit));  in gt_engine_identity()
243 		ident = xe_mmio_read32(mmio, INTR_IDENTITY_REG(bank));  in gt_engine_identity()
253 	xe_mmio_write32(mmio, INTR_IDENTITY_REG(bank), ident);  in gt_engine_identity()
310 	struct xe_mmio *mmio = &tile->mmio;  in gt_irq_handler()  local
322 		intr_dw[bank] = xe_mmio_read32(mmio, GT_INTR_DW(bank));  in gt_irq_handler()
324 			identity[bit] = gt_engine_identity(xe, mmio, bank, bit);  in gt_irq_handler()
325 		xe_mmio_write32(mmio, GT_INTR_DW(bank), intr_dw[bank]);  in gt_irq_handler()
397 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);  in dg1_intr_disable()  local
401 	xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0);  in dg1_intr_disable()
404 	val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);  in dg1_intr_disable()
408 	xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val);  in dg1_intr_disable()
415 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);  in dg1_intr_enable()  local
417 	xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);  in dg1_intr_enable()
419 		xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);  in dg1_intr_enable()
448 		struct xe_mmio *mmio = &tile->mmio;  in dg1_irq_handler()  local
453 		master_ctl = xe_mmio_read32(mmio, GFX_MSTR_IRQ);  in dg1_irq_handler()
457 		 * and all MMIO reads will be returned with all 1's. Ignore this  in dg1_irq_handler()
466 		xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);  in dg1_irq_handler()
491 	struct xe_mmio *mmio = &tile->mmio;  in gt_irq_reset()  local
499 	xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, 0);  in gt_irq_reset()
500 	xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, 0);  in gt_irq_reset()
502 		xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, 0);  in gt_irq_reset()
505 	xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK,	~0);  in gt_irq_reset()
506 	xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK,	~0);  in gt_irq_reset()
508 		xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~0);  in gt_irq_reset()
510 		xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~0);  in gt_irq_reset()
512 		xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~0);  in gt_irq_reset()
514 		xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~0);  in gt_irq_reset()
515 	xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK,	~0);  in gt_irq_reset()
516 	xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK,	~0);  in gt_irq_reset()
517 	xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK,	~0);  in gt_irq_reset()
519 		xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~0);  in gt_irq_reset()
521 		xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0);  in gt_irq_reset()
526 		xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0);  in gt_irq_reset()
527 		xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0);  in gt_irq_reset()
528 		xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~0);  in gt_irq_reset()
529 		xe_mmio_write32(mmio, CRYPTO_RSVD_INTR_ENABLE, 0);  in gt_irq_reset()
530 		xe_mmio_write32(mmio, CRYPTO_RSVD_INTR_MASK, ~0);  in gt_irq_reset()
533 	xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_ENABLE, 0);  in gt_irq_reset()
534 	xe_mmio_write32(mmio, GPM_WGBOXPERF_INTR_MASK,  ~0);  in gt_irq_reset()
535 	xe_mmio_write32(mmio, GUC_SG_INTR_ENABLE,	 0);  in gt_irq_reset()
536 	xe_mmio_write32(mmio, GUC_SG_INTR_MASK,		~0);  in gt_irq_reset()
566 	struct xe_mmio *mmio = &tile->mmio;  in dg1_irq_reset_mstr()  local
568 	xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0);  in dg1_irq_reset_mstr()