Lines Matching +full:no +full:- +full:reset +full:- +full:on +full:- +full:init
1 // SPDX-License-Identifier: MIT
49 u32 fw_size = gsc->fw.size; in memcpy_fw()
58 return -ENOMEM; in memcpy_fw()
60 xe_map_memcpy_from(xe, storage, &gsc->fw.bo->vmap, 0, fw_size); in memcpy_fw()
61 xe_map_memcpy_to(xe, &gsc->private->vmap, 0, storage, fw_size); in memcpy_fw()
62 xe_map_memset(xe, &gsc->private->vmap, fw_size, 0, gsc->private->size - fw_size); in memcpy_fw()
72 u64 offset = xe_bo_ggtt_addr(gsc->private); in emit_gsc_upload()
82 bb->cs[bb->len++] = GSC_FW_LOAD; in emit_gsc_upload()
83 bb->cs[bb->len++] = lower_32_bits(offset); in emit_gsc_upload()
84 bb->cs[bb->len++] = upper_32_bits(offset); in emit_gsc_upload()
85 bb->cs[bb->len++] = (gsc->private->size / SZ_4K) | GSC_FW_LOAD_LIMIT_VALID; in emit_gsc_upload()
87 job = xe_bb_create_job(gsc->q, bb); in emit_gsc_upload()
94 fence = dma_fence_get(&job->drm.s_fence->finished); in emit_gsc_upload()
103 return -ETIME; in emit_gsc_upload()
127 struct xe_uc_fw_version *compat = &gsc->fw.versions.found[XE_UC_FW_VER_COMPATIBILITY]; in query_compatibility_version()
148 wr_offset = xe_gsc_emit_header(xe, &bo->vmap, 0, HECI_MEADDRESS_MKHI, 0, in query_compatibility_version()
150 wr_offset = emit_version_query_msg(xe, &bo->vmap, wr_offset); in query_compatibility_version()
162 err = xe_gsc_read_out_header(xe, &bo->vmap, GSC_VER_PKT_SZ, in query_compatibility_version()
170 compat->major = version_query_rd(xe, &bo->vmap, rd_offset, proj_major); in query_compatibility_version()
171 compat->minor = version_query_rd(xe, &bo->vmap, rd_offset, compat_major); in query_compatibility_version()
172 compat->patch = version_query_rd(xe, &bo->vmap, rd_offset, compat_minor); in query_compatibility_version()
174 xe_gt_info(gt, "found GSC cv%u.%u.%u\n", compat->major, compat->minor, compat->patch); in query_compatibility_version()
183 return xe_mmio_read32(>->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) & in gsc_fw_is_loaded()
194 return xe_mmio_wait32(>->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE), in gsc_fw_wait()
206 /* we should only be here if the init step were successful */ in gsc_upload()
207 xe_assert(xe, xe_uc_fw_is_loadable(&gsc->fw) && gsc->q); in gsc_upload()
211 return -EEXIST; in gsc_upload()
221 * GSC is only killed by an FLR, so we need to trigger one on unload to in gsc_upload()
224 * using it when we release it to the system on driver unload. Note that in gsc_upload()
225 * this is not a problem of the unload per-se, because the GSC will not in gsc_upload()
227 * driver; therefore, no accesses will happen while Xe is not loaded, in gsc_upload()
228 * but if we re-load the driver then the GSC might wake up and try to in gsc_upload()
235 xe->needs_flr_on_fini = true; in gsc_upload()
253 err = xe_uc_fw_check_version_requirements(&gsc->fw); in gsc_upload()
267 if (XE_WA(tile->primary_gt, 14018094691)) { in gsc_upload_and_init()
268 fw_ref = xe_force_wake_get(gt_to_fw(tile->primary_gt), XE_FORCEWAKE_ALL); in gsc_upload_and_init()
275 xe_gt_mcr_multicast_write(tile->primary_gt, in gsc_upload_and_init()
282 if (XE_WA(tile->primary_gt, 14018094691)) in gsc_upload_and_init()
283 xe_force_wake_put(gt_to_fw(tile->primary_gt), fw_ref); in gsc_upload_and_init()
288 xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_TRANSFERRED); in gsc_upload_and_init()
296 if (xe_huc_is_authenticated(>->uc.huc, XE_HUC_AUTH_VIA_GUC)) in gsc_upload_and_init()
297 xe_huc_auth(>->uc.huc, XE_HUC_AUTH_VIA_GSC); in gsc_upload_and_init()
303 xe_gt_dbg(gt, "GSC proxy init completed\n"); in gsc_upload_and_init()
316 * Starting on Xe2, the GSCCS engine reset is a 2-step process. When the in gsc_er_complete()
317 * driver or the GuC hit the GDRST register, the CS is immediately reset in gsc_er_complete()
319 * background. While the shim reset is ongoing, the CS is able to accept in gsc_er_complete()
321 * be stalled until the reset is completed. This means that we can keep in gsc_er_complete()
323 * timeout is big enough to cover any delay introduced by the reset. in gsc_er_complete()
324 * When the shim reset completes, a specific CS interrupt is triggered, in gsc_er_complete()
326 * to see if the reset was successful or not. in gsc_er_complete()
328 * so it gets reset on MC6 entry. However, a reset failure stops MC6, in gsc_er_complete()
332 er_status = xe_mmio_read32(>->mmio, GSCI_TIMER_STATUS) & GSCI_TIMER_STATUS_VALUE; in gsc_er_complete()
342 return -EIO; in gsc_er_complete()
357 spin_lock_irq(&gsc->lock); in gsc_work()
358 actions = gsc->work_actions; in gsc_work()
359 gsc->work_actions = 0; in gsc_work()
360 spin_unlock_irq(&gsc->lock); in gsc_work()
373 if (ret && ret != -EEXIST) in gsc_work()
374 xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_LOAD_FAIL); in gsc_work()
376 xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_RUNNING); in gsc_work()
389 struct xe_gt *gt = hwe->gt; in xe_gsc_hwe_irq_handler()
390 struct xe_gsc *gsc = >->uc.gsc; in xe_gsc_hwe_irq_handler()
396 spin_lock(&gsc->lock); in xe_gsc_hwe_irq_handler()
397 gsc->work_actions |= GSC_ACTION_ER_COMPLETE; in xe_gsc_hwe_irq_handler()
398 spin_unlock(&gsc->lock); in xe_gsc_hwe_irq_handler()
400 queue_work(gsc->wq, &gsc->work); in xe_gsc_hwe_irq_handler()
410 gsc->fw.type = XE_UC_FW_TYPE_GSC; in xe_gsc_init()
411 INIT_WORK(&gsc->work, gsc_work); in xe_gsc_init()
412 spin_lock_init(&gsc->lock); in xe_gsc_init()
414 /* The GSC uC is only available on the media GT */ in xe_gsc_init()
415 if (tile->media_gt && (gt != tile->media_gt)) { in xe_gsc_init()
416 xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_NOT_SUPPORTED); in xe_gsc_init()
427 ret = xe_uc_fw_init(&gsc->fw); in xe_gsc_init()
428 if (!xe_uc_fw_is_enabled(&gsc->fw)) in xe_gsc_init()
434 if (ret && ret != -ENODEV) in xe_gsc_init()
440 xe_gt_err(gt, "GSC init failed with %d", ret); in xe_gsc_init()
448 if (gsc->wq) { in free_resources()
449 destroy_workqueue(gsc->wq); in free_resources()
450 gsc->wq = NULL; in free_resources()
453 if (gsc->q) { in free_resources()
454 xe_exec_queue_put(gsc->q); in free_resources()
455 gsc->q = NULL; in free_resources()
470 if (!xe_uc_fw_is_available(&gsc->fw)) in xe_gsc_init_post_hwconfig()
474 return -ENODEV; in xe_gsc_init_post_hwconfig()
483 BIT(hwe->logical_instance), 1, hwe, in xe_gsc_init_post_hwconfig()
492 wq = alloc_ordered_workqueue("gsc-ordered-wq", 0); in xe_gsc_init_post_hwconfig()
494 err = -ENOMEM; in xe_gsc_init_post_hwconfig()
498 gsc->private = bo; in xe_gsc_init_post_hwconfig()
499 gsc->q = q; in xe_gsc_init_post_hwconfig()
500 gsc->wq = wq; in xe_gsc_init_post_hwconfig()
502 err = devm_add_action_or_reset(xe->drm.dev, free_resources, gsc); in xe_gsc_init_post_hwconfig()
506 xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_LOADABLE); in xe_gsc_init_post_hwconfig()
522 if (!xe_uc_fw_is_loadable(&gsc->fw) || !gsc->q) in xe_gsc_load_start()
526 * The GSC HW is only reset by driver FLR or D3cold entry. We don't in xe_gsc_load_start()
527 * support the former at runtime, while the latter is only supported on in xe_gsc_load_start()
529 * load previously there is no need to try again because the HW is in xe_gsc_load_start()
533 if (xe_uc_fw_is_in_error_state(&gsc->fw)) in xe_gsc_load_start()
536 /* GSC FW survives GT reset and D3Hot */ in xe_gsc_load_start()
539 xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_RUNNING); in xe_gsc_load_start()
541 xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_TRANSFERRED); in xe_gsc_load_start()
545 spin_lock_irq(&gsc->lock); in xe_gsc_load_start()
546 gsc->work_actions |= GSC_ACTION_FW_LOAD; in xe_gsc_load_start()
547 spin_unlock_irq(&gsc->lock); in xe_gsc_load_start()
549 queue_work(gsc->wq, &gsc->work); in xe_gsc_load_start()
554 if (xe_uc_fw_is_loadable(&gsc->fw) && gsc->wq) in xe_gsc_wait_for_worker_completion()
555 flush_work(&gsc->work); in xe_gsc_wait_for_worker_completion()
563 if (!xe_uc_fw_is_loadable(&gsc->fw) || xe_uc_fw_is_in_error_state(&gsc->fw)) in xe_gsc_stop_prepare()
569 * If the GSC FW load or the proxy init are interrupted, the only way in xe_gsc_stop_prepare()
571 * Therefore, let's wait for the init to complete before stopping in xe_gsc_stop_prepare()
572 * operations. The proxy init is the last step, so we can just wait on in xe_gsc_stop_prepare()
577 xe_gt_err(gt, "failed to wait for GSC init completion before uc stop\n"); in xe_gsc_stop_prepare()
582 * GSC engine reset by writing a notification bit in the GS1 register and then
584 * for the FW to get prepare for the reset, so we need to wait for that amount
586 * After the reset is complete we need to then clear the GS1 register.
597 xe_mmio_rmw32(>->mmio, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set); in xe_gsc_wa_14015076503()
600 /* make sure the reset bit is clear when writing the CSR reg */ in xe_gsc_wa_14015076503()
601 xe_mmio_rmw32(>->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), in xe_gsc_wa_14015076503()
608 * xe_gsc_print_info - print info about GSC FW status
615 struct xe_mmio *mmio = >->mmio; in xe_gsc_print_info()
618 xe_uc_fw_print(&gsc->fw, p); in xe_gsc_print_info()
620 drm_printf(p, "\tfound security version %u\n", gsc->security_version); in xe_gsc_print_info()
622 if (!xe_uc_fw_is_enabled(&gsc->fw)) in xe_gsc_print_info()