Lines Matching +full:shader +full:- +full:db
40 * user-submitted CL and writing the validated copy out to the memory
55 /** Return the width in pixels of a 64-byte microtile. */
73 /** Return the height in pixels of a 64-byte microtile. */
91 * size_is_lt() - Returns whether a miplevel of the given size will
108 struct vc4_dev *vc4 = exec->dev; in vc4_use_bo()
112 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_use_bo()
115 if (hindex >= exec->bo_count) { in vc4_use_bo()
117 hindex, exec->bo_count); in vc4_use_bo()
120 obj = to_drm_gem_dma_obj(exec->bo[hindex]); in vc4_use_bo()
121 bo = to_vc4_bo(&obj->base); in vc4_use_bo()
123 if (bo->validated_shader) { in vc4_use_bo()
124 DRM_DEBUG("Trying to use shader BO as something other than " in vc4_use_bo()
125 "a shader\n"); in vc4_use_bo()
135 return vc4_use_bo(exec, exec->bo_index[gem_handles_packet_index]); in vc4_use_handle()
144 return (untrusted - 1 == exec->bin_u + pos); in validate_bin_pos()
167 struct vc4_dev *vc4 = exec->dev; in vc4_check_tex_size()
172 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_check_tex_size()
176 * (-2048,2047) offsets from the viewport center, so we should in vc4_check_tex_size()
210 size + offset > fbo->base.size) { in vc4_check_tex_size()
214 size, offset, fbo->base.size); in vc4_check_tex_size()
224 if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 1)) { in validate_flush()
226 return -EINVAL; in validate_flush()
228 exec->found_flush = true; in validate_flush()
236 if (exec->found_start_tile_binning_packet) { in validate_start_tile_binning()
238 return -EINVAL; in validate_start_tile_binning()
240 exec->found_start_tile_binning_packet = true; in validate_start_tile_binning()
242 if (!exec->found_tile_binning_mode_config_packet) { in validate_start_tile_binning()
244 return -EINVAL; in validate_start_tile_binning()
253 if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 2)) { in validate_increment_semaphore()
256 return -EINVAL; in validate_increment_semaphore()
258 exec->found_increment_semaphore_packet = true; in validate_increment_semaphore()
274 if (exec->shader_state_count == 0) { in validate_indexed_prim_list()
275 DRM_DEBUG("shader state must precede primitives\n"); in validate_indexed_prim_list()
276 return -EINVAL; in validate_indexed_prim_list()
278 shader_state = &exec->shader_state[exec->shader_state_count - 1]; in validate_indexed_prim_list()
280 if (max_index > shader_state->max_index) in validate_indexed_prim_list()
281 shader_state->max_index = max_index; in validate_indexed_prim_list()
285 return -EINVAL; in validate_indexed_prim_list()
287 if (offset > ib->base.size || in validate_indexed_prim_list()
288 (ib->base.size - offset) / index_size < length) { in validate_indexed_prim_list()
290 offset, length, index_size, ib->base.size); in validate_indexed_prim_list()
291 return -EINVAL; in validate_indexed_prim_list()
294 *(uint32_t *)(validated + 5) = ib->dma_addr + offset; in validate_indexed_prim_list()
308 if (exec->shader_state_count == 0) { in validate_gl_array_primitive()
309 DRM_DEBUG("shader state must precede primitives\n"); in validate_gl_array_primitive()
310 return -EINVAL; in validate_gl_array_primitive()
312 shader_state = &exec->shader_state[exec->shader_state_count - 1]; in validate_gl_array_primitive()
316 return -EINVAL; in validate_gl_array_primitive()
318 max_index = length + base_index - 1; in validate_gl_array_primitive()
320 if (max_index > shader_state->max_index) in validate_gl_array_primitive()
321 shader_state->max_index = max_index; in validate_gl_array_primitive()
329 uint32_t i = exec->shader_state_count++; in validate_gl_shader_state()
331 if (i >= exec->shader_state_size) { in validate_gl_shader_state()
332 DRM_DEBUG("More requests for shader states than declared\n"); in validate_gl_shader_state()
333 return -EINVAL; in validate_gl_shader_state()
336 exec->shader_state[i].addr = *(uint32_t *)untrusted; in validate_gl_shader_state()
337 exec->shader_state[i].max_index = 0; in validate_gl_shader_state()
339 if (exec->shader_state[i].addr & ~0xf) { in validate_gl_shader_state()
340 DRM_DEBUG("high bits set in GL shader rec reference\n"); in validate_gl_shader_state()
341 return -EINVAL; in validate_gl_shader_state()
344 *(uint32_t *)validated = (exec->shader_rec_p + in validate_gl_shader_state()
345 exec->shader_state[i].addr); in validate_gl_shader_state()
347 exec->shader_rec_p += in validate_gl_shader_state()
348 roundup(gl_shader_rec_size(exec->shader_state[i].addr), 16); in validate_gl_shader_state()
356 struct drm_device *dev = exec->exec_bo->base.dev; in validate_tile_binning_config()
363 if (exec->found_tile_binning_mode_config_packet) { in validate_tile_binning_config()
365 return -EINVAL; in validate_tile_binning_config()
367 exec->found_tile_binning_mode_config_packet = true; in validate_tile_binning_config()
369 exec->bin_tiles_x = *(uint8_t *)(untrusted + 12); in validate_tile_binning_config()
370 exec->bin_tiles_y = *(uint8_t *)(untrusted + 13); in validate_tile_binning_config()
371 tile_count = exec->bin_tiles_x * exec->bin_tiles_y; in validate_tile_binning_config()
374 if (exec->bin_tiles_x == 0 || in validate_tile_binning_config()
375 exec->bin_tiles_y == 0) { in validate_tile_binning_config()
377 exec->bin_tiles_x, exec->bin_tiles_y); in validate_tile_binning_config()
378 return -EINVAL; in validate_tile_binning_config()
384 return -EINVAL; in validate_tile_binning_config()
389 if (bin_slot != -EINTR && bin_slot != -ERESTARTSYS) { in validate_tile_binning_config()
399 exec->bin_slots |= BIT(bin_slot); in validate_tile_binning_config()
400 bin_addr = vc4->bin_bo->base.dma_addr + bin_slot * vc4->bin_alloc_size; in validate_tile_binning_config()
408 exec->tile_alloc_offset = bin_addr + roundup(tile_state_size, 4096); in validate_tile_binning_config()
420 *(uint32_t *)(validated + 0) = exec->tile_alloc_offset; in validate_tile_binning_config()
422 *(uint32_t *)(validated + 4) = (bin_addr + vc4->bin_alloc_size - in validate_tile_binning_config()
423 exec->tile_alloc_offset); in validate_tile_binning_config()
433 memcpy(exec->bo_index, untrusted, sizeof(exec->bo_index)); in validate_gem_handles()
491 uint32_t len = exec->args->bin_cl_size; in vc4_validate_bin_cl()
495 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_validate_bin_cl()
496 return -ENODEV; in vc4_validate_bin_cl()
507 return -EINVAL; in vc4_validate_bin_cl()
511 if (!info->name) { in vc4_validate_bin_cl()
514 return -EINVAL; in vc4_validate_bin_cl()
517 if (src_offset + info->len > len) { in vc4_validate_bin_cl()
520 src_offset, cmd, info->name, info->len, in vc4_validate_bin_cl()
522 return -EINVAL; in vc4_validate_bin_cl()
526 memcpy(dst_pkt, src_pkt, info->len); in vc4_validate_bin_cl()
528 if (info->func && info->func(exec, in vc4_validate_bin_cl()
532 src_offset, cmd, info->name); in vc4_validate_bin_cl()
533 return -EINVAL; in vc4_validate_bin_cl()
536 src_offset += info->len; in vc4_validate_bin_cl()
539 dst_offset += info->len; in vc4_validate_bin_cl()
546 exec->ct0ea = exec->ct0ca + dst_offset; in vc4_validate_bin_cl()
548 if (!exec->found_start_tile_binning_packet) { in vc4_validate_bin_cl()
550 return -EINVAL; in vc4_validate_bin_cl()
560 if (!exec->found_increment_semaphore_packet || !exec->found_flush) { in vc4_validate_bin_cl()
563 return -EINVAL; in vc4_validate_bin_cl()
576 uint32_t p0 = *(uint32_t *)(uniform_data_u + sample->p_offset[0]); in reloc_tex()
577 uint32_t p1 = *(uint32_t *)(uniform_data_u + sample->p_offset[1]); in reloc_tex()
578 uint32_t p2 = (sample->p_offset[2] != ~0 ? in reloc_tex()
579 *(uint32_t *)(uniform_data_u + sample->p_offset[2]) : 0); in reloc_tex()
580 uint32_t p3 = (sample->p_offset[3] != ~0 ? in reloc_tex()
581 *(uint32_t *)(uniform_data_u + sample->p_offset[3]) : 0); in reloc_tex()
582 uint32_t *validated_p0 = exec->uniforms_v + sample->p_offset[0]; in reloc_tex()
596 if (sample->is_direct) { in reloc_tex()
597 uint32_t remaining_size = tex->base.size - p0; in reloc_tex()
599 if (p0 > tex->base.size - 4) { in reloc_tex()
603 if (p1 > remaining_size - 4) { in reloc_tex()
608 *validated_p0 = tex->dma_addr + p0; in reloc_tex()
659 /* ETC1 is arranged as 64-bit blocks, where each block is 4x4 in reloc_tex()
725 DRM_DEBUG("Level %d (%dx%d -> %dx%d) size %db " in reloc_tex()
733 offset -= level_size; in reloc_tex()
736 *validated_p0 = tex->dma_addr + p0; in reloc_tex()
740 DRM_INFO("Texture p0 at %d: 0x%08x\n", sample->p_offset[0], p0); in reloc_tex()
741 DRM_INFO("Texture p1 at %d: 0x%08x\n", sample->p_offset[1], p1); in reloc_tex()
742 DRM_INFO("Texture p2 at %d: 0x%08x\n", sample->p_offset[2], p2); in reloc_tex()
743 DRM_INFO("Texture p3 at %d: 0x%08x\n", sample->p_offset[3], p3); in reloc_tex()
764 nr_attributes = state->addr & 0x7; in validate_gl_shader_rec()
767 packet_size = gl_shader_rec_size(state->addr); in validate_gl_shader_rec()
770 if (nr_relocs * 4 > exec->shader_rec_size) { in validate_gl_shader_rec()
771 DRM_DEBUG("overflowed shader recs reading %d handles " in validate_gl_shader_rec()
773 nr_relocs, exec->shader_rec_size); in validate_gl_shader_rec()
774 return -EINVAL; in validate_gl_shader_rec()
776 src_handles = exec->shader_rec_u; in validate_gl_shader_rec()
777 exec->shader_rec_u += nr_relocs * 4; in validate_gl_shader_rec()
778 exec->shader_rec_size -= nr_relocs * 4; in validate_gl_shader_rec()
780 if (packet_size > exec->shader_rec_size) { in validate_gl_shader_rec()
781 DRM_DEBUG("overflowed shader recs copying %db packet " in validate_gl_shader_rec()
783 packet_size, exec->shader_rec_size); in validate_gl_shader_rec()
784 return -EINVAL; in validate_gl_shader_rec()
786 pkt_u = exec->shader_rec_u; in validate_gl_shader_rec()
787 pkt_v = exec->shader_rec_v; in validate_gl_shader_rec()
789 exec->shader_rec_u += packet_size; in validate_gl_shader_rec()
790 /* Shader recs have to be aligned to 16 bytes (due to the attribute in validate_gl_shader_rec()
791 * flags being in the low bytes), so round the next validated shader in validate_gl_shader_rec()
793 * relocations in a shader rec packet. in validate_gl_shader_rec()
795 BUG_ON(roundup(packet_size, 16) - packet_size > nr_relocs * 4); in validate_gl_shader_rec()
796 exec->shader_rec_v += roundup(packet_size, 16); in validate_gl_shader_rec()
797 exec->shader_rec_size -= packet_size; in validate_gl_shader_rec()
800 if (src_handles[i] > exec->bo_count) { in validate_gl_shader_rec()
801 DRM_DEBUG("Shader handle %d too big\n", src_handles[i]); in validate_gl_shader_rec()
802 return -EINVAL; in validate_gl_shader_rec()
805 bo[i] = to_drm_gem_dma_obj(exec->bo[src_handles[i]]); in validate_gl_shader_rec()
807 return -EINVAL; in validate_gl_shader_rec()
812 return -EINVAL; in validate_gl_shader_rec()
816 to_vc4_bo(&bo[0]->base)->validated_shader->is_threaded) { in validate_gl_shader_rec()
818 return -EINVAL; in validate_gl_shader_rec()
821 if (to_vc4_bo(&bo[1]->base)->validated_shader->is_threaded || in validate_gl_shader_rec()
822 to_vc4_bo(&bo[2]->base)->validated_shader->is_threaded) { in validate_gl_shader_rec()
824 return -EINVAL; in validate_gl_shader_rec()
835 *(uint32_t *)(pkt_v + o) = bo[i]->dma_addr + src_offset; in validate_gl_shader_rec()
840 return -EINVAL; in validate_gl_shader_rec()
843 validated_shader = to_vc4_bo(&bo[i]->base)->validated_shader; in validate_gl_shader_rec()
845 return -EINVAL; in validate_gl_shader_rec()
847 if (validated_shader->uniforms_src_size > in validate_gl_shader_rec()
848 exec->uniforms_size) { in validate_gl_shader_rec()
850 return -EINVAL; in validate_gl_shader_rec()
853 texture_handles_u = exec->uniforms_u; in validate_gl_shader_rec()
855 validated_shader->num_texture_samples); in validate_gl_shader_rec()
857 memcpy(exec->uniforms_v, uniform_data_u, in validate_gl_shader_rec()
858 validated_shader->uniforms_size); in validate_gl_shader_rec()
861 tex < validated_shader->num_texture_samples; in validate_gl_shader_rec()
865 &validated_shader->texture_samples[tex], in validate_gl_shader_rec()
868 return -EINVAL; in validate_gl_shader_rec()
872 /* Fill in the uniform slots that need this shader's in validate_gl_shader_rec()
873 * start-of-uniforms address (used for resetting the uniform in validate_gl_shader_rec()
877 uni < validated_shader->num_uniform_addr_offsets; in validate_gl_shader_rec()
879 uint32_t o = validated_shader->uniform_addr_offsets[uni]; in validate_gl_shader_rec()
880 ((uint32_t *)exec->uniforms_v)[o] = exec->uniforms_p; in validate_gl_shader_rec()
883 *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p; in validate_gl_shader_rec()
885 exec->uniforms_u += validated_shader->uniforms_src_size; in validate_gl_shader_rec()
886 exec->uniforms_v += validated_shader->uniforms_size; in validate_gl_shader_rec()
887 exec->uniforms_p += validated_shader->uniforms_size; in validate_gl_shader_rec()
899 if (state->addr & 0x8) in validate_gl_shader_rec()
902 if (vbo->base.size < offset || in validate_gl_shader_rec()
903 vbo->base.size - offset < attr_size) { in validate_gl_shader_rec()
905 offset, attr_size, vbo->base.size); in validate_gl_shader_rec()
906 return -EINVAL; in validate_gl_shader_rec()
910 max_index = ((vbo->base.size - offset - attr_size) / in validate_gl_shader_rec()
912 if (state->max_index > max_index) { in validate_gl_shader_rec()
915 state->max_index, max_index); in validate_gl_shader_rec()
916 return -EINVAL; in validate_gl_shader_rec()
920 *(uint32_t *)(pkt_v + o) = vbo->dma_addr + offset; in validate_gl_shader_rec()
934 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_validate_shader_recs()
935 return -ENODEV; in vc4_validate_shader_recs()
937 for (i = 0; i < exec->shader_state_count; i++) { in vc4_validate_shader_recs()
938 ret = validate_gl_shader_rec(dev, exec, &exec->shader_state[i]); in vc4_validate_shader_recs()