Lines Matching +full:0 +full:x2000
37 const u32 hoff = head * 0x800; in tu102_sor_dp_vcpi()
39 nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn); in tu102_sor_dp_vcpi()
40 nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot); in tu102_sor_dp_vcpi()
49 u32 dpctrl = 0x00000000; in tu102_sor_dp_links()
50 u32 clksor = 0x00000000; in tu102_sor_dp_links()
55 dpctrl |= 0x40000000; in tu102_sor_dp_links()
57 dpctrl |= 0x00004000; in tu102_sor_dp_links()
59 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor); in tu102_sor_dp_links()
63 nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000); in tu102_sor_dp_links()
64 nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001); in tu102_sor_dp_links()
66 nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl); in tu102_sor_dp_links()
67 return 0; in tu102_sor_dp_links()
72 .lanes = { 0, 1, 2, 3 },
102 u32 hda = nvkm_rd32(device, 0x08a15c); in tu102_sor_new()
116 if (nvkm_rd32(device, 0x6254e8) & 0x00000002) { in tu102_disp_init()
117 nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000); in tu102_disp_init()
119 if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002)) in tu102_disp_init()
121 ) < 0) in tu102_disp_init()
126 tmp = 0x00000021; /*XXX*/ in tu102_disp_init()
127 nvkm_wr32(device, 0x640008, tmp); in tu102_disp_init()
130 for (i = 0; i < disp->sor.nr; i++) { in tu102_disp_init()
131 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); in tu102_disp_init()
132 nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i); in tu102_disp_init()
133 nvkm_wr32(device, 0x640144 + (i * 0x08), tmp); in tu102_disp_init()
141 tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); in tu102_disp_init()
142 nvkm_wr32(device, 0x640048 + (id * 0x020), tmp); in tu102_disp_init()
145 for (j = 0; j < 5 * 4; j += 4) { in tu102_disp_init()
146 tmp = nvkm_rd32(device, 0x616140 + (id * 0x800) + j); in tu102_disp_init()
147 nvkm_wr32(device, 0x640680 + (id * 0x20) + j, tmp); in tu102_disp_init()
152 for (i = 0; i < disp->wndw.nr; i++) { in tu102_disp_init()
153 nvkm_mask(device, 0x640004, 1 << i, 1 << i); in tu102_disp_init()
154 for (j = 0; j < 6 * 4; j += 4) { in tu102_disp_init()
155 tmp = nvkm_rd32(device, 0x630100 + (i * 0x800) + j); in tu102_disp_init()
156 nvkm_mask(device, 0x640780 + (i * 0x20) + j, 0xffffffff, tmp); in tu102_disp_init()
158 nvkm_mask(device, 0x64000c, 0x00000100, 0x00000100); in tu102_disp_init()
162 for (i = 0; i < 3; i++) { in tu102_disp_init()
163 tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04)); in tu102_disp_init()
164 nvkm_wr32(device, 0x640010 + (i * 0x04), tmp); in tu102_disp_init()
167 nvkm_mask(device, 0x610078, 0x00000001, 0x00000001); in tu102_disp_init()
171 case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break; in tu102_disp_init()
172 case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break; in tu102_disp_init()
173 case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break; in tu102_disp_init()
177 nvkm_wr32(device, 0x610010, 0x00000008 | tmp); in tu102_disp_init()
178 nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); in tu102_disp_init()
181 nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */ in tu102_disp_init()
182 nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */ in tu102_disp_init()
185 nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | in tu102_disp_init()
186 0x00000001); /* MSK. */ in tu102_disp_init()
187 nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */ in tu102_disp_init()
190 nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ in tu102_disp_init()
191 nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */ in tu102_disp_init()
194 nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ in tu102_disp_init()
195 nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */ in tu102_disp_init()
200 nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */ in tu102_disp_init()
201 nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */ in tu102_disp_init()
205 nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */ in tu102_disp_init()
206 nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */ in tu102_disp_init()
207 return 0; in tu102_disp_init()
221 .ramht_size = 0x2000,
222 .root = { 0, 0,TU102_DISP },
225 {{ 0, 0,TU102_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs },
226 {{ 0, 0,TU102_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm },
227 {{ 0, 0,TU102_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gv100_disp_core },
228 {{ 0, 0,TU102_DISP_WINDOW_CHANNEL_DMA }, nvkm_disp_wndw_new, &gv100_disp_wndw },