40 #define DSI_PHY_28NM_QUIRK_PHY_LP	BIT(0)
110 	writel(0, base + REG_DSI_28nm_PHY_PLL_TEST_CFG);  in pll_28nm_software_reset()
136 	for (i = 0; i < LPFR_LUT_SIZE; i++)  in dsi_pll_28nm_clk_set_rate()
147 	writel(0x70, base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG);  in dsi_pll_28nm_clk_set_rate()
148 	writel(0x15, base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG);  in dsi_pll_28nm_clk_set_rate()
157 		refclk_cfg = 0x0;  in dsi_pll_28nm_clk_set_rate()
158 		frac_n_mode = 0;  in dsi_pll_28nm_clk_set_rate()
172 	rem = 0;  in dsi_pll_28nm_clk_set_rate()
176 		sdm_cfg0 = 0x0;  in dsi_pll_28nm_clk_set_rate()
177 		sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0);  in dsi_pll_28nm_clk_set_rate()
179 				(u32)(((div_fbx1000 / 1000) & 0x3f) - 1));  in dsi_pll_28nm_clk_set_rate()
181 		sdm_cfg2 = frac_n_value & 0xff;  in dsi_pll_28nm_clk_set_rate()
185 				(u32)(((div_fbx1000 / 1000) & 0x3f) - 1));  in dsi_pll_28nm_clk_set_rate()
186 		sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0);  in dsi_pll_28nm_clk_set_rate()
187 		sdm_cfg2 = 0;  in dsi_pll_28nm_clk_set_rate()
188 		sdm_cfg3 = 0;  in dsi_pll_28nm_clk_set_rate()
200 	writel(0x02, base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG);  in dsi_pll_28nm_clk_set_rate()
201 	writel(0x2b, base + REG_DSI_28nm_PHY_PLL_CAL_CFG3);  in dsi_pll_28nm_clk_set_rate()
202 	writel(0x06, base + REG_DSI_28nm_PHY_PLL_CAL_CFG4);  in dsi_pll_28nm_clk_set_rate()
203 	writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);  in dsi_pll_28nm_clk_set_rate()
210 	writel(0, base + REG_DSI_28nm_PHY_PLL_SDM_CFG4);  in dsi_pll_28nm_clk_set_rate()
219 	writel(0x00, base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG);  in dsi_pll_28nm_clk_set_rate()
220 	writel(0x31, base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG);  in dsi_pll_28nm_clk_set_rate()
222 	writel(0x12, base + REG_DSI_28nm_PHY_PLL_CAL_CFG0);  in dsi_pll_28nm_clk_set_rate()
223 	writel(0x30, base + REG_DSI_28nm_PHY_PLL_CAL_CFG6);  in dsi_pll_28nm_clk_set_rate()
224 	writel(0x00, base + REG_DSI_28nm_PHY_PLL_CAL_CFG7);  in dsi_pll_28nm_clk_set_rate()
225 	writel(0x60, base + REG_DSI_28nm_PHY_PLL_CAL_CFG8);  in dsi_pll_28nm_clk_set_rate()
226 	writel(0x00, base + REG_DSI_28nm_PHY_PLL_CAL_CFG9);  in dsi_pll_28nm_clk_set_rate()
227 	writel(cal_cfg10 & 0xff, base + REG_DSI_28nm_PHY_PLL_CAL_CFG10);  in dsi_pll_28nm_clk_set_rate()
228 	writel(cal_cfg11 & 0xff, base + REG_DSI_28nm_PHY_PLL_CAL_CFG11);  in dsi_pll_28nm_clk_set_rate()
229 	writel(0x20, base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG);  in dsi_pll_28nm_clk_set_rate()
231 	return 0;  in dsi_pll_28nm_clk_set_rate()
323 	for (i = 0; i < 2; i++) {  in _dsi_pll_28nm_vco_prepare_hpm()
325 		writel(0x0c, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);  in _dsi_pll_28nm_vco_prepare_hpm()
327 		writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);  in _dsi_pll_28nm_vco_prepare_hpm()
371 	return locked ? 0 : -EINVAL;  in _dsi_pll_28nm_vco_prepare_hpm()
380 		return 0;  in dsi_pll_28nm_vco_prepare_hpm()
382 	for (i = 0; i < 3; i++) {  in dsi_pll_28nm_vco_prepare_hpm()
386 			return 0;  in dsi_pll_28nm_vco_prepare_hpm()
411 	writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1);  in dsi_pll_28nm_vco_prepare_8226()
426 	for (i = 0; i < 7; i++) {  in dsi_pll_28nm_vco_prepare_8226()
428 		writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);  in dsi_pll_28nm_vco_prepare_8226()
429 		writel(0x0c, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);  in dsi_pll_28nm_vco_prepare_8226()
431 		writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);  in dsi_pll_28nm_vco_prepare_8226()
445 		writel(0x00, base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG);  in dsi_pll_28nm_vco_prepare_8226()
464 	return locked ? 0 : -EINVAL;  in dsi_pll_28nm_vco_prepare_8226()
479 		return 0;  in dsi_pll_28nm_vco_prepare_lp()
487 	writel(0x34, base + REG_DSI_28nm_PHY_PLL_CAL_CFG1);  in dsi_pll_28nm_vco_prepare_lp()
504 	writel(0x04, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);  in dsi_pll_28nm_vco_prepare_lp()
506 	writel(0x05, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2);  in dsi_pll_28nm_vco_prepare_lp()
519 	return 0;  in dsi_pll_28nm_vco_prepare_lp()
531 	writel(0, pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG);  in dsi_pll_28nm_vco_unprepare()
594 		cached_state->vco_rate = 0;  in dsi_28nm_pll_save_state()
605 					cached_state->vco_rate, 0);  in dsi_28nm_pll_restore_state()
616 	return 0;  in dsi_28nm_pll_restore_state()
654 			0, 4, 0, NULL);  in pll_28nm_register()
666 			&pll_28nm->clk_hw, 0, pll_28nm->phy->pll_base +  in pll_28nm_register()
668 			0, 8, 0, NULL);  in pll_28nm_register()
679 				REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);  in pll_28nm_register()
690 	return 0;  in pll_28nm_register()
716 	return 0;  in dsi_pll_28nm_init()
748 	writel(DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0),  in dsi_28nm_dphy_set_timing()
756 	writel(0x0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);  in dsi_28nm_phy_regulator_enable_dcdc()
758 	writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5);  in dsi_28nm_phy_regulator_enable_dcdc()
759 	writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3);  in dsi_28nm_phy_regulator_enable_dcdc()
760 	writel(0x3, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2);  in dsi_28nm_phy_regulator_enable_dcdc()
761 	writel(0x9, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1);  in dsi_28nm_phy_regulator_enable_dcdc()
762 	writel(0x7, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);  in dsi_28nm_phy_regulator_enable_dcdc()
763 	writel(0x20, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4);  in dsi_28nm_phy_regulator_enable_dcdc()
764 	writel(0x00, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);  in dsi_28nm_phy_regulator_enable_dcdc()
771 	writel(0x0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0);  in dsi_28nm_phy_regulator_enable_ldo()
772 	writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG);  in dsi_28nm_phy_regulator_enable_ldo()
773 	writel(0x7, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5);  in dsi_28nm_phy_regulator_enable_ldo()
774 	writel(0, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3);  in dsi_28nm_phy_regulator_enable_ldo()
775 	writel(0x1, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2);  in dsi_28nm_phy_regulator_enable_ldo()
776 	writel(0x1, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1);  in dsi_28nm_phy_regulator_enable_ldo()
777 	writel(0x20, base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4);  in dsi_28nm_phy_regulator_enable_ldo()
780 		writel(0x05, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);  in dsi_28nm_phy_regulator_enable_ldo()
782 		writel(0x0d, phy->base + REG_DSI_28nm_PHY_LDO_CNTRL);  in dsi_28nm_phy_regulator_enable_ldo()
788 		writel(0, phy->reg_base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG);  in dsi_28nm_phy_regulator_ctrl()
815 	writel(0xff, base + REG_DSI_28nm_PHY_STRENGTH_0);  in dsi_28nm_phy_enable()
821 	writel(0x00, base + REG_DSI_28nm_PHY_CTRL_1);  in dsi_28nm_phy_enable()
822 	writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0);  in dsi_28nm_phy_enable()
824 	writel(0x6, base + REG_DSI_28nm_PHY_STRENGTH_1);  in dsi_28nm_phy_enable()
826 	for (i = 0; i < 4; i++) {  in dsi_28nm_phy_enable()
827 		writel(0, base + REG_DSI_28nm_PHY_LN_CFG_0(i));  in dsi_28nm_phy_enable()
828 		writel(0, base + REG_DSI_28nm_PHY_LN_CFG_1(i));  in dsi_28nm_phy_enable()
829 		writel(0, base + REG_DSI_28nm_PHY_LN_CFG_2(i));  in dsi_28nm_phy_enable()
830 		writel(0, base + REG_DSI_28nm_PHY_LN_CFG_3(i));  in dsi_28nm_phy_enable()
831 		writel(0, base + REG_DSI_28nm_PHY_LN_CFG_4(i));  in dsi_28nm_phy_enable()
832 		writel(0, base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i));  in dsi_28nm_phy_enable()
833 		writel(0, base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i));  in dsi_28nm_phy_enable()
834 		writel(0x1, base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i));  in dsi_28nm_phy_enable()
835 		writel(0x97, base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i));  in dsi_28nm_phy_enable()
838 	writel(0, base + REG_DSI_28nm_PHY_LNCK_CFG_4);  in dsi_28nm_phy_enable()
839 	writel(0xc0, base + REG_DSI_28nm_PHY_LNCK_CFG_1);  in dsi_28nm_phy_enable()
840 	writel(0x1, base + REG_DSI_28nm_PHY_LNCK_TEST_STR0);  in dsi_28nm_phy_enable()
841 	writel(0xbb, base + REG_DSI_28nm_PHY_LNCK_TEST_STR1);  in dsi_28nm_phy_enable()
843 	writel(0x5f, base + REG_DSI_28nm_PHY_CTRL_0);  in dsi_28nm_phy_enable()
852 	return 0;  in dsi_28nm_phy_enable()
857 	writel(0, phy->base + REG_DSI_28nm_PHY_CTRL_0);  in dsi_28nm_phy_disable()
884 	.io_start = { 0xfd922b00, 0xfd923100 },
901 	.io_start = { 0x1a94400, 0x1a96400 },
918 	.io_start = { 0x1a98500 },
936 	.io_start = { 0xfd922b00 },
954 	.io_start = { 0x1a94400, 0x1a96400 },