1 // SPDX-License-Identifier: GPL-2.0-only
25 	struct device *dev = &mdp5_kms->pdev->dev;  in mdp5_hw_init()
54 	spin_lock_irqsave(&mdp5_kms->resource_lock, flags);  in mdp5_hw_init()
56 	spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);  in mdp5_hw_init()
58 	mdp5_ctlm_hw_reset(mdp5_kms->ctlm);  in mdp5_hw_init()
75 	return to_mdp5_global_state(mdp5_kms->glob_state.state);  in mdp5_get_existing_global_state()
84 	struct msm_drm_private *priv = s->dev->dev_private;  in mdp5_get_global_state()
85 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));  in mdp5_get_global_state()
88 	priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);  in mdp5_get_global_state()
100 	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);  in mdp5_global_duplicate_state()
104 	__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);  in mdp5_global_duplicate_state()
106 	return &state->base;  in mdp5_global_duplicate_state()
122 	if (mdp5_state->mdp5_kms->smp)  in mdp5_global_print_state()
123 		mdp5_smp_dump(mdp5_state->mdp5_kms->smp, p, mdp5_state);  in mdp5_global_print_state()
138 		return -ENOMEM;  in mdp5_global_obj_init()
140 	state->mdp5_kms = mdp5_kms;  in mdp5_global_obj_init()
142 	drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state,  in mdp5_global_obj_init()
143 				    &state->base,  in mdp5_global_obj_init()
151 	pm_runtime_get_sync(&mdp5_kms->pdev->dev);  in mdp5_enable_commit()
157 	pm_runtime_put_sync(&mdp5_kms->pdev->dev);  in mdp5_disable_commit()
167 	if (mdp5_kms->smp)  in mdp5_prepare_commit()
168 		mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp);  in mdp5_prepare_commit()
181 	for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask)  in mdp5_wait_flush()
192 	if (mdp5_kms->smp)  in mdp5_complete_commit()
193 		mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp);  in mdp5_complete_commit()
201 	struct msm_gem_address_space *aspace = kms->aspace;  in mdp5_kms_destroy()
204 		aspace->mmu->funcs->detach(aspace->mmu);  in mdp5_kms_destroy()
208 	mdp_kms_destroy(&mdp5_kms->base);  in mdp5_kms_destroy()
236 	mdp5_kms->enable_count--;  in mdp5_disable()
237 	WARN_ON(mdp5_kms->enable_count < 0);  in mdp5_disable()
239 	clk_disable_unprepare(mdp5_kms->tbu_rt_clk);  in mdp5_disable()
240 	clk_disable_unprepare(mdp5_kms->tbu_clk);  in mdp5_disable()
241 	clk_disable_unprepare(mdp5_kms->ahb_clk);  in mdp5_disable()
242 	clk_disable_unprepare(mdp5_kms->axi_clk);  in mdp5_disable()
243 	clk_disable_unprepare(mdp5_kms->core_clk);  in mdp5_disable()
244 	clk_disable_unprepare(mdp5_kms->lut_clk);  in mdp5_disable()
253 	mdp5_kms->enable_count++;  in mdp5_enable()
255 	clk_prepare_enable(mdp5_kms->ahb_clk);  in mdp5_enable()
256 	clk_prepare_enable(mdp5_kms->axi_clk);  in mdp5_enable()
257 	clk_prepare_enable(mdp5_kms->core_clk);  in mdp5_enable()
258 	clk_prepare_enable(mdp5_kms->lut_clk);  in mdp5_enable()
259 	clk_prepare_enable(mdp5_kms->tbu_clk);  in mdp5_enable()
260 	clk_prepare_enable(mdp5_kms->tbu_rt_clk);  in mdp5_enable()
269 	struct drm_device *dev = mdp5_kms->dev;  in construct_encoder()
274 		DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n");  in construct_encoder()
283 	const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;  in get_dsi_id_from_intf()
284 	const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);  in get_dsi_id_from_intf()
296 	return -EINVAL;  in get_dsi_id_from_intf()
302 	struct drm_device *dev = mdp5_kms->dev;  in modeset_init_intf()
303 	struct msm_drm_private *priv = dev->dev_private;  in modeset_init_intf()
304 	struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm;  in modeset_init_intf()
309 	switch (intf->type) {  in modeset_init_intf()
311 		DRM_DEV_INFO(dev->dev, "Skipping eDP interface %d\n", intf->num);  in modeset_init_intf()
314 		if (!priv->hdmi)  in modeset_init_intf()
317 		ctl = mdp5_ctlm_request(ctlm, intf->num);  in modeset_init_intf()
319 			ret = -EINVAL;  in modeset_init_intf()
329 		ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);  in modeset_init_intf()
334 					mdp5_cfg_get_hw_config(mdp5_kms->cfg);  in modeset_init_intf()
335 		int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);  in modeset_init_intf()
337 		if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) {  in modeset_init_intf()
338 			DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n",  in modeset_init_intf()
339 				intf->num);  in modeset_init_intf()
340 			ret = -EINVAL;  in modeset_init_intf()
344 		if (!priv->dsi[dsi_id])  in modeset_init_intf()
347 		ctl = mdp5_ctlm_request(ctlm, intf->num);  in modeset_init_intf()
349 			ret = -EINVAL;  in modeset_init_intf()
359 		ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);  in modeset_init_intf()
361 			mdp5_encoder_set_intf_mode(encoder, msm_dsi_is_cmd_mode(priv->dsi[dsi_id]));  in modeset_init_intf()
366 		DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type);  in modeset_init_intf()
367 		ret = -EINVAL;  in modeset_init_intf()
376 	struct drm_device *dev = mdp5_kms->dev;  in modeset_init()
377 	struct msm_drm_private *priv = dev->dev_private;  in modeset_init()
389 	for (i = 0; i < mdp5_kms->num_intfs; i++) {  in modeset_init()
390 		ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]);  in modeset_init()
404 	num_crtcs = min(num_encoders, mdp5_kms->num_hwmixers);  in modeset_init()
411 	for (i = 0; i < mdp5_kms->num_hwpipes; i++) {  in modeset_init()
412 		struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i];  in modeset_init()
418 		else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR)  in modeset_init()
426 			DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret);  in modeset_init()
442 			DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret);  in modeset_init()
445 		priv->num_crtcs++;  in modeset_init()
453 		encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;  in modeset_init()
464 	struct device *dev = &mdp5_kms->pdev->dev;  in read_mdp_hw_revision()
480 	struct device *dev = &pdev->dev;  in get_clk()
498 	struct msm_drm_private *priv = dev->dev_private;  in mdp5_kms_init()
502 	struct msm_kms *kms = priv->kms;  in mdp5_kms_init()
506 	ret = mdp5_init(to_platform_device(dev->dev), dev);  in mdp5_kms_init()
512 	pdev = mdp5_kms->pdev;  in mdp5_kms_init()
514 	ret = mdp_kms_init(&mdp5_kms->base, &kms_funcs);  in mdp5_kms_init()
516 		DRM_DEV_ERROR(&pdev->dev, "failed to init kms\n");  in mdp5_kms_init()
520 	config = mdp5_cfg_get_config(mdp5_kms->cfg);  in mdp5_kms_init()
526 	pm_runtime_get_sync(&pdev->dev);  in mdp5_kms_init()
528 		if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||  in mdp5_kms_init()
529 		    !config->hw->intf.base[i])  in mdp5_kms_init()
537 	aspace = msm_kms_init_aspace(mdp5_kms->dev);  in mdp5_kms_init()
543 	kms->aspace = aspace;  in mdp5_kms_init()
545 	pm_runtime_put_sync(&pdev->dev);  in mdp5_kms_init()
549 		DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret);  in mdp5_kms_init()
553 	dev->mode_config.min_width = 0;  in mdp5_kms_init()
554 	dev->mode_config.min_height = 0;  in mdp5_kms_init()
555 	dev->mode_config.max_width = 0xffff;  in mdp5_kms_init()
556 	dev->mode_config.max_height = 0xffff;  in mdp5_kms_init()
558 	dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */  in mdp5_kms_init()
559 	dev->vblank_disable_immediate = true;  in mdp5_kms_init()
571 	if (mdp5_kms->rpm_enabled)  in mdp5_destroy()
572 		pm_runtime_disable(&mdp5_kms->pdev->dev);  in mdp5_destroy()
574 	drm_atomic_private_obj_fini(&mdp5_kms->glob_state);  in mdp5_destroy()
581 	struct drm_device *dev = mdp5_kms->dev;  in construct_pipes()
590 			DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n",  in construct_pipes()
594 		hwpipe->idx = mdp5_kms->num_hwpipes;  in construct_pipes()
595 		mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe;  in construct_pipes()
618 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);  in hwpipe_init()
621 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,  in hwpipe_init()
622 			hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);  in hwpipe_init()
627 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,  in hwpipe_init()
628 			hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);  in hwpipe_init()
633 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,  in hwpipe_init()
634 			hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);  in hwpipe_init()
639 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,  in hwpipe_init()
640 			cursor_planes, hw_cfg->pipe_cursor.base,  in hwpipe_init()
641 			hw_cfg->pipe_cursor.caps);  in hwpipe_init()
650 	struct drm_device *dev = mdp5_kms->dev;  in hwmixer_init()
654 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);  in hwmixer_init()
656 	for (i = 0; i < hw_cfg->lm.count; i++) {  in hwmixer_init()
659 		mixer = mdp5_mixer_init(dev, &hw_cfg->lm.instances[i]);  in hwmixer_init()
662 			DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n",  in hwmixer_init()
667 		mixer->idx = mdp5_kms->num_hwmixers;  in hwmixer_init()
668 		mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer;  in hwmixer_init()
676 	struct drm_device *dev = mdp5_kms->dev;  in interface_init()
681 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);  in interface_init()
682 	intf_types = hw_cfg->intf.connect;  in interface_init()
684 	for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {  in interface_init()
690 		intf = devm_kzalloc(dev->dev, sizeof(*intf), GFP_KERNEL);  in interface_init()
692 			DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i);  in interface_init()
693 			return -ENOMEM;  in interface_init()
696 		intf->num = i;  in interface_init()
697 		intf->type = intf_types[i];  in interface_init()
698 		intf->mode = MDP5_INTF_MODE_NONE;  in interface_init()
699 		intf->idx = mdp5_kms->num_intfs;  in interface_init()
700 		mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf;  in interface_init()
708 	struct msm_drm_private *priv = dev->dev_private;  in mdp5_init()
709 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));  in mdp5_init()
714 	mdp5_kms->dev = dev;  in mdp5_init()
724 	clk_set_rate(mdp5_kms->core_clk, 200000000);  in mdp5_init()
726 	pm_runtime_enable(&pdev->dev);  in mdp5_init()
727 	mdp5_kms->rpm_enabled = true;  in mdp5_init()
731 	mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);  in mdp5_init()
732 	if (IS_ERR(mdp5_kms->cfg)) {  in mdp5_init()
733 		ret = PTR_ERR(mdp5_kms->cfg);  in mdp5_init()
734 		mdp5_kms->cfg = NULL;  in mdp5_init()
738 	config = mdp5_cfg_get_config(mdp5_kms->cfg);  in mdp5_init()
739 	mdp5_kms->caps = config->hw->mdp.caps;  in mdp5_init()
742 	clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);  in mdp5_init()
749 	if (mdp5_kms->caps & MDP_CAP_SMP) {  in mdp5_init()
750 		mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp);  in mdp5_init()
751 		if (IS_ERR(mdp5_kms->smp)) {  in mdp5_init()
752 			ret = PTR_ERR(mdp5_kms->smp);  in mdp5_init()
753 			mdp5_kms->smp = NULL;  in mdp5_init()
758 	mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);  in mdp5_init()
759 	if (IS_ERR(mdp5_kms->ctlm)) {  in mdp5_init()
760 		ret = PTR_ERR(mdp5_kms->ctlm);  in mdp5_init()
761 		mdp5_kms->ctlm = NULL;  in mdp5_init()
785 	struct icc_path *path0 = msm_icc_get(&pdev->dev, "mdp0-mem");  in mdp5_setup_interconnect()
786 	struct icc_path *path1 = msm_icc_get(&pdev->dev, "mdp1-mem");  in mdp5_setup_interconnect()
787 	struct icc_path *path_rot = msm_icc_get(&pdev->dev, "rotator-mem");  in mdp5_setup_interconnect()
799 		dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n");  in mdp5_setup_interconnect()
820 	if (!msm_disp_drv_should_bind(&pdev->dev, false))  in mdp5_dev_probe()
821 		return -ENODEV;  in mdp5_dev_probe()
823 	mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL);  in mdp5_dev_probe()
825 		return -ENOMEM;  in mdp5_dev_probe()
831 	mdp5_kms->pdev = pdev;  in mdp5_dev_probe()
833 	spin_lock_init(&mdp5_kms->resource_lock);  in mdp5_dev_probe()
835 	mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys");  in mdp5_dev_probe()
836 	if (IS_ERR(mdp5_kms->mmio))  in mdp5_dev_probe()
837 		return PTR_ERR(mdp5_kms->mmio);  in mdp5_dev_probe()
840 	ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true);  in mdp5_dev_probe()
843 	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true);  in mdp5_dev_probe()
846 	ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true);  in mdp5_dev_probe()
849 	ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true);  in mdp5_dev_probe()
854 	get_clk(pdev, &mdp5_kms->lut_clk, "lut", false);  in mdp5_dev_probe()
855 	get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false);  in mdp5_dev_probe()
856 	get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false);  in mdp5_dev_probe()
860 		return dev_err_probe(&pdev->dev, irq, "failed to get irq\n");  in mdp5_dev_probe()
862 	mdp5_kms->base.base.irq = irq;  in mdp5_dev_probe()
864 	return msm_drv_probe(&pdev->dev, mdp5_kms_init, &mdp5_kms->base.base);  in mdp5_dev_probe()
870 	component_master_del(&pdev->dev, &msm_drm_ops);  in mdp5_dev_remove()
877 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));  in mdp5_runtime_suspend()
888 	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));  in mdp5_runtime_resume()