Lines Matching +full:sc7180 +full:- +full:dp
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
13 #include <linux/dma-buf.h>
65 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
68 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
75 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
78 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
79 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, in _dpu_danger_signal_status()
83 if (kms->hw_mdp->ops.get_safe_status) in _dpu_danger_signal_status()
84 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, in _dpu_danger_signal_status()
87 pm_runtime_put_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
92 seq_printf(s, "SSPP%d : 0x%x \n", i - SSPP_VIG0, in _dpu_danger_signal_status()
114 struct dpu_kms *kms = file->private_data; in _dpu_plane_danger_read()
118 len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl); in _dpu_plane_danger_read()
127 drm_for_each_plane(plane, kms->dev) { in _dpu_plane_set_danger_state()
128 if (plane->fb && plane->state) { in _dpu_plane_set_danger_state()
131 plane->base.id, plane->fb->width, in _dpu_plane_set_danger_state()
132 plane->fb->height); in _dpu_plane_set_danger_state()
134 plane->state->src_x >> 16, in _dpu_plane_set_danger_state()
135 plane->state->src_y >> 16, in _dpu_plane_set_danger_state()
136 plane->state->src_w >> 16, in _dpu_plane_set_danger_state()
137 plane->state->src_h >> 16, in _dpu_plane_set_danger_state()
138 plane->state->crtc_x, plane->state->crtc_y, in _dpu_plane_set_danger_state()
139 plane->state->crtc_w, plane->state->crtc_h); in _dpu_plane_set_danger_state()
141 DPU_DEBUG("Inactive plane:%d\n", plane->base.id); in _dpu_plane_set_danger_state()
149 struct dpu_kms *kms = file->private_data; in _dpu_plane_danger_write()
161 kms->has_danger_ctrl = false; in _dpu_plane_danger_write()
165 kms->has_danger_ctrl = true; in _dpu_plane_danger_write()
203 struct dpu_debugfs_regset32 *regset = s->private; in dpu_regset32_show()
204 struct dpu_kms *dpu_kms = regset->dpu_kms; in dpu_regset32_show()
208 if (!dpu_kms->mmio) in dpu_regset32_show()
211 base = dpu_kms->mmio + regset->offset; in dpu_regset32_show()
214 if (regset->offset & 0xF) { in dpu_regset32_show()
215 seq_printf(s, "[%x]", regset->offset & ~0xF); in dpu_regset32_show()
216 for (i = 0; i < (regset->offset & 0xF); i += 4) in dpu_regset32_show()
220 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_regset32_show()
223 for (i = 0; i < regset->blk_len; i += 4) { in dpu_regset32_show()
224 addr = regset->offset + i; in dpu_regset32_show()
230 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_regset32_show()
237 * dpu_debugfs_create_regset32 - Create register read back file for debugfs
247 * @offset: sub-block offset
248 * @length: sub-block length, in bytes
260 regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL); in dpu_debugfs_create_regset32()
265 regset->offset = round_down(offset, 4); in dpu_debugfs_create_regset32()
266 regset->blk_len = length; in dpu_debugfs_create_regset32()
267 regset->dpu_kms = dpu_kms; in dpu_debugfs_create_regset32()
281 struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i); in dpu_debugfs_sspp_init()
297 return -EINVAL; in dpu_kms_debugfs_init()
300 if (minor->type != DRM_MINOR_PRIMARY) in dpu_kms_debugfs_init()
303 entry = debugfs_create_dir("debug", minor->debugfs_root); in dpu_kms_debugfs_init()
326 return to_dpu_global_state(dpu_kms->global_state.state); in dpu_kms_get_existing_global_state()
335 struct msm_drm_private *priv = s->dev->dev_private; in dpu_kms_get_global_state()
336 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_kms_get_global_state()
340 &dpu_kms->global_state); in dpu_kms_get_global_state()
352 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in dpu_kms_global_duplicate_state()
356 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); in dpu_kms_global_duplicate_state()
358 return &state->base; in dpu_kms_global_duplicate_state()
389 return -ENOMEM; in dpu_kms_global_obj_init()
391 drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, in dpu_kms_global_obj_init()
392 &state->base, in dpu_kms_global_obj_init()
395 state->rm = &dpu_kms->rm; in dpu_kms_global_obj_init()
402 drm_atomic_private_obj_fini(&dpu_kms->global_state); in dpu_kms_global_obj_fini()
409 struct device *dpu_dev = &dpu_kms->pdev->dev; in dpu_kms_parse_data_bus_icc_path()
411 path0 = msm_icc_get(dpu_dev, "mdp0-mem"); in dpu_kms_parse_data_bus_icc_path()
412 path1 = msm_icc_get(dpu_dev, "mdp1-mem"); in dpu_kms_parse_data_bus_icc_path()
417 dpu_kms->path[0] = path0; in dpu_kms_parse_data_bus_icc_path()
418 dpu_kms->num_paths = 1; in dpu_kms_parse_data_bus_icc_path()
421 dpu_kms->path[1] = path1; in dpu_kms_parse_data_bus_icc_path()
422 dpu_kms->num_paths++; in dpu_kms_parse_data_bus_icc_path()
440 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_kms_enable_commit()
446 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_disable_commit()
467 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) { in dpu_kms_flush_commit()
468 if (!crtc->state->active) in dpu_kms_flush_commit()
483 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) in dpu_kms_complete_commit()
496 if (!kms || !crtc || !crtc->state) { in dpu_kms_wait_for_commit_done()
501 dev = crtc->dev; in dpu_kms_wait_for_commit_done()
503 if (!crtc->state->enable) { in dpu_kms_wait_for_commit_done()
504 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id); in dpu_kms_wait_for_commit_done()
508 if (!drm_atomic_crtc_effectively_active(crtc->state)) { in dpu_kms_wait_for_commit_done()
509 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id); in dpu_kms_wait_for_commit_done()
513 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dpu_kms_wait_for_commit_done()
514 if (encoder->crtc != crtc) in dpu_kms_wait_for_commit_done()
517 * Wait for post-flush if necessary to delay before in dpu_kms_wait_for_commit_done()
519 * mode panels. This may be a no-op for command mode panels. in dpu_kms_wait_for_commit_done()
523 if (ret && ret != -EWOULDBLOCK) { in dpu_kms_wait_for_commit_done()
535 for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) in dpu_kms_wait_flush()
561 info->vsync_source = DPU_VSYNC_SOURCE_GPIO_0; in dpu_kms_dsi_set_te_source()
569 info->vsync_source = i; in dpu_kms_dsi_set_te_source()
574 return -EINVAL; in dpu_kms_dsi_set_te_source()
585 if (!(priv->dsi[0] || priv->dsi[1])) in _dpu_kms_initialize_dsi()
590 * - Single DSI host (dsi0 or dsi1) in _dpu_kms_initialize_dsi()
591 * - Two independent DSI hosts in _dpu_kms_initialize_dsi()
592 * - Bonded DSI0 and DSI1 hosts in _dpu_kms_initialize_dsi()
596 for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { in _dpu_kms_initialize_dsi()
599 if (!priv->dsi[i]) in _dpu_kms_initialize_dsi()
602 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && in _dpu_kms_initialize_dsi()
603 !msm_dsi_is_master_dsi(priv->dsi[i])) in _dpu_kms_initialize_dsi()
610 if (msm_dsi_is_bonded_dsi(priv->dsi[i])) in _dpu_kms_initialize_dsi()
613 info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); in _dpu_kms_initialize_dsi()
615 rc = dpu_kms_dsi_set_te_source(&info, priv->dsi[i]); in _dpu_kms_initialize_dsi()
627 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder); in _dpu_kms_initialize_dsi()
634 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) { in _dpu_kms_initialize_dsi()
635 rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder); in _dpu_kms_initialize_dsi()
657 for (i = 0; i < ARRAY_SIZE(priv->dp); i++) { in _dpu_kms_initialize_displayport()
658 if (!priv->dp[i]) in _dpu_kms_initialize_displayport()
672 yuv_supported = !!dpu_kms->catalog->cdm; in _dpu_kms_initialize_displayport()
673 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder, yuv_supported); in _dpu_kms_initialize_displayport()
675 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); in _dpu_kms_initialize_displayport()
691 if (!priv->hdmi) in _dpu_kms_initialize_hdmi()
705 rc = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); in _dpu_kms_initialize_hdmi()
707 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); in _dpu_kms_initialize_hdmi()
731 maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth; in _dpu_kms_initialize_writeback()
749 * _dpu_kms_setup_displays - create encoders, bridges and connectors
782 if (dpu_kms->catalog->wb_count) { in _dpu_kms_setup_displays()
783 for (i = 0; i < dpu_kms->catalog->wb_count; i++) { in _dpu_kms_setup_displays()
784 if (dpu_kms->catalog->wb[i].id == WB_2) { in _dpu_kms_setup_displays()
786 dpu_kms->catalog->wb[i].format_list, in _dpu_kms_setup_displays()
787 dpu_kms->catalog->wb[i].num_formats); in _dpu_kms_setup_displays()
814 dev = dpu_kms->dev; in _dpu_kms_drm_obj_init()
815 priv = dev->dev_private; in _dpu_kms_drm_obj_init()
816 catalog = dpu_kms->catalog; in _dpu_kms_drm_obj_init()
829 if (catalog->cwb_count > 0) in _dpu_kms_drm_obj_init()
830 encoder->possible_clones = dpu_encoder_get_clones(encoder); in _dpu_kms_drm_obj_init()
833 max_crtc_count = min(catalog->mixer_count, num_encoders); in _dpu_kms_drm_obj_init()
836 for (i = 0; i < catalog->sspp_count; i++) { in _dpu_kms_drm_obj_init()
839 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)) in _dpu_kms_drm_obj_init()
848 type, catalog->sspp[i].features, in _dpu_kms_drm_obj_init()
849 catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); in _dpu_kms_drm_obj_init()
852 plane = dpu_plane_init_virtual(dev, type, (1UL << max_crtc_count) - 1); in _dpu_kms_drm_obj_init()
854 plane = dpu_plane_init(dev, catalog->sspp[i].id, type, in _dpu_kms_drm_obj_init()
855 (1UL << max_crtc_count) - 1); in _dpu_kms_drm_obj_init()
877 priv->num_crtcs++; in _dpu_kms_drm_obj_init()
882 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; in _dpu_kms_drm_obj_init()
891 dpu_kms->hw_intr = NULL; in _dpu_kms_hw_destroy()
896 for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { in _dpu_kms_hw_destroy()
897 dpu_kms->hw_vbif[i] = NULL; in _dpu_kms_hw_destroy()
902 dpu_kms->catalog = NULL; in _dpu_kms_hw_destroy()
904 dpu_kms->hw_mdp = NULL; in _dpu_kms_hw_destroy()
920 msm_kms_destroy(&dpu_kms->base); in dpu_kms_destroy()
922 if (dpu_kms->rpm_enabled) in dpu_kms_destroy()
923 pm_runtime_disable(&dpu_kms->pdev->dev); in dpu_kms_destroy()
931 if (!dpu_kms || !dpu_kms->dev) in dpu_irq_postinstall()
932 return -EINVAL; in dpu_irq_postinstall()
934 priv = dpu_kms->dev->dev_private; in dpu_irq_postinstall()
936 return -EINVAL; in dpu_irq_postinstall()
950 cat = dpu_kms->catalog; in dpu_kms_mdp_snapshot()
952 pm_runtime_get_sync(&dpu_kms->pdev->dev); in dpu_kms_mdp_snapshot()
954 /* dump CTL sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
955 for (i = 0; i < cat->ctl_count; i++) in dpu_kms_mdp_snapshot()
956 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, in dpu_kms_mdp_snapshot()
957 dpu_kms->mmio + cat->ctl[i].base, "%s", in dpu_kms_mdp_snapshot()
958 cat->ctl[i].name); in dpu_kms_mdp_snapshot()
960 /* dump DSPP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
961 for (i = 0; i < cat->dspp_count; i++) { in dpu_kms_mdp_snapshot()
962 base = dpu_kms->mmio + cat->dspp[i].base; in dpu_kms_mdp_snapshot()
963 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, base, in dpu_kms_mdp_snapshot()
964 "%s", cat->dspp[i].name); in dpu_kms_mdp_snapshot()
966 if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0) in dpu_kms_mdp_snapshot()
967 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len, in dpu_kms_mdp_snapshot()
968 base + cat->dspp[i].sblk->pcc.base, "%s_%s", in dpu_kms_mdp_snapshot()
969 cat->dspp[i].name, in dpu_kms_mdp_snapshot()
970 cat->dspp[i].sblk->pcc.name); in dpu_kms_mdp_snapshot()
973 /* dump INTF sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
974 for (i = 0; i < cat->intf_count; i++) in dpu_kms_mdp_snapshot()
975 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, in dpu_kms_mdp_snapshot()
976 dpu_kms->mmio + cat->intf[i].base, "%s", in dpu_kms_mdp_snapshot()
977 cat->intf[i].name); in dpu_kms_mdp_snapshot()
979 /* dump PP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
980 for (i = 0; i < cat->pingpong_count; i++) { in dpu_kms_mdp_snapshot()
981 base = dpu_kms->mmio + cat->pingpong[i].base; in dpu_kms_mdp_snapshot()
982 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, base, in dpu_kms_mdp_snapshot()
983 "%s", cat->pingpong[i].name); in dpu_kms_mdp_snapshot()
985 /* TE2 sub-block has length of 0, so will not print it */ in dpu_kms_mdp_snapshot()
987 if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0) in dpu_kms_mdp_snapshot()
988 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len, in dpu_kms_mdp_snapshot()
989 base + cat->pingpong[i].sblk->dither.base, in dpu_kms_mdp_snapshot()
990 "%s_%s", cat->pingpong[i].name, in dpu_kms_mdp_snapshot()
991 cat->pingpong[i].sblk->dither.name); in dpu_kms_mdp_snapshot()
994 /* dump SSPP sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
995 for (i = 0; i < cat->sspp_count; i++) { in dpu_kms_mdp_snapshot()
996 base = dpu_kms->mmio + cat->sspp[i].base; in dpu_kms_mdp_snapshot()
997 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, base, in dpu_kms_mdp_snapshot()
998 "%s", cat->sspp[i].name); in dpu_kms_mdp_snapshot()
1000 if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0) in dpu_kms_mdp_snapshot()
1001 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len, in dpu_kms_mdp_snapshot()
1002 base + cat->sspp[i].sblk->scaler_blk.base, in dpu_kms_mdp_snapshot()
1003 "%s_%s", cat->sspp[i].name, in dpu_kms_mdp_snapshot()
1004 cat->sspp[i].sblk->scaler_blk.name); in dpu_kms_mdp_snapshot()
1006 if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0) in dpu_kms_mdp_snapshot()
1007 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len, in dpu_kms_mdp_snapshot()
1008 base + cat->sspp[i].sblk->csc_blk.base, in dpu_kms_mdp_snapshot()
1009 "%s_%s", cat->sspp[i].name, in dpu_kms_mdp_snapshot()
1010 cat->sspp[i].sblk->csc_blk.name); in dpu_kms_mdp_snapshot()
1013 /* dump LM sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
1014 for (i = 0; i < cat->mixer_count; i++) in dpu_kms_mdp_snapshot()
1015 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, in dpu_kms_mdp_snapshot()
1016 dpu_kms->mmio + cat->mixer[i].base, in dpu_kms_mdp_snapshot()
1017 "%s", cat->mixer[i].name); in dpu_kms_mdp_snapshot()
1019 /* dump WB sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
1020 for (i = 0; i < cat->wb_count; i++) in dpu_kms_mdp_snapshot()
1021 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, in dpu_kms_mdp_snapshot()
1022 dpu_kms->mmio + cat->wb[i].base, "%s", in dpu_kms_mdp_snapshot()
1023 cat->wb[i].name); in dpu_kms_mdp_snapshot()
1025 if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { in dpu_kms_mdp_snapshot()
1027 dpu_kms->mmio + cat->mdp[0].base, "top"); in dpu_kms_mdp_snapshot()
1028 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END, in dpu_kms_mdp_snapshot()
1029 dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2"); in dpu_kms_mdp_snapshot()
1031 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, in dpu_kms_mdp_snapshot()
1032 dpu_kms->mmio + cat->mdp[0].base, "top"); in dpu_kms_mdp_snapshot()
1035 /* dump CWB sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
1036 for (i = 0; i < cat->cwb_count; i++) in dpu_kms_mdp_snapshot()
1037 msm_disp_snapshot_add_block(disp_state, cat->cwb[i].len, in dpu_kms_mdp_snapshot()
1038 dpu_kms->mmio + cat->cwb[i].base, cat->cwb[i].name); in dpu_kms_mdp_snapshot()
1040 /* dump DSC sub-blocks HW regs info */ in dpu_kms_mdp_snapshot()
1041 for (i = 0; i < cat->dsc_count; i++) { in dpu_kms_mdp_snapshot()
1042 base = dpu_kms->mmio + cat->dsc[i].base; in dpu_kms_mdp_snapshot()
1043 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, in dpu_kms_mdp_snapshot()
1044 "%s", cat->dsc[i].name); in dpu_kms_mdp_snapshot()
1046 if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) { in dpu_kms_mdp_snapshot()
1047 struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc; in dpu_kms_mdp_snapshot()
1048 struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl; in dpu_kms_mdp_snapshot()
1051 cat->dsc[i].name, enc.name); in dpu_kms_mdp_snapshot()
1053 cat->dsc[i].name, ctl.name); in dpu_kms_mdp_snapshot()
1057 if (cat->cdm) in dpu_kms_mdp_snapshot()
1058 msm_disp_snapshot_add_block(disp_state, cat->cdm->len, in dpu_kms_mdp_snapshot()
1059 dpu_kms->mmio + cat->cdm->base, in dpu_kms_mdp_snapshot()
1060 "%s", cat->cdm->name); in dpu_kms_mdp_snapshot()
1062 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { in dpu_kms_mdp_snapshot()
1063 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; in dpu_kms_mdp_snapshot()
1065 msm_disp_snapshot_add_block(disp_state, vbif->len, in dpu_kms_mdp_snapshot()
1066 dpu_kms->vbif[vbif->id] + vbif->base, in dpu_kms_mdp_snapshot()
1067 "%s", vbif->name); in dpu_kms_mdp_snapshot()
1070 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_mdp_snapshot()
1098 if (!dpu_kms->base.aspace) in _dpu_kms_mmu_destroy()
1101 mmu = dpu_kms->base.aspace->mmu; in _dpu_kms_mmu_destroy()
1103 mmu->funcs->detach(mmu); in _dpu_kms_mmu_destroy()
1104 msm_gem_address_space_put(dpu_kms->base.aspace); in _dpu_kms_mmu_destroy()
1106 dpu_kms->base.aspace = NULL; in _dpu_kms_mmu_destroy()
1113 aspace = msm_kms_init_aspace(dpu_kms->dev); in _dpu_kms_mmu_init()
1117 dpu_kms->base.aspace = aspace; in _dpu_kms_mmu_init()
1123 * dpu_kms_get_clk_rate() - get the clock rate
1133 clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name); in dpu_kms_get_clk_rate()
1146 int i, rc = -EINVAL; in dpu_kms_hw_init()
1156 dev = dpu_kms->dev; in dpu_kms_hw_init()
1158 dev->mode_config.cursor_width = 512; in dpu_kms_hw_init()
1159 dev->mode_config.cursor_height = 512; in dpu_kms_hw_init()
1165 atomic_set(&dpu_kms->bandwidth_ref, 0); in dpu_kms_hw_init()
1167 rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1171 core_rev = readl_relaxed(dpu_kms->mmio + 0x0); in dpu_kms_hw_init()
1175 dpu_kms->catalog = of_device_get_match_data(dev->dev); in dpu_kms_hw_init()
1176 if (!dpu_kms->catalog) { in dpu_kms_hw_init()
1178 rc = -EINVAL; in dpu_kms_hw_init()
1192 dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent); in dpu_kms_hw_init()
1193 if (IS_ERR(dpu_kms->mdss)) { in dpu_kms_hw_init()
1194 rc = PTR_ERR(dpu_kms->mdss); in dpu_kms_hw_init()
1199 if (!dpu_kms->mdss) { in dpu_kms_hw_init()
1200 rc = -EINVAL; in dpu_kms_hw_init()
1205 rc = dpu_rm_init(dev, &dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio); in dpu_kms_hw_init()
1211 dpu_kms->hw_mdp = dpu_hw_mdptop_init(dev, in dpu_kms_hw_init()
1212 dpu_kms->catalog->mdp, in dpu_kms_hw_init()
1213 dpu_kms->mmio, in dpu_kms_hw_init()
1214 dpu_kms->catalog->mdss_ver); in dpu_kms_hw_init()
1215 if (IS_ERR(dpu_kms->hw_mdp)) { in dpu_kms_hw_init()
1216 rc = PTR_ERR(dpu_kms->hw_mdp); in dpu_kms_hw_init()
1218 dpu_kms->hw_mdp = NULL; in dpu_kms_hw_init()
1222 for (i = 0; i < dpu_kms->catalog->vbif_count; i++) { in dpu_kms_hw_init()
1224 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i]; in dpu_kms_hw_init()
1226 hw = dpu_hw_vbif_init(dev, vbif, dpu_kms->vbif[vbif->id]); in dpu_kms_hw_init()
1229 DPU_ERROR("failed to init vbif %d: %d\n", vbif->id, rc); in dpu_kms_hw_init()
1233 dpu_kms->hw_vbif[vbif->id] = hw; in dpu_kms_hw_init()
1243 rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate); in dpu_kms_hw_init()
1250 * We need to program DP <-> PHY relationship only for SC8180X since it in dpu_kms_hw_init()
1251 * has fewer DP controllers than DP PHYs. in dpu_kms_hw_init()
1253 * the INTF <->DP relationship isn't static anymore, this needs to be in dpu_kms_hw_init()
1256 if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,sc8180x-dpu")) in dpu_kms_hw_init()
1257 dpu_kms->hw_mdp->ops.dp_phy_intf_sel(dpu_kms->hw_mdp, (unsigned int[]){ 1, 2, }); in dpu_kms_hw_init()
1259 dpu_kms->hw_intr = dpu_hw_intr_init(dev, dpu_kms->mmio, dpu_kms->catalog); in dpu_kms_hw_init()
1260 if (IS_ERR(dpu_kms->hw_intr)) { in dpu_kms_hw_init()
1261 rc = PTR_ERR(dpu_kms->hw_intr); in dpu_kms_hw_init()
1263 dpu_kms->hw_intr = NULL; in dpu_kms_hw_init()
1267 dev->mode_config.min_width = 0; in dpu_kms_hw_init()
1268 dev->mode_config.min_height = 0; in dpu_kms_hw_init()
1270 dev->mode_config.max_width = DPU_MAX_IMG_WIDTH; in dpu_kms_hw_init()
1271 dev->mode_config.max_height = DPU_MAX_IMG_HEIGHT; in dpu_kms_hw_init()
1273 dev->max_vblank_count = 0xffffffff; in dpu_kms_hw_init()
1274 /* Disable vblank irqs aggressively for power-saving */ in dpu_kms_hw_init()
1275 dev->vblank_disable_immediate = true; in dpu_kms_hw_init()
1289 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1294 pm_runtime_put_sync(&dpu_kms->pdev->dev); in dpu_kms_hw_init()
1303 struct msm_drm_private *priv = ddev->dev_private; in dpu_kms_init()
1304 struct device *dev = ddev->dev; in dpu_kms_init()
1306 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_kms_init()
1317 ret = msm_kms_init(&dpu_kms->base, &kms_funcs); in dpu_kms_init()
1322 dpu_kms->dev = ddev; in dpu_kms_init()
1324 pm_runtime_enable(&pdev->dev); in dpu_kms_init()
1325 dpu_kms->rpm_enabled = true; in dpu_kms_init()
1332 struct platform_device *pdev = dpu_kms->pdev; in dpu_kms_mmap_mdp5()
1336 if (!dev_is_platform(dpu_kms->pdev->dev.parent)) in dpu_kms_mmap_mdp5()
1337 return -EINVAL; in dpu_kms_mmap_mdp5()
1339 mdss_dev = to_platform_device(dpu_kms->pdev->dev.parent); in dpu_kms_mmap_mdp5()
1341 dpu_kms->mmio = msm_ioremap(pdev, "mdp_phys"); in dpu_kms_mmap_mdp5()
1342 if (IS_ERR(dpu_kms->mmio)) { in dpu_kms_mmap_mdp5()
1343 ret = PTR_ERR(dpu_kms->mmio); in dpu_kms_mmap_mdp5()
1345 dpu_kms->mmio = NULL; in dpu_kms_mmap_mdp5()
1348 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); in dpu_kms_mmap_mdp5()
1350 dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev, in dpu_kms_mmap_mdp5()
1351 dpu_kms->pdev, in dpu_kms_mmap_mdp5()
1353 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { in dpu_kms_mmap_mdp5()
1354 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); in dpu_kms_mmap_mdp5()
1356 dpu_kms->vbif[VBIF_RT] = NULL; in dpu_kms_mmap_mdp5()
1360 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_mdss(mdss_dev, in dpu_kms_mmap_mdp5()
1361 dpu_kms->pdev, in dpu_kms_mmap_mdp5()
1363 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { in dpu_kms_mmap_mdp5()
1364 dpu_kms->vbif[VBIF_NRT] = NULL; in dpu_kms_mmap_mdp5()
1373 struct platform_device *pdev = dpu_kms->pdev; in dpu_kms_mmap_dpu()
1376 dpu_kms->mmio = msm_ioremap(pdev, "mdp"); in dpu_kms_mmap_dpu()
1377 if (IS_ERR(dpu_kms->mmio)) { in dpu_kms_mmap_dpu()
1378 ret = PTR_ERR(dpu_kms->mmio); in dpu_kms_mmap_dpu()
1380 dpu_kms->mmio = NULL; in dpu_kms_mmap_dpu()
1383 DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); in dpu_kms_mmap_dpu()
1385 dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif"); in dpu_kms_mmap_dpu()
1386 if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { in dpu_kms_mmap_dpu()
1387 ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); in dpu_kms_mmap_dpu()
1389 dpu_kms->vbif[VBIF_RT] = NULL; in dpu_kms_mmap_dpu()
1393 dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt"); in dpu_kms_mmap_dpu()
1394 if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { in dpu_kms_mmap_dpu()
1395 dpu_kms->vbif[VBIF_NRT] = NULL; in dpu_kms_mmap_dpu()
1404 struct device *dev = &pdev->dev; in dpu_dev_probe()
1409 if (!msm_disp_drv_should_bind(&pdev->dev, true)) in dpu_dev_probe()
1410 return -ENODEV; in dpu_dev_probe()
1414 return -ENOMEM; in dpu_dev_probe()
1416 dpu_kms->pdev = pdev; in dpu_dev_probe()
1423 if (ret && ret != -ENODEV) in dpu_dev_probe()
1426 ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks); in dpu_dev_probe()
1430 dpu_kms->num_clocks = ret; in dpu_dev_probe()
1436 dpu_kms->base.irq = irq; in dpu_dev_probe()
1438 if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,mdp5")) in dpu_dev_probe()
1449 return msm_drv_probe(&pdev->dev, dpu_kms_init, &dpu_kms->base); in dpu_dev_probe()
1454 component_master_del(&pdev->dev, &msm_drm_ops); in dpu_dev_remove()
1462 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_runtime_suspend()
1466 clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks); in dpu_runtime_suspend()
1468 for (i = 0; i < dpu_kms->num_paths; i++) in dpu_runtime_suspend()
1469 icc_set_bw(dpu_kms->path[i], 0, 0); in dpu_runtime_suspend()
1476 int rc = -1; in dpu_runtime_resume()
1479 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); in dpu_runtime_resume()
1483 ddev = dpu_kms->dev; in dpu_runtime_resume()
1485 rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks); in dpu_runtime_resume()
1508 { .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
1509 { .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
1510 { .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
1511 { .compatible = "qcom,msm8996-mdp5", .data = &dpu_msm8996_cfg, },
1512 { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
1513 { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
1514 { .compatible = "qcom,sa8775p-dpu", .data = &dpu_sa8775p_cfg, },
1515 { .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, },
1516 { .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, },
1517 { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
1518 { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
1519 { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
1520 { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
1521 { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
1522 { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
1523 { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
1524 { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
1525 { .compatible = "qcom,sm6150-dpu", .data = &dpu_sm6150_cfg, },
1526 { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
1527 { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
1528 { .compatible = "qcom,sm7150-dpu", .data = &dpu_sm7150_cfg, },
1529 { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
1530 { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
1531 { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
1532 { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
1533 { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
1534 { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
1535 { .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },