176 	u32 opmode;  in _sspp_setup_opmode()  local
182 	opmode = DPU_REG_READ(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE);  in _sspp_setup_opmode()
185 		opmode |= mask;  in _sspp_setup_opmode()
187 		opmode &= ~mask;  in _sspp_setup_opmode()
189 	DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);  in _sspp_setup_opmode()
196 	u32 opmode;  in _sspp_setup_csc10_opmode()  local
198 	opmode = DPU_REG_READ(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE);  in _sspp_setup_csc10_opmode()
200 		opmode |= mask;  in _sspp_setup_csc10_opmode()
202 		opmode &= ~mask;  in _sspp_setup_csc10_opmode()
204 	DPU_REG_WRITE(&ctx->hw, sblk->csc_blk.base + SSPP_VIG_CSC_10_OP_MODE, opmode);  in _sspp_setup_csc10_opmode()
216 	u32 opmode = 0;  in dpu_hw_sspp_setup_format()  local
235 	opmode = DPU_REG_READ(c, op_mode_off);  in dpu_hw_sspp_setup_format()
236 	opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |  in dpu_hw_sspp_setup_format()
240 		opmode |= MDSS_MDP_OP_FLIP_LR;  in dpu_hw_sspp_setup_format()
242 		opmode |= MDSS_MDP_OP_FLIP_UD;  in dpu_hw_sspp_setup_format()
274 			opmode |= MDSS_MDP_OP_BWC_EN;  in dpu_hw_sspp_setup_format()
305 	opmode |= MDSS_MDP_OP_PE_OVERRIDE;  in dpu_hw_sspp_setup_format()
314 	/* update scaler opmode, if appropriate */  in dpu_hw_sspp_setup_format()
325 	DPU_REG_WRITE(c, op_mode_off, opmode);  in dpu_hw_sspp_setup_format()