Lines Matching +full:ssc +full:- +full:block +full:- +full:bus
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
232 * [0-7] @ 0x2000 gen2,gen3
233 * [8-15] @ 0x3000 945,g33,pnv
235 * [0-15] @ 0x3000 gen4,gen5
237 * [0-15] @ 0x100000 gen6,vlv,chv
238 * [0-31] @ 0x100000 gen7+
243 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
251 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
280 #define PRB0_BASE (0x2030 - 0x30)
281 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
282 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
283 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
284 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
285 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
286 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
351 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
352 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
465 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
541 /* Block grant count for isoch requests when block count is
561 /* Enables non-sequential data reads through arbiter
570 /* Arbiter time slice for non-isoch streams */
598 * interrupt. The second control is for the functional block generating the
604 * These defines should cover us well from SNB->HSW with minor exceptions
643 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
769 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
770 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)…
779 /* i830, required in DVO non-gang */
791 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
829 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
831 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
836 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
894 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
895 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
896 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
897 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
898 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
899 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
900 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
901 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
902 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
903 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
904 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
905 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
911 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
912 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1013 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
1296 * Programmed value is multiplier - 1, up to 5x.
1344 * of the infoframe structure specified by CEA-861. */
1410 /* Link training mode - select a suitable mode for each stage */
1434 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1445 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
1498 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1500 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
1516 * Attributes and VB-ID.
1535 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
1538 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
1539 …CONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
1543 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
1546 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
1557 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
1573 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
1574 … TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
1575 …RANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
1576 …RANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
1578 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
1611 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
1634 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
1661 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
1663 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
1828 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
1829 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
1830 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
1831 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
1832 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
1902 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
1918 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-lin…
1930 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
2206 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
2215 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
2216 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
2386 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
2439 #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
2440 #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
2441 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
2653 /* south display engine interrupt: CPT - CNP */
2740 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
2741 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
2742 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
2743 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
2744 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
2751 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
2752 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
2753 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
2754 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
2755 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
2762 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
2763 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
2764 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
2765 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
2766 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
2939 /* Per-transcoder DIP controls (PCH) */
2955 /* Per-transcoder DIP controls (VLV) */
3056 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
3079 …CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
3096 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3097 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3131 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
3170 /* SNB A-stepping */
3175 /* SNB B-stepping */
3232 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
3306 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
3309 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
3335 /* These are the 4 32-bit write offset registers for each stream
3342 * HSW - ICL power wells
3346 * - main (HSW_PWR_WELL_CTL[1-4])
3347 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
3348 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
3351 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
3352 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
3353 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
3354 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
3379 /* ICL/TGL - power wells */
3386 /* XE_LPD - power wells */
3438 /* HSW - power well misc debug registers */
3458 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
3461 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
3464 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
3467 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
3468 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
3470 /* Per-pipe DDI Function Control */
3523 #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
3612 ((width) == 3 ? 4 : (width) - 1))
3691 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
3708 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
3709 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
3867 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
3876 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
3901 (tc_port) - TC_PORT_4 + 21))
3984 /* ADL-P Type C PLL */
4074 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
4118 /* Pipe WM_LINETIME - watermark line time */