Lines Matching +full:0 +full:x1d0000
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
119 #define GU_CNTL_PROTECTED _MMIO(0x10100C)
122 #define GU_CNTL _MMIO(0x101010)
125 #define GU_DEBUG _MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
130 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
132 #define GEN6_STOLEN_RESERVED_1M (0 << 4)
137 #define GEN7_STOLEN_RESERVED_1M (0 << 5)
140 #define GEN8_STOLEN_RESERVED_1M (0 << 7)
144 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
147 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
148 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
154 #define DEBUG_RESET_I830 _MMIO(0x6070)
162 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
168 #define IOSF_SB_BUSY (1 << 0)
169 #define IOSF_PORT_BUNIT 0x03
170 #define IOSF_PORT_PUNIT 0x04
171 #define IOSF_PORT_NC 0x11
172 #define IOSF_PORT_DPIO 0x12
173 #define IOSF_PORT_GPIO_NC 0x13
174 #define IOSF_PORT_CCK 0x14
175 #define IOSF_PORT_DPIO_2 0x1a
176 #define IOSF_PORT_FLISDSI 0x1b
177 #define IOSF_PORT_GPIO_SC 0x48
178 #define IOSF_PORT_GPIO_SUS 0xa8
179 #define IOSF_PORT_CCU 0xa9
180 #define CHV_IOSF_PORT_GPIO_N 0x13
181 #define CHV_IOSF_PORT_GPIO_SE 0x48
182 #define CHV_IOSF_PORT_GPIO_E 0xa8
183 #define CHV_IOSF_PORT_GPIO_SW 0xb2
184 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
185 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
188 #define DPIO_DEVFN 0
190 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
194 #define DPIO_CMNRST (1 << 0)
196 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
199 #define _BXT_PHY_CTL_DDI_A 0x64C00
200 #define _BXT_PHY_CTL_DDI_B 0x64C10
201 #define _BXT_PHY_CTL_DDI_C 0x64C20
208 #define _PHY_CTL_FAMILY_DDI 0x64C90
209 #define _PHY_CTL_FAMILY_EDP 0x64C80
210 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0
218 #define UAIMI_SPR1 _MMIO(0x4F074)
220 #define SKL_VCCIO_MASK 0x1
222 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
232 * [0-7] @ 0x2000 gen2,gen3
233 * [8-15] @ 0x3000 945,g33,pnv
235 * [0-15] @ 0x3000 gen4,gen5
237 * [0-15] @ 0x100000 gen6,vlv,chv
238 * [0-31] @ 0x100000 gen7+
240 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
241 #define I830_FENCE_START_MASK 0x07f80000
245 #define I830_FENCE_REG_VALID (1 << 0)
250 #define I915_FENCE_START_MASK 0x0ff00000
253 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
254 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
257 #define I965_FENCE_REG_VALID (1 << 0)
258 #define I965_FENCE_MAX_PITCH_VAL 0x0400
260 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
261 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
263 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800
267 #define TILECTL _MMIO(0x101000)
268 #define TILECTL_SWZCTL (1 << 0)
276 #define PGTBL_CTL _MMIO(0x02020)
277 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
278 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
279 #define PGTBL_ER _MMIO(0x02024)
280 #define PRB0_BASE (0x2030 - 0x30)
281 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
282 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
283 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
284 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
285 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
286 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
287 #define RENDER_RING_BASE 0x02000
288 #define BSD_RING_BASE 0x04000
289 #define GEN6_BSD_RING_BASE 0x12000
290 #define GEN8_BSD2_RING_BASE 0x1c000
291 #define GEN11_BSD_RING_BASE 0x1c0000
292 #define GEN11_BSD2_RING_BASE 0x1c4000
293 #define GEN11_BSD3_RING_BASE 0x1d0000
294 #define GEN11_BSD4_RING_BASE 0x1d4000
295 #define XEHP_BSD5_RING_BASE 0x1e0000
296 #define XEHP_BSD6_RING_BASE 0x1e4000
297 #define XEHP_BSD7_RING_BASE 0x1f0000
298 #define XEHP_BSD8_RING_BASE 0x1f4000
299 #define VEBOX_RING_BASE 0x1a000
300 #define GEN11_VEBOX_RING_BASE 0x1c8000
301 #define GEN11_VEBOX2_RING_BASE 0x1d8000
302 #define XEHP_VEBOX3_RING_BASE 0x1e8000
303 #define XEHP_VEBOX4_RING_BASE 0x1f8000
304 #define MTL_GSC_RING_BASE 0x11a000
305 #define GEN12_COMPUTE0_RING_BASE 0x1a000
306 #define GEN12_COMPUTE1_RING_BASE 0x1c000
307 #define GEN12_COMPUTE2_RING_BASE 0x1e000
308 #define GEN12_COMPUTE3_RING_BASE 0x26000
309 #define BLT_RING_BASE 0x22000
310 #define XEHPC_BCS1_RING_BASE 0x3e0000
311 #define XEHPC_BCS2_RING_BASE 0x3e2000
312 #define XEHPC_BCS3_RING_BASE 0x3e4000
313 #define XEHPC_BCS4_RING_BASE 0x3e6000
314 #define XEHPC_BCS5_RING_BASE 0x3e8000
315 #define XEHPC_BCS6_RING_BASE 0x3ea000
316 #define XEHPC_BCS7_RING_BASE 0x3ec000
317 #define XEHPC_BCS8_RING_BASE 0x3ee000
318 #define DG1_GSC_HECI1_BASE 0x00258000
319 #define DG1_GSC_HECI2_BASE 0x00259000
320 #define DG2_GSC_HECI1_BASE 0x00373000
321 #define DG2_GSC_HECI2_BASE 0x00374000
322 #define MTL_GSC_HECI1_BASE 0x00116000
323 #define MTL_GSC_HECI2_BASE 0x00117000
325 #define HECI_H_CSR(base) _MMIO((base) + 0x4)
326 #define HECI_H_CSR_IE REG_BIT(0)
332 #define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
333 #define HECI_H_GS1_ER_PREP REG_BIT(0)
339 #define HECI_FWSTS1 0xc40
340 #define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
341 #define HECI1_FWSTS1_CURRENT_STATE_RESET 0
344 #define HECI_FWSTS2 0xc48
345 #define HECI_FWSTS3 0xc60
346 #define HECI_FWSTS4 0xc64
347 #define HECI_FWSTS5 0xc68
349 #define HECI_FWSTS6 0xc6c
351 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
360 #define HSW_GTT_CACHE_EN _MMIO(0x4024)
361 #define GTT_CACHE_EN_ALL 0xF0007FFF
362 #define GEN7_WR_WATERMARK _MMIO(0x4028)
363 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
364 #define ARB_MODE _MMIO(0x4030)
367 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
368 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
370 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
372 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
373 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
375 #define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */
383 #define GTT_FAULT_PRIMARY_A_FAULT (1 << 0)
385 #define GEN7_ERR_INT _MMIO(0x44040)
405 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
408 #define FPGA_DBG _MMIO(0x42300)
411 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
414 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
416 #define DERRMR _MMIO(0x44050)
418 #define DERRMR_PIPEA_SCANLINE (1 << 0)
435 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
436 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
437 #define SCPD0 _MMIO(0x209c) /* 915+ only */
440 #define GEN2_IER _MMIO(0x20a0)
441 #define GEN2_IIR _MMIO(0x20a4)
442 #define GEN2_IMR _MMIO(0x20a8)
443 #define GEN2_ISR _MMIO(0x20ac)
449 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
452 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
453 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
454 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
455 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
456 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
457 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
458 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
466 #define EIR _MMIO(0x20b0)
467 #define EMR _MMIO(0x20b4)
468 #define ESR _MMIO(0x20b8)
474 #define I915_ERROR_INSTRUCTION (1 << 0)
478 #define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)
479 #define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)
480 #define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)
484 #define VLV_ERROR_CLAIM (1 << 0)
488 #define INSTPM _MMIO(0x20c0)
496 #define MEM_MODE _MMIO(0x20cc)
500 #define FW_BLC _MMIO(0x20d8)
501 #define FW_BLC2 _MMIO(0x20dc)
502 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
506 #define MM_BURST_LENGTH 0x00700000
507 #define MM_FIFO_WATERMARK 0x0001F000
508 #define LM_BURST_LENGTH 0x00000700
509 #define LM_FIFO_WATERMARK 0x0000001F
510 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
512 #define _MBUS_ABOX0_CTL 0x45038
513 #define _MBUS_ABOX1_CTL 0x45048
514 #define _MBUS_ABOX2_CTL 0x4504C
522 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
524 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
526 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
527 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
545 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
572 #define MI_ARB_TIME_SLICE_1 (0 << 5)
582 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
589 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
590 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
592 #define MI_STATE _MMIO(0x20e4) /* gen2 only */
594 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
620 #define GT_RENDER_USER_INTERRUPT (1 << 0)
627 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
665 #define I915_ASLE_INTERRUPT (1 << 0)
668 #define GEN6_BSD_RNCID _MMIO(0x12198)
670 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
671 #define GEN7_FF_SCHED_MASK 0x0077070
674 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
675 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
676 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
677 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
679 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
680 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
681 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
682 #define GEN7_FF_VS_SCHED_HW (0x0 << 12)
683 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
684 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
685 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
686 #define GEN7_FF_DS_SCHED_HW (0x0 << 4)
688 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
693 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
698 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
703 #define IPS_CTL _MMIO(0x43408)
710 #define _DPLL_A 0x6014
711 #define _DPLL_B 0x6018
712 #define _CHV_DPLL_C 0x6030
716 #define VGA0 _MMIO(0x6000)
717 #define VGA1 _MMIO(0x6004)
718 #define VGA_PD _MMIO(0x6010)
721 #define VGA0_PD_P1_SHIFT 0
722 #define VGA0_PD_P1_MASK (0x1f << 0)
726 #define VGA1_PD_P1_MASK (0x1f << 8)
737 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
739 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
741 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
742 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
743 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
748 #define DPLL_PORTC_READY_MASK (0xf << 4)
749 #define DPLL_PORTB_READY_MASK (0xf)
751 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
754 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
755 #define DPLL_PORTD_READY_MASK (0xf)
756 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
758 #define PHY_LDO_DELAY_0NS 0x0
759 #define PHY_LDO_DELAY_200NS 0x1
760 #define PHY_LDO_DELAY_600NS 0x2
763 #define PHY_CH_SU_PSR 0x1
764 #define PHY_CH_DEEP_PSR 0x7
767 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
776 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
782 #define PLL_REF_INPUT_DREFCLK (0 << 13)
792 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
793 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
801 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
806 #define SDVO_MULTIPLIER_MASK 0x000000ff
808 #define SDVO_MULTIPLIER_SHIFT_VGA 0
810 #define _DPLL_A_MD 0x601c
811 #define _DPLL_B_MD 0x6020
812 #define _CHV_DPLL_C_MD 0x603c
821 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
824 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
843 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
850 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
851 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
853 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
855 #define _FPA0 0x6040
856 #define _FPA1 0x6044
857 #define _FPB0 0x6048
858 #define _FPB1 0x604c
861 #define FP_N_DIV_MASK 0x003f0000
862 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
864 #define FP_M1_DIV_MASK 0x00003f00
866 #define FP_M2_DIV_MASK 0x0000003f
867 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
868 #define FP_M2_DIV_SHIFT 0
869 #define DPLL_TEST _MMIO(0x606c)
870 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
879 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
880 #define D_STATE _MMIO(0x6104)
884 #define DSTATE_DOT_CLOCK_GATING (1 << 0)
885 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
922 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
923 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
925 #define RENCLK_GATE_D1 _MMIO(0x6204)
941 # define SV_CLOCK_GATE_DISABLE (1 << 0)
958 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
987 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
989 #define RENCLK_GATE_D2 _MMIO(0x6208)
994 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
997 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
998 #define DEUC _MMIO(0x6214) /* CRL only */
1000 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
1003 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
1005 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
1007 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1008 #define CZCLK_FREQ_MASK 0xf
1010 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
1017 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
1019 #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
1021 #define BXT_RP_STATE_CAP _MMIO(0x138170)
1022 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
1024 #define MTL_RP_STATE_CAP _MMIO(0x138000)
1025 #define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
1026 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
1029 #define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
1030 #define MTL_MPE_FREQUENCY _MMIO(0x13802c)
1031 #define MTL_RPE_MASK REG_GENMASK(8, 0)
1033 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
1034 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3
1035 #define PROCHOT_MASK REG_BIT(0)
1044 #define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1046 #define CHV_CLK_CTL1 _MMIO(0x101100)
1047 #define VLV_CLK_CTL2 _MMIO(0x101104)
1054 #define OVADD _MMIO(0x30000)
1055 #define DOVSTA _MMIO(0x30008)
1056 #define OC_BUF (0x3 << 20)
1057 #define OGAMC5 _MMIO(0x30010)
1058 #define OGAMC4 _MMIO(0x30014)
1059 #define OGAMC3 _MMIO(0x30018)
1060 #define OGAMC2 _MMIO(0x3001c)
1061 #define OGAMC1 _MMIO(0x30020)
1062 #define OGAMC0 _MMIO(0x30024)
1067 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1074 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1078 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1081 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1084 #define _CLKGATE_DIS_PSL_A 0x46520
1085 #define _CLKGATE_DIS_PSL_B 0x46524
1086 #define _CLKGATE_DIS_PSL_C 0x46528
1098 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C
1099 #define _CLKGATE_DIS_PSL_EXT_B 0x46550
1110 #define _TRANS_HTOTAL_A 0x60000
1111 #define _TRANS_HTOTAL_B 0x61000
1115 #define HACTIVE_MASK REG_GENMASK(15, 0)
1118 #define _TRANS_HBLANK_A 0x60004
1119 #define _TRANS_HBLANK_B 0x61004
1123 #define HBLANK_START_MASK REG_GENMASK(15, 0)
1126 #define _TRANS_HSYNC_A 0x60008
1127 #define _TRANS_HSYNC_B 0x61008
1131 #define HSYNC_START_MASK REG_GENMASK(15, 0)
1134 #define _TRANS_VTOTAL_A 0x6000c
1135 #define _TRANS_VTOTAL_B 0x6100c
1139 #define VACTIVE_MASK REG_GENMASK(15, 0)
1142 #define _TRANS_VBLANK_A 0x60010
1143 #define _TRANS_VBLANK_B 0x61010
1147 #define VBLANK_START_MASK REG_GENMASK(15, 0)
1150 #define _TRANS_VSYNC_A 0x60014
1151 #define _TRANS_VSYNC_B 0x61014
1155 #define VSYNC_START_MASK REG_GENMASK(15, 0)
1158 #define _PIPEASRC 0x6001c
1159 #define _PIPEBSRC 0x6101c
1163 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1166 #define _BCLRPAT_A 0x60020
1167 #define _BCLRPAT_B 0x61020
1170 #define _TRANS_VSYNCSHIFT_A 0x60028
1171 #define _TRANS_VSYNCSHIFT_B 0x61028
1174 #define _TRANS_MULT_A 0x6002c
1175 #define _TRANS_MULT_B 0x6102c
1179 #define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
1194 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1197 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1199 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1204 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1206 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1209 #define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
1229 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1264 #define _GEN3_SDVOB 0x61140
1265 #define _GEN3_SDVOC 0x61160
1270 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
1271 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
1272 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
1273 #define PCH_SDVOB _MMIO(0xe1140)
1275 #define PCH_HDMIC _MMIO(0xe1150)
1276 #define PCH_HDMID _MMIO(0xe1160)
1278 #define PORT_DFT_I9XX _MMIO(0x61150)
1280 #define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
1282 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
1285 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
1314 #define SDVO_COLOR_FORMAT_8bpc (0 << 26)
1316 #define SDVO_ENCODING_SDVO (0 << 10)
1319 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
1341 #define VIDEO_DIP_DATA _MMIO(0x61178)
1350 #define VIDEO_DIP_CTL _MMIO(0x61170)
1360 #define VIDEO_DIP_SELECT_AVI (0 << 19)
1365 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
1372 #define VSC_SELECT_MASK (0x3 << 25)
1374 #define VSC_DIP_HW_HEA_DATA (0 << 25)
1384 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
1388 #define PCH_GTC_CTL _MMIO(0xe7000)
1392 #define DP_A _MMIO(0x64000) /* eDP */
1393 #define DP_B _MMIO(0x64100)
1394 #define DP_C _MMIO(0x64200)
1395 #define DP_D _MMIO(0x64300)
1396 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
1397 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
1398 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
1411 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
1419 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
1427 #define DP_VOLTAGE_0_4 (0 << 25)
1437 #define DP_PRE_EMPHASIS_0 (0 << 22)
1453 #define DP_PLL_FREQ_270MHZ (0 << 16)
1495 #define _PIPEA_DATA_M_G4X 0x70050
1496 #define _PIPEB_DATA_M_G4X 0x71050
1498 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1501 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
1502 #define DATA_LINK_N_MAX (0x800000)
1504 #define _PIPEA_DATA_N_G4X 0x70054
1505 #define _PIPEB_DATA_N_G4X 0x71054
1518 #define _PIPEA_LINK_M_G4X 0x70060
1519 #define _PIPEB_LINK_M_G4X 0x71060
1522 #define _PIPEA_LINK_N_G4X 0x70064
1523 #define _PIPEB_LINK_N_G4X 0x71064
1527 #define _PIPEADSL 0x70000
1530 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
1532 #define _TRANSACONF 0x70008
1539 …CONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
1544 #define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
1550 #define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
1561 #define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
1574 #define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* il…
1579 #define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
1585 #define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
1589 #define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
1592 #define _PIPEASTAT 0x70024
1638 #define PIPE_HBLANK_INT_STATUS (1UL << 0)
1639 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
1640 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
1641 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff
1643 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
1647 #define _PIPE_MISC_A 0x70030
1648 #define _PIPE_MISC_B 0x71030
1667 #define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
1673 #define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
1678 #define _PIPE_MISC2_A 0x7002C
1679 #define _PIPE_MISC2_B 0x7102C
1684 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1687 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
1708 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
1723 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
1724 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
1736 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
1738 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
1742 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
1760 #define _PIPEAFRAMEHIGH 0x70040
1762 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
1763 #define PIPE_FRAME_HIGH_SHIFT 0
1765 #define _PIPEAFRAMEPIXEL 0x70044
1767 #define PIPE_FRAME_LOW_MASK 0xff000000
1769 #define PIPE_PIXEL_MASK 0x00ffffff
1770 #define PIPE_PIXEL_SHIFT 0
1773 #define _PIPEA_FRMCOUNT_G4X 0x70040
1776 #define _PIPEA_FLIPCOUNT_G4X 0x70044
1780 #define _CHV_BLEND_A 0x60a00
1783 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
1787 #define _CHV_CANVAS_A 0x60a04
1791 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
1794 #define DISP_BASEADDR_MASK (0xfffff000)
1805 * [00:0f] all
1809 #define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
1810 #define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
1811 #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
1812 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
1815 #define VGACNTRL _MMIO(0x71400)
1820 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
1824 #define CPU_VGACNTRL _MMIO(0x41000)
1826 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
1828 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
1833 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
1834 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
1835 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
1836 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
1839 #define RR_HW_CTL _MMIO(0x45300)
1840 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
1841 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
1843 #define PCH_3DCGDIS0 _MMIO(0x46020)
1847 #define PCH_3DCGDIS1 _MMIO(0x46024)
1850 #define _PIPEA_DATA_M1 0x60030
1851 #define _PIPEB_DATA_M1 0x61030
1854 #define _PIPEA_DATA_N1 0x60034
1855 #define _PIPEB_DATA_N1 0x61034
1858 #define _PIPEA_DATA_M2 0x60038
1859 #define _PIPEB_DATA_M2 0x61038
1862 #define _PIPEA_DATA_N2 0x6003c
1863 #define _PIPEB_DATA_N2 0x6103c
1866 #define _PIPEA_LINK_M1 0x60040
1867 #define _PIPEB_LINK_M1 0x61040
1870 #define _PIPEA_LINK_N1 0x60044
1871 #define _PIPEB_LINK_N1 0x61044
1874 #define _PIPEA_LINK_M2 0x60048
1875 #define _PIPEB_LINK_M2 0x61048
1878 #define _PIPEA_LINK_N2 0x6004c
1879 #define _PIPEB_LINK_N2 0x6104c
1886 #define _PS_1A_CTRL 0x68180
1887 #define _PS_2A_CTRL 0x68280
1888 #define _PS_1B_CTRL 0x68980
1889 #define _PS_2B_CTRL 0x68A80
1890 #define _PS_1C_CTRL 0x69180
1896 #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
1899 #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
1903 #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
1907 #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
1910 #define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
1915 #define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
1918 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-lin…
1927 #define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
1941 #define _PS_PWR_GATE_1A 0x68160
1942 #define _PS_PWR_GATE_2A 0x68260
1943 #define _PS_PWR_GATE_1B 0x68960
1944 #define _PS_PWR_GATE_2B 0x68A60
1945 #define _PS_PWR_GATE_1C 0x69160
1951 #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
1955 #define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
1956 #define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
1961 #define _PS_WIN_POS_1A 0x68170
1962 #define _PS_WIN_POS_2A 0x68270
1963 #define _PS_WIN_POS_1B 0x68970
1964 #define _PS_WIN_POS_2B 0x68A70
1965 #define _PS_WIN_POS_1C 0x69170
1971 #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
1974 #define _PS_WIN_SZ_1A 0x68174
1975 #define _PS_WIN_SZ_2A 0x68274
1976 #define _PS_WIN_SZ_1B 0x68974
1977 #define _PS_WIN_SZ_2B 0x68A74
1978 #define _PS_WIN_SZ_1C 0x69174
1984 #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
1987 #define _PS_VSCALE_1A 0x68184
1988 #define _PS_VSCALE_2A 0x68284
1989 #define _PS_VSCALE_1B 0x68984
1990 #define _PS_VSCALE_2B 0x68A84
1991 #define _PS_VSCALE_1C 0x69184
1996 #define _PS_HSCALE_1A 0x68190
1997 #define _PS_HSCALE_2A 0x68290
1998 #define _PS_HSCALE_1B 0x68990
1999 #define _PS_HSCALE_2B 0x68A90
2000 #define _PS_HSCALE_1C 0x69190
2005 #define _PS_VPHASE_1A 0x68188
2006 #define _PS_VPHASE_2A 0x68288
2007 #define _PS_VPHASE_1B 0x68988
2008 #define _PS_VPHASE_2B 0x68A88
2009 #define _PS_VPHASE_1C 0x69188
2015 #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
2017 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
2018 #define PS_PHASE_TRIP (1 << 0)
2020 #define _PS_HPHASE_1A 0x68194
2021 #define _PS_HPHASE_2A 0x68294
2022 #define _PS_HPHASE_1B 0x68994
2023 #define _PS_HPHASE_2B 0x68A94
2024 #define _PS_HPHASE_1C 0x69194
2029 #define _PS_ECC_STAT_1A 0x681D0
2030 #define _PS_ECC_STAT_2A 0x682D0
2031 #define _PS_ECC_STAT_1B 0x689D0
2032 #define _PS_ECC_STAT_2B 0x68AD0
2033 #define _PS_ECC_STAT_1C 0x691D0
2038 #define _PS_COEF_SET0_INDEX_1A 0x68198
2039 #define _PS_COEF_SET0_INDEX_2A 0x68298
2040 #define _PS_COEF_SET0_INDEX_1B 0x68998
2041 #define _PS_COEF_SET0_INDEX_2B 0x68A98
2047 #define _PS_COEF_SET0_DATA_1A 0x6819C
2048 #define _PS_COEF_SET0_DATA_2A 0x6829C
2049 #define _PS_COEF_SET0_DATA_1B 0x6899C
2050 #define _PS_COEF_SET0_DATA_2B 0x68A9C
2056 #define RM_TIMEOUT _MMIO(0x42060)
2057 #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
2058 #define MMIO_TIMEOUT_US(us) ((us) << 0)
2090 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2109 #define DE_PIPEA_VBLANK_IVB (1 << 0)
2112 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
2115 #define DEISR _MMIO(0x44000)
2116 #define DEIMR _MMIO(0x44004)
2117 #define DEIIR _MMIO(0x44008)
2118 #define DEIER _MMIO(0x4400c)
2124 #define GTISR _MMIO(0x44010)
2125 #define GTIMR _MMIO(0x44014)
2126 #define GTIIR _MMIO(0x44018)
2127 #define GTIER _MMIO(0x4401c)
2133 #define GEN8_MASTER_IRQ _MMIO(0x44200)
2149 #define GEN8_GT_RCS_IRQ (1 << 0)
2151 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
2153 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
2154 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
2155 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
2156 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
2162 #define GEN8_RCS_IRQ_SHIFT 0
2164 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
2166 #define GEN8_VECS_IRQ_SHIFT 0
2169 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
2170 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
2171 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
2172 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
2209 #define GEN8_PIPE_VBLANK REG_BIT(0)
2218 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
2219 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
2220 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
2221 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
2237 #define GEN8_AUX_CHANNEL_A (1 << 0)
2248 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
2254 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
2255 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
2256 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
2257 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
2269 #define GEN8_PCU_ISR _MMIO(0x444e0)
2270 #define GEN8_PCU_IMR _MMIO(0x444e4)
2271 #define GEN8_PCU_IIR _MMIO(0x444e8)
2272 #define GEN8_PCU_IER _MMIO(0x444ec)
2278 #define GEN11_GU_MISC_ISR _MMIO(0x444f0)
2279 #define GEN11_GU_MISC_IMR _MMIO(0x444f4)
2280 #define GEN11_GU_MISC_IIR _MMIO(0x444f8)
2281 #define GEN11_GU_MISC_IER _MMIO(0x444fc)
2288 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
2295 #define GEN11_GT_DW0_IRQ (1 << 0)
2297 #define DG1_MSTR_TILE_INTR _MMIO(0x190008)
2301 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
2312 #define GEN11_DE_HPD_ISR _MMIO(0x44470)
2313 #define GEN11_DE_HPD_IMR _MMIO(0x44474)
2314 #define GEN11_DE_HPD_IIR _MMIO(0x44478)
2315 #define GEN11_DE_HPD_IER _MMIO(0x4447c)
2335 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
2336 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
2340 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
2342 #define PICAINTERRUPT_ISR _MMIO(0x16FE50)
2343 #define PICAINTERRUPT_IMR _MMIO(0x16FE54)
2344 #define PICAINTERRUPT_IIR _MMIO(0x16FE58)
2345 #define PICAINTERRUPT_IER _MMIO(0x16FE5C)
2353 #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
2359 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
2365 #define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
2367 #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
2374 #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
2380 #define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
2382 #define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
2385 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
2391 #define FUSE_STRAP _MMIO(0x42014)
2402 #define FUSE_STRAP3 _MMIO(0x42020)
2405 #define ILK_DSPCLK_GATE_D _MMIO(0x42020)
2412 #define IVB_CHICKEN3 _MMIO(0x4200c)
2416 #define CHICKEN_PAR1_1 _MMIO(0x42080)
2426 #define CHICKEN_PAR2_1 _MMIO(0x42090)
2429 #define CHICKEN_MISC_2 _MMIO(0x42084)
2438 #define CHICKEN_MISC_3 _MMIO(0x42088)
2441 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
2443 #define CHICKEN_MISC_4 _MMIO(0x4208c)
2445 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
2448 #define _CHICKEN_PIPESL_1_A 0x420b0
2449 #define _CHICKEN_PIPESL_1_B 0x420b4
2452 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
2457 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
2464 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
2465 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
2469 #define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
2471 #define _CHICKEN_TRANS_A 0x420c0
2472 #define _CHICKEN_TRANS_B 0x420c4
2473 #define _CHICKEN_TRANS_C 0x420c8
2474 #define _CHICKEN_TRANS_EDP 0x420cc
2475 #define _CHICKEN_TRANS_D 0x420d8
2482 #define _MTL_CHICKEN_TRANS_A 0x604e0
2483 #define _MTL_CHICKEN_TRANS_B 0x614e0
2503 #define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
2505 #define DISP_ARB_CTL _MMIO(0x45000)
2510 #define DISP_ARB_CTL2 _MMIO(0x45004)
2514 #define GEN7_MSG_CTL _MMIO(0x45010)
2516 #define WAIT_FOR_PCH_FLR_ACK (1 << 0)
2518 #define _BW_BUDDY0_CTL 0x45130
2519 #define _BW_BUDDY1_CTL 0x45140
2527 #define _BW_BUDDY0_PAGE_MASK 0x45134
2528 #define _BW_BUDDY1_PAGE_MASK 0x45144
2533 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
2537 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
2553 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
2559 #define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
2562 #define SKL_DFSM _MMIO(0x51000)
2566 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
2578 #define XE2LPD_DE_CAP _MMIO(0x41100)
2585 #define SKL_DSSM _MMIO(0x51004)
2587 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
2591 #define GMD_ID_DISPLAY _MMIO(0x510a0)
2594 #define GMD_ID_STEP REG_GENMASK(5, 0)
2597 #define _PIPEA_CHICKEN 0x70038
2598 #define _PIPEB_CHICKEN 0x71038
2599 #define _PIPEC_CHICKEN 0x72038
2610 #define PCH_DISPLAY_BASE 0xc0000u
2650 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
2651 #define SDE_TRANS_MASK (0x3f)
2690 #define SDE_FDI_RXA_CPT (1 << 0)
2718 #define SDEISR _MMIO(0xc4000)
2719 #define SDEIMR _MMIO(0xc4004)
2720 #define SDEIIR _MMIO(0xc4008)
2721 #define SDEIER _MMIO(0xc400c)
2727 #define SERR_INT _MMIO(0xc4040)
2732 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
2736 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
2740 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
2746 #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
2751 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
2757 #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
2762 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
2767 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
2768 #define PORTB_HOTPLUG_NO_DETECT (0 << 0)
2769 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2770 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
2775 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
2777 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
2778 #define PORTE_HOTPLUG_NO_DETECT (0 << 0)
2779 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
2780 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
2787 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
2788 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
2789 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
2790 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
2791 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
2792 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
2793 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
2794 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
2796 #define SHOTPLUG_CTL_TC _MMIO(0xc4034)
2801 #define SHPD_FILTER_CNT _MMIO(0xc4038)
2802 #define SHPD_FILTER_CNT_500_ADJ 0x001D9
2803 #define SHPD_FILTER_CNT_250 0x000F8
2805 #define _PCH_DPLL_A 0xc6014
2806 #define _PCH_DPLL_B 0xc6018
2807 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
2809 #define _PCH_FPA0 0xc6040
2810 #define _PCH_FPB0 0xc6048
2811 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
2812 #define FP_CB_TUNE (0x3 << 22)
2814 #define _PCH_FPA1 0xc6044
2815 #define _PCH_FPB1 0xc604c
2816 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
2818 #define PCH_DPLL_TEST _MMIO(0xc606c)
2820 #define PCH_DREF_CONTROL _MMIO(0xC6200)
2821 #define DREF_CONTROL_MASK 0x7fc3
2822 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
2826 #define DREF_SSC_SOURCE_DISABLE (0 << 11)
2829 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
2833 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
2836 #define DREF_SSC4_DOWNSPREAD (0 << 6)
2838 #define DREF_SSC1_DISABLE (0 << 1)
2840 #define DREF_SSC4_DISABLE (0)
2843 #define PCH_RAWCLK_FREQ _MMIO(0xc6204)
2848 #define RAWCLK_FREQ_MASK 0x3ff
2849 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
2851 #define CNP_RAWCLK_FRAC_MASK (0xf << 26)
2855 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
2857 #define PCH_SSC4_PARMS _MMIO(0xc6210)
2858 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
2860 #define PCH_DPLL_SEL _MMIO(0xc7000)
2862 #define TRANS_DPLLA_SEL(pipe) 0
2867 #define _PCH_TRANS_HTOTAL_A 0xe0000
2868 #define _PCH_TRANS_HTOTAL_B 0xe1000
2871 #define TRANS_HACTIVE_SHIFT 0
2873 #define _PCH_TRANS_HBLANK_A 0xe0004
2874 #define _PCH_TRANS_HBLANK_B 0xe1004
2877 #define TRANS_HBLANK_START_SHIFT 0
2879 #define _PCH_TRANS_HSYNC_A 0xe0008
2880 #define _PCH_TRANS_HSYNC_B 0xe1008
2883 #define TRANS_HSYNC_START_SHIFT 0
2885 #define _PCH_TRANS_VTOTAL_A 0xe000c
2886 #define _PCH_TRANS_VTOTAL_B 0xe100c
2889 #define TRANS_VACTIVE_SHIFT 0
2891 #define _PCH_TRANS_VBLANK_A 0xe0010
2892 #define _PCH_TRANS_VBLANK_B 0xe1010
2895 #define TRANS_VBLANK_START_SHIFT 0
2897 #define _PCH_TRANS_VSYNC_A 0xe0014
2898 #define _PCH_TRANS_VSYNC_B 0xe1014
2901 #define TRANS_VSYNC_START_SHIFT 0
2903 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
2904 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
2907 #define _PCH_TRANSA_DATA_M1 0xe0030
2908 #define _PCH_TRANSB_DATA_M1 0xe1030
2911 #define _PCH_TRANSA_DATA_N1 0xe0034
2912 #define _PCH_TRANSB_DATA_N1 0xe1034
2915 #define _PCH_TRANSA_DATA_M2 0xe0038
2916 #define _PCH_TRANSB_DATA_M2 0xe1038
2919 #define _PCH_TRANSA_DATA_N2 0xe003c
2920 #define _PCH_TRANSB_DATA_N2 0xe103c
2923 #define _PCH_TRANSA_LINK_M1 0xe0040
2924 #define _PCH_TRANSB_LINK_M1 0xe1040
2927 #define _PCH_TRANSA_LINK_N1 0xe0044
2928 #define _PCH_TRANSB_LINK_N1 0xe1044
2931 #define _PCH_TRANSA_LINK_M2 0xe0048
2932 #define _PCH_TRANSB_LINK_M2 0xe1048
2935 #define _PCH_TRANSA_LINK_N2 0xe004c
2936 #define _PCH_TRANSB_LINK_N2 0xe104c
2940 #define _VIDEO_DIP_CTL_A 0xe0200
2941 #define _VIDEO_DIP_CTL_B 0xe1200
2944 #define _VIDEO_DIP_DATA_A 0xe0208
2945 #define _VIDEO_DIP_DATA_B 0xe1208
2948 #define _VIDEO_DIP_GCP_A 0xe0210
2949 #define _VIDEO_DIP_GCP_B 0xe1210
2953 #define GCP_AV_MUTE (1 << 0)
2956 #define _VLV_VIDEO_DIP_CTL_A 0x60200
2957 #define _VLV_VIDEO_DIP_CTL_B 0x61170
2958 #define _CHV_VIDEO_DIP_CTL_C 0x611f0
2964 #define _VLV_VIDEO_DIP_DATA_A 0x60208
2965 #define _VLV_VIDEO_DIP_DATA_B 0x61174
2966 #define _CHV_VIDEO_DIP_DATA_C 0x611f4
2972 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
2973 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
2974 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
2981 #define _HSW_VIDEO_DIP_CTL_A 0x60200
2982 #define _HSW_VIDEO_DIP_CTL_B 0x61200
2985 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
2986 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
2989 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
2990 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
2993 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
2994 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
2997 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
2998 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
3001 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
3002 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
3006 #define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
3007 #define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
3011 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
3012 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
3015 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
3016 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
3017 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
3018 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
3019 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
3020 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
3021 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
3022 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
3023 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
3024 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
3026 #define _HSW_VIDEO_DIP_GCP_A 0x60210
3027 #define _HSW_VIDEO_DIP_GCP_B 0x61210
3036 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
3037 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
3040 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
3041 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
3044 #define _HSW_STEREO_3D_CTL_A 0x70020
3045 #define _HSW_STEREO_3D_CTL_B 0x71020
3049 #define _PCH_TRANSACONF 0xf0008
3050 #define _PCH_TRANSBCONF 0xf1008
3056 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
3058 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
3062 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
3067 #define _TRANSA_CHICKEN1 0xf0060
3068 #define _TRANSB_CHICKEN1 0xf1060
3073 #define _TRANSA_CHICKEN2 0xf0064
3074 #define _TRANSB_CHICKEN2 0xf1064
3079 …CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
3083 #define SOUTH_CHICKEN1 _MMIO(0xc2000)
3099 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
3103 #define SPT_PWM_GRANULARITY (1 << 0)
3104 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
3108 #define DPLS_EDP_PPS_FIX_DIS (1 << 0)
3110 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
3119 #define PCH_DP_B _MMIO(0xe4100)
3120 #define PCH_DP_C _MMIO(0xe4200)
3121 #define PCH_DP_D _MMIO(0xe4300)
3124 #define _TRANS_DP_CTL_A 0xe0300
3125 #define _TRANS_DP_CTL_B 0xe1300
3126 #define _TRANS_DP_CTL_C 0xe2300
3135 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
3142 #define _TRANS_DP2_CTL_A 0x600a0
3143 #define _TRANS_DP2_CTL_B 0x610a0
3144 #define _TRANS_DP2_CTL_C 0x620a0
3145 #define _TRANS_DP2_CTL_D 0x630a0
3151 #define _TRANS_DP2_VFREQHIGH_A 0x600a4
3152 #define _TRANS_DP2_VFREQHIGH_B 0x610a4
3153 #define _TRANS_DP2_VFREQHIGH_C 0x620a4
3154 #define _TRANS_DP2_VFREQHIGH_D 0x630a4
3159 #define _TRANS_DP2_VFREQLOW_A 0x600a8
3160 #define _TRANS_DP2_VFREQLOW_B 0x610a8
3161 #define _TRANS_DP2_VFREQLOW_C 0x620a8
3162 #define _TRANS_DP2_VFREQLOW_D 0x630a8
3165 #define _DP_MIN_HBLANK_CTL_A 0x600ac
3166 #define _DP_MIN_HBLANK_CTL_B 0x610ac
3171 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
3172 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
3173 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
3174 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
3176 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
3177 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
3178 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
3179 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
3180 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
3181 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
3184 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
3185 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
3186 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
3187 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
3188 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
3189 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
3190 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
3193 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
3194 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
3195 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
3196 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
3197 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
3199 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
3201 #define VLV_PMWGICZ _MMIO(0x1300a4)
3203 #define HSW_EDRAM_CAP _MMIO(0x120010)
3204 #define EDRAM_ENABLED 0x1
3205 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
3206 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
3207 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
3209 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
3213 #define GEN6_PCODE_MAILBOX _MMIO(0x138124)
3217 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
3218 #define GEN6_PCODE_ERROR_MASK 0xFF
3219 #define GEN6_PCODE_SUCCESS 0x0
3220 #define GEN6_PCODE_ILLEGAL_CMD 0x1
3221 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
3222 #define GEN6_PCODE_TIMEOUT 0x3
3223 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
3224 #define GEN7_PCODE_TIMEOUT 0x2
3225 #define GEN7_PCODE_ILLEGAL_DATA 0x3
3226 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
3227 #define GEN11_PCODE_LOCKED 0x6
3228 #define GEN11_PCODE_REJECTED 0x11
3229 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
3230 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
3231 #define GEN6_PCODE_READ_RC6VIDS 0x5
3234 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
3235 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
3239 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
3240 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5
3241 #define SKL_PCODE_CDCLK_CONTROL 0x7
3242 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
3243 #define SKL_CDCLK_READY_FOR_CHANGE 0x1
3244 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3245 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3246 #define GEN6_READ_OC_PARAMS 0xc
3247 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
3248 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
3249 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
3250 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
3251 #define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
3252 #define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
3265 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
3266 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
3267 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
3271 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
3274 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
3278 #define GEN6_PCODE_READ_D_COMP 0x10
3279 #define GEN6_PCODE_WRITE_D_COMP 0x11
3280 #define ICL_PCODE_EXIT_TCCOLD 0x12
3281 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
3282 #define DISPLAY_IPS_CONTROL 0x19
3283 #define TGL_PCODE_TCCOLD 0x26
3284 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
3285 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
3286 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
3289 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
3290 #define GEN9_PCODE_SAGV_CONTROL 0x21
3291 #define GEN9_SAGV_DISABLE 0x0
3292 #define GEN9_SAGV_IS_DISABLED 0x1
3293 #define GEN9_SAGV_ENABLE 0x3
3294 #define DG1_PCODE_STATUS 0x7E
3295 #define DG1_UNCORE_GET_INIT_STATUS 0x0
3296 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
3297 #define PCODE_POWER_SETUP 0x7C
3298 #define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
3299 #define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
3302 #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
3303 #define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
3304 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
3305 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
3307 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
3308 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
3311 #define PCODE_MBOX_DOMAIN_NONE 0x0
3312 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
3313 #define GEN6_PCODE_DATA _MMIO(0x138128)
3316 #define GEN6_PCODE_DATA1 _MMIO(0x13812C)
3318 #define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
3319 #define STOLEN_ACCESS_ALLOWED 0x1
3322 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
3323 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
3339 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
3356 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
3357 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
3358 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
3359 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
3360 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
3361 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
3377 #define SKL_PW_CTL_IDX_MISC_IO 0
3384 #define ICL_PW_CTL_IDX_PW_1 0
3392 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
3393 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
3394 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
3418 #define ICL_PW_CTL_IDX_AUX_A 0
3420 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
3421 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
3422 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
3436 #define ICL_PW_CTL_IDX_DDI_A 0
3439 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
3443 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
3454 #define SKL_FUSE_STATUS _MMIO(0x42000)
3471 #define _TRANS_DDI_FUNC_CTL_A 0x60400
3472 #define _TRANS_DDI_FUNC_CTL_B 0x61400
3473 #define _TRANS_DDI_FUNC_CTL_C 0x62400
3474 #define _TRANS_DDI_FUNC_CTL_D 0x63400
3475 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
3476 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
3477 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
3485 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
3489 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
3495 #define TRANS_DDI_BPC_8 (0 << 20)
3506 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
3524 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
3529 #define _TRANS_DDI_FUNC_CTL2_A 0x60404
3530 #define _TRANS_DDI_FUNC_CTL2_B 0x61404
3531 #define _TRANS_DDI_FUNC_CTL2_C 0x62404
3532 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
3533 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
3534 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
3538 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
3541 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
3545 #define _DP_TP_CTL_A 0x64040
3546 #define _DP_TP_CTL_B 0x64140
3547 #define _TGL_DP_TP_CTL_A 0x60540
3553 #define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)
3557 #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)
3563 #define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)
3572 #define _DP_TP_STATUS_A 0x64044
3573 #define _DP_TP_STATUS_B 0x64144
3574 #define _TGL_DP_TP_STATUS_A 0x60544
3585 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0)
3588 #define _DDI_BUF_CTL_A 0x64000
3589 #define _DDI_BUF_CTL_B 0x64100
3600 #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
3614 #define DDI_INIT_DISPLAY_DETECTED REG_BIT(0)
3617 #define _DDI_BUF_TRANS_A 0x64E00
3618 #define _DDI_BUF_TRANS_B 0x64E60
3624 #define _DDI_DP_COMP_CTL_A 0x605F0
3625 #define _DDI_DP_COMP_CTL_B 0x615F0
3628 #define DDI_DP_COMP_CTL_D10_2 (0 << 28)
3634 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
3637 #define _DDI_DP_COMP_PAT_A 0x605F4
3638 #define _DDI_DP_COMP_PAT_B 0x615F4
3644 #define SBI_ADDR _MMIO(0xC6000)
3645 #define SBI_DATA _MMIO(0xC6004)
3646 #define SBI_CTL_STAT _MMIO(0xC6008)
3647 #define SBI_CTL_DEST_ICLK (0x0 << 16)
3648 #define SBI_CTL_DEST_MPHY (0x1 << 16)
3649 #define SBI_CTL_OP_IORD (0x2 << 8)
3650 #define SBI_CTL_OP_IOWR (0x3 << 8)
3651 #define SBI_CTL_OP_CRRD (0x6 << 8)
3652 #define SBI_CTL_OP_CRWR (0x7 << 8)
3653 #define SBI_RESPONSE_FAIL (0x1 << 1)
3654 #define SBI_RESPONSE_SUCCESS (0x0 << 1)
3655 #define SBI_BUSY (0x1 << 0)
3656 #define SBI_READY (0x0 << 0)
3659 #define SBI_SSCDIVINTPHASE 0x0200
3660 #define SBI_SSCDIVINTPHASE6 0x0600
3662 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
3665 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
3668 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
3669 #define SBI_SSCDITHPHASE 0x0204
3670 #define SBI_SSCCTL 0x020c
3671 #define SBI_SSCCTL6 0x060C
3673 #define SBI_SSCCTL_DISABLE (1 << 0)
3674 #define SBI_SSCAUXDIV6 0x0610
3678 #define SBI_DBUFF0 0x2a00
3679 #define SBI_GEN0 0x1f00
3680 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
3683 #define PIXCLK_GATE _MMIO(0xC6020)
3684 #define PIXCLK_GATE_UNGATE (1 << 0)
3685 #define PIXCLK_GATE_GATE (0 << 0)
3688 #define SPLL_CTL _MMIO(0x46020)
3690 #define SPLL_REF_BCLK (0 << 28)
3696 #define SPLL_FREQ_810MHz (0 << 26)
3702 #define _WRPLL_CTL1 0x46040
3703 #define _WRPLL_CTL2 0x46060
3706 #define WRPLL_REF_BCLK (0 << 28)
3713 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
3714 #define WRPLL_DIVIDER_REF_MASK (0xff)
3716 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
3720 #define WRPLL_DIVIDER_FB_MASK (0xff << 16)
3723 #define _PORT_CLK_SEL_A 0x46100
3724 #define _PORT_CLK_SEL_B 0x46104
3727 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
3739 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
3740 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
3741 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
3742 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
3743 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
3744 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
3747 #define _TRANS_CLK_SEL_A 0x46140
3748 #define _TRANS_CLK_SEL_B 0x46144
3751 #define TRANS_CLK_SEL_DISABLED (0x0 << 29)
3753 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
3757 #define CDCLK_FREQ _MMIO(0x46200)
3759 #define _TRANSA_MSA_MISC 0x60410
3760 #define _TRANSB_MSA_MISC 0x61410
3761 #define _TRANSC_MSA_MISC 0x62410
3762 #define _TRANS_EDP_MSA_MISC 0x6f410
3766 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
3767 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
3768 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
3769 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
3771 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
3775 #define LCPLL_CTL _MMIO(0x130040)
3778 #define LCPLL_REF_NON_SSC (0 << 28)
3783 #define LCPLL_CLK_FREQ_450 (0 << 26)
3799 #define CDCLK_CTL _MMIO(0x46000)
3801 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
3806 #define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
3809 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
3816 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
3821 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
3824 #define CDCLK_SQUASH_CTL _MMIO(0x46008)
3828 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
3832 #define LCPLL1_CTL _MMIO(0x46010)
3833 #define LCPLL2_CTL _MMIO(0x46014)
3837 #define DPLL_CTRL1 _MMIO(0x6C058)
3844 #define DPLL_CTRL1_LINK_RATE_2700 0
3852 #define DPLL_CTRL2 _MMIO(0x6C05C)
3860 #define DPLL_STATUS _MMIO(0x6C060)
3864 #define _DPLL1_CFGCR1 0x6C040
3865 #define _DPLL2_CFGCR1 0x6C048
3866 #define _DPLL3_CFGCR1 0x6C050
3869 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
3871 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
3873 #define _DPLL1_CFGCR2 0x6C044
3874 #define _DPLL2_CFGCR2 0x6C04C
3875 #define _DPLL3_CFGCR2 0x6C054
3877 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
3882 #define DPLL_CFGCR2_KDIV_5 (0 << 5)
3888 #define DPLL_CFGCR2_PDIV_1 (0 << 2)
3896 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
3905 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
3917 #define _DG1_DPCLKA_CFGCR0 0x164280
3918 #define _DG1_DPCLKA1_CFGCR0 0x16C280
3927 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
3930 #define _ADLS_DPCLKA_CFGCR0 0x164280
3931 #define _ADLS_DPCLKA_CFGCR1 0x1642BC
3939 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
3942 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
3951 #define _DPLL0_ENABLE 0x46010
3952 #define _DPLL1_ENABLE 0x46014
3953 #define _ADLS_DPLL2_ENABLE 0x46018
3954 #define _ADLS_DPLL3_ENABLE 0x46030
3963 #define _DG2_PLL3_ENABLE 0x4601C
3969 #define TBT_PLL_ENABLE _MMIO(0x46020)
3971 #define _MG_PLL1_ENABLE 0x46030
3972 #define _MG_PLL2_ENABLE 0x46034
3973 #define _MG_PLL3_ENABLE 0x46038
3974 #define _MG_PLL4_ENABLE 0x4603C
3985 #define PORTTC1_PLL_ENABLE 0x46038
3986 #define PORTTC2_PLL_ENABLE 0x46040
3991 #define _ICL_DPLL0_CFGCR0 0x164000
3992 #define _ICL_DPLL1_CFGCR0 0x164080
3998 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
3999 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
4007 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
4010 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
4012 #define _ICL_DPLL0_CFGCR1 0x164004
4013 #define _ICL_DPLL1_CFGCR1 0x164084
4016 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
4027 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
4034 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
4035 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
4036 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
4038 #define _TGL_DPLL0_CFGCR0 0x164284
4039 #define _TGL_DPLL1_CFGCR0 0x16428C
4040 #define _TGL_TBTPLL_CFGCR0 0x16429C
4047 #define _TGL_DPLL0_DIV0 0x164B00
4048 #define _TGL_DPLL1_DIV0 0x164C00
4053 #define _TGL_DPLL0_CFGCR1 0x164288
4054 #define _TGL_DPLL1_CFGCR1 0x164290
4055 #define _TGL_TBTPLL_CFGCR1 0x1642A0
4062 #define _DG1_DPLL2_CFGCR0 0x16C284
4063 #define _DG1_DPLL3_CFGCR0 0x16C28C
4068 #define _DG1_DPLL2_CFGCR1 0x16C288
4069 #define _DG1_DPLL3_CFGCR1 0x16C290
4075 #define _ADLS_DPLL4_CFGCR0 0x164294
4076 #define _ADLS_DPLL3_CFGCR0 0x1642C0
4081 #define _ADLS_DPLL4_CFGCR1 0x164298
4082 #define _ADLS_DPLL3_CFGCR1 0x1642C4
4088 #define BXT_DE_PLL_CTL _MMIO(0x6d000)
4090 #define BXT_DE_PLL_RATIO_MASK 0xff
4092 #define BXT_DE_PLL_ENABLE _MMIO(0x46070)
4098 #define ICL_CDCLK_PLL_RATIO_MASK 0xff
4101 #define DC_STATE_EN _MMIO(0x45504)
4102 #define DC_STATE_DISABLE 0
4107 #define DC_STATE_EN_UPTO_DC5 (1 << 0)
4109 #define DC_STATE_EN_UPTO_DC6 (2 << 0)
4110 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
4112 #define DC_STATE_DEBUG _MMIO(0x45520)
4113 #define DC_STATE_DEBUG_MASK_CORES (1 << 0)
4116 #define D_COMP_BDW _MMIO(0x138144)
4119 #define _WM_LINETIME_A 0x45270
4120 #define _WM_LINETIME_B 0x45274
4122 #define HSW_LINETIME_MASK REG_GENMASK(8, 0)
4128 #define SFUSE_STRAP _MMIO(0xc2014)
4136 #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
4139 #define GEN4_TIMESTAMP _MMIO(0x2358)
4140 #define ILK_TIMESTAMP_HI _MMIO(0x70070)
4141 #define IVB_TIMESTAMP_CTR _MMIO(0x44070)
4143 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
4144 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
4145 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
4147 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
4150 #define _PIPE_FRMTMSTMP_A 0x70048
4151 #define _PIPE_FRMTMSTMP_B 0x71048
4156 #define _PIPE_FLIPTMSTMP_A 0x7004C
4157 #define _PIPE_FLIPTMSTMP_B 0x7104C
4162 #define _PIPE_FLIPDONETMSTMP_A 0x70054
4163 #define _PIPE_FLIPDONETMSTMP_B 0x71054
4167 #define _VLV_PIPE_MSA_MISC_A 0x70048
4171 #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
4173 #define GGC _MMIO(0x108040)
4177 #define GEN6_GSMBASE _MMIO(0x108100)
4178 #define GEN6_DSMBASE _MMIO(0x1080C0)
4182 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
4187 #define _ICL_PHY_MISC_A 0x64C00
4188 #define _ICL_PHY_MISC_B 0x64C04
4189 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
4197 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
4202 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
4205 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
4208 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
4211 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
4213 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
4216 #define _TCSS_DDI_STATUS_1 0x161500
4217 #define _TCSS_DDI_STATUS_2 0x161504
4224 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
4226 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
4227 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
4228 #define PRIMARY_SPI_REGIONID _MMIO(0x102084)
4229 #define SPI_STATIC_REGIONS _MMIO(0x102090)
4230 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
4231 #define OROM_OFFSET _MMIO(0x1020c0)
4234 #define CLKREQ_POLICY _MMIO(0x101038)
4237 #define CLKGATE_DIS_MISC _MMIO(0x46534)
4240 #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
4241 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
4245 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
4248 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
4250 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
4254 #define MTL_DCLK_MASK REG_GENMASK(15, 0)
4258 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
4260 #define MTL_MEDIA_GSI_BASE 0x380000