Lines Matching +full:cs +full:- +full:x
1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
32 * set-context and then emitting the batch.
42 if (engine->class == RENDER_CLASS) { in set_hwstam()
43 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
57 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
60 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
65 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
68 return sg_page(obj->mm.pages->sgl); in status_page()
85 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
86 switch (engine->id) { in set_hwsp()
92 GEM_BUG_ON(engine->id); in set_hwsp()
107 } else if (GRAPHICS_VER(engine->i915) == 6) { in set_hwsp()
108 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); in set_hwsp()
110 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
113 intel_uncore_write_fw(engine->uncore, hwsp, offset); in set_hwsp()
114 intel_uncore_posting_read_fw(engine->uncore, hwsp); in set_hwsp()
119 if (!IS_GRAPHICS_VER(engine->i915, 6, 7)) in flush_cs_tlb()
124 drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n", in flush_cs_tlb()
125 engine->name); in flush_cs_tlb()
130 if (__intel_wait_for_register_fw(engine->uncore, in flush_cs_tlb()
131 RING_INSTPM(engine->mmio_base), in flush_cs_tlb()
140 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
149 vm = &i915_vm_to_ggtt(vm)->alias->vm; in vm_alias()
156 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir; in pp_dir()
161 struct i915_address_space *vm = vm_alias(engine->gt->vm); in set_pp_dir()
169 if (GRAPHICS_VER(engine->i915) >= 7) { in set_pp_dir()
195 struct intel_ring *ring = engine->legacy.ring; in xcs_resume()
198 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n", in xcs_resume()
199 ring->head, ring->tail); in xcs_resume()
205 intel_synchronize_hardirq(engine->i915); in xcs_resume()
209 if (HWS_NEEDS_PHYSICAL(engine->i915)) in xcs_resume()
214 intel_breadcrumbs_reset(engine->breadcrumbs); in xcs_resume()
225 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
228 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); in xcs_resume()
229 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); in xcs_resume()
248 ENGINE_WRITE_FW(engine, RING_HEAD, ring->head); in xcs_resume()
249 if (ENGINE_READ_FW(engine, RING_HEAD) == ring->head) in xcs_resume()
253 ENGINE_WRITE_FW(engine, RING_TAIL, ring->head); in xcs_resume()
255 ENGINE_TRACE(engine, "failed to reset empty ring: [%x, %x]: %x\n", in xcs_resume()
258 ring->head); in xcs_resume()
263 RING_CTL_SIZE(ring->size) | RING_VALID); in xcs_resume()
266 if (__intel_wait_for_register_fw(engine->uncore, in xcs_resume()
267 RING_CTL(engine->mmio_base), in xcs_resume()
274 if (GRAPHICS_VER(engine->i915) > 2) { in xcs_resume()
281 if (ring->tail != ring->head) { in xcs_resume()
282 ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail); in xcs_resume()
291 gt_err(engine->gt, "%s initialization failed\n", engine->name); in xcs_resume()
293 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", in xcs_resume()
296 ENGINE_READ(engine, RING_HEAD), ring->head, in xcs_resume()
297 ENGINE_READ(engine, RING_TAIL), ring->tail, in xcs_resume()
299 i915_ggtt_offset(ring->vma)); in xcs_resume()
301 return -EIO; in xcs_resume()
308 list_for_each_entry(tl, &engine->status_page.timelines, engine_link) in sanitize_hwsp()
324 memset(engine->status_page.addr, POISON_INUSE, PAGE_SIZE); in xcs_sanitize()
334 drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE); in xcs_sanitize()
363 "{ CTL:%08x, HEAD:%08x, TAIL:%08x, START:%08x }\n", in reset_prepare()
369 drm_err(&engine->i915->drm, in reset_prepare()
371 "ctl %08x head %08x tail %08x start %08x\n", in reset_prepare()
372 engine->name, in reset_prepare()
388 spin_lock_irqsave(&engine->sched_engine->lock, flags); in reset_rewind()
390 list_for_each_entry(pos, &engine->sched_engine->requests, sched.link) { in reset_rewind()
438 GEM_BUG_ON(rq->ring != engine->legacy.ring); in reset_rewind()
439 head = rq->head; in reset_rewind()
441 head = engine->legacy.ring->tail; in reset_rewind()
443 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); in reset_rewind()
445 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); in reset_rewind()
457 spin_lock_irqsave(&engine->sched_engine->lock, flags); in reset_cancel()
460 list_for_each_entry(request, &engine->sched_engine->requests, sched.link) in reset_cancel()
466 spin_unlock_irqrestore(&engine->sched_engine->lock, flags); in reset_cancel()
474 ENGINE_WRITE(request->engine, RING_TAIL, in i9xx_submit_request()
475 intel_ring_set_tail(request->ring, request->tail)); in i9xx_submit_request()
480 i915_vma_put(ce->state); in __ring_context_fini()
489 if (ce->state) in ring_context_destroy()
499 struct drm_i915_gem_object *obj = ce->state->obj; in ring_context_init_default_state()
506 shmem_read(ce->default_state, 0, vaddr, ce->engine->context_size); in ring_context_init_default_state()
511 __set_bit(CONTEXT_VALID_BIT, &ce->flags); in ring_context_init_default_state()
522 if (ce->default_state && in ring_context_pre_pin()
523 !test_bit(CONTEXT_VALID_BIT, &ce->flags)) { in ring_context_pre_pin()
529 vm = vm_alias(ce->vm); in ring_context_pre_pin()
540 vm = vm_alias(ce->vm); in __context_unpin_ppgtt()
557 struct drm_i915_private *i915 = engine->i915; in alloc_context_vma()
562 obj = i915_gem_object_create_shmem(i915, engine->context_size); in alloc_context_vma()
574 * Snooping is required on non-llc platforms in execlist in alloc_context_vma()
584 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in alloc_context_vma()
599 struct intel_engine_cs *engine = ce->engine; in ring_context_alloc()
602 ce->default_state = engine->default_state; in ring_context_alloc()
605 GEM_BUG_ON(!engine->legacy.ring); in ring_context_alloc()
606 ce->ring = engine->legacy.ring; in ring_context_alloc()
607 ce->timeline = intel_timeline_get(engine->legacy.timeline); in ring_context_alloc()
609 GEM_BUG_ON(ce->state); in ring_context_alloc()
610 if (engine->context_size) { in ring_context_alloc()
617 ce->state = vma; in ring_context_alloc()
630 intel_ring_reset(ce->ring, ce->ring->emit); in ring_context_reset()
631 clear_bit(CONTEXT_VALID_BIT, &ce->flags); in ring_context_reset()
643 engine = rq->engine; in ring_context_revoke()
644 lockdep_assert_held(&engine->sched_engine->lock); in ring_context_revoke()
645 list_for_each_entry_continue(rq, &engine->sched_engine->requests, in ring_context_revoke()
647 if (rq->context == ce) { in ring_context_revoke()
648 i915_request_set_error_once(rq, -EIO); in ring_context_revoke()
661 intel_gt_handle_error(engine->gt, engine->mask, 0, in ring_context_cancel_request()
663 current->comm); in ring_context_cancel_request()
689 const struct intel_engine_cs * const engine = rq->engine; in load_pd_dir()
690 u32 *cs; in load_pd_dir() local
692 cs = intel_ring_begin(rq, 12); in load_pd_dir()
693 if (IS_ERR(cs)) in load_pd_dir()
694 return PTR_ERR(cs); in load_pd_dir()
696 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
697 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
698 *cs++ = valid; in load_pd_dir()
700 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
701 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
702 *cs++ = pp_dir(vm); in load_pd_dir()
705 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; in load_pd_dir()
706 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
707 *cs++ = intel_gt_scratch_offset(engine->gt, in load_pd_dir()
710 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
711 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
712 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); in load_pd_dir()
714 intel_ring_advance(rq, cs); in load_pd_dir()
716 return rq->engine->emit_flush(rq, EMIT_FLUSH); in load_pd_dir()
723 struct intel_engine_cs *engine = rq->engine; in mi_set_context()
724 struct drm_i915_private *i915 = engine->i915; in mi_set_context()
727 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; in mi_set_context()
730 u32 *cs; in mi_set_context() local
744 cs = intel_ring_begin(rq, len); in mi_set_context()
745 if (IS_ERR(cs)) in mi_set_context()
746 return PTR_ERR(cs); in mi_set_context()
750 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; in mi_set_context()
754 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
755 for_each_engine(signaller, engine->gt, id) { in mi_set_context()
759 *cs++ = i915_mmio_reg_offset( in mi_set_context()
760 RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
761 *cs++ = _MASKED_BIT_ENABLE( in mi_set_context()
767 * This w/a is only listed for pre-production ilk a/b steppings, in mi_set_context()
770 * this should never take effect and so be a no-op! in mi_set_context()
772 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; in mi_set_context()
788 *cs++ = MI_SET_CONTEXT; in mi_set_context()
789 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
794 *cs++ = MI_NOOP; in mi_set_context()
795 *cs++ = MI_SET_CONTEXT; in mi_set_context()
796 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
801 *cs++ = MI_NOOP; in mi_set_context()
808 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
809 for_each_engine(signaller, engine->gt, id) { in mi_set_context()
813 last_reg = RING_PSMI_CTL(signaller->mmio_base); in mi_set_context()
814 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
815 *cs++ = _MASKED_BIT_DISABLE( in mi_set_context()
820 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; in mi_set_context()
821 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
822 *cs++ = intel_gt_scratch_offset(engine->gt, in mi_set_context()
824 *cs++ = MI_NOOP; in mi_set_context()
826 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; in mi_set_context()
828 *cs++ = MI_SUSPEND_FLUSH; in mi_set_context()
831 intel_ring_advance(rq, cs); in mi_set_context()
839 u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; in remap_l3_slice() local
845 cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2); in remap_l3_slice()
846 if (IS_ERR(cs)) in remap_l3_slice()
847 return PTR_ERR(cs); in remap_l3_slice()
854 *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW); in remap_l3_slice()
856 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
857 *cs++ = remap_info[i]; in remap_l3_slice()
859 *cs++ = MI_NOOP; in remap_l3_slice()
860 intel_ring_advance(rq, cs); in remap_l3_slice()
871 if (!ctx || !ctx->remap_slice) in remap_l3()
875 if (!(ctx->remap_slice & BIT(i))) in remap_l3()
883 ctx->remap_slice = 0; in remap_l3()
894 ret = rq->engine->emit_flush(rq, EMIT_FLUSH); in switch_mm()
899 * Not only do we need a full barrier (post-sync write) after in switch_mm()
903 * post-sync op, this extra pass appears vital before a in switch_mm()
910 return rq->engine->emit_flush(rq, EMIT_INVALIDATE); in switch_mm()
915 struct intel_engine_cs *engine = rq->engine; in clear_residuals()
918 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm)); in clear_residuals()
922 if (engine->kernel_context->state) { in clear_residuals()
924 engine->kernel_context, in clear_residuals()
930 ret = engine->emit_bb_start(rq, in clear_residuals()
931 i915_vma_offset(engine->wa_ctx.vma), 0, in clear_residuals()
936 ret = engine->emit_flush(rq, EMIT_FLUSH); in clear_residuals()
941 return engine->emit_flush(rq, EMIT_INVALIDATE); in clear_residuals()
946 struct intel_engine_cs *engine = rq->engine; in switch_context()
947 struct intel_context *ce = rq->context; in switch_context()
951 GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); in switch_context()
953 if (engine->wa_ctx.vma && ce != engine->kernel_context) { in switch_context()
954 if (engine->wa_ctx.vma->private != ce && in switch_context()
960 residuals = &engine->wa_ctx.vma->private; in switch_context()
964 ret = switch_mm(rq, vm_alias(ce->vm)); in switch_context()
968 if (ce->state) { in switch_context()
971 GEM_BUG_ON(engine->id != RCS0); in switch_context()
978 if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) in switch_context()
1013 GEM_BUG_ON(!intel_context_is_pinned(request->context)); in ring_request_alloc()
1014 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb); in ring_request_alloc()
1018 * we start building the request - in which case we will just in ring_request_alloc()
1021 request->reserved_space += LEGACY_REQUEST_SIZE; in ring_request_alloc()
1024 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); in ring_request_alloc()
1032 request->reserved_space -= LEGACY_REQUEST_SIZE; in ring_request_alloc()
1038 struct intel_uncore *uncore = request->engine->uncore; in gen6_bsd_submit_request()
1059 drm_err(&uncore->i915->drm, in gen6_bsd_submit_request()
1076 engine->submit_request = i9xx_submit_request; in i9xx_set_default_submission()
1081 engine->submit_request = gen6_bsd_submit_request; in gen6_bsd_set_default_submission()
1086 struct drm_i915_private *i915 = engine->i915; in ring_release()
1088 drm_WARN_ON(&i915->drm, GRAPHICS_VER(i915) > 2 && in ring_release()
1093 if (engine->wa_ctx.vma) { in ring_release()
1094 intel_context_put(engine->wa_ctx.vma->private); in ring_release()
1095 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); in ring_release()
1098 intel_ring_unpin(engine->legacy.ring); in ring_release()
1099 intel_ring_put(engine->legacy.ring); in ring_release()
1101 intel_timeline_unpin(engine->legacy.timeline); in ring_release()
1102 intel_timeline_put(engine->legacy.timeline); in ring_release()
1112 struct drm_i915_private *i915 = engine->i915; in setup_irq()
1117 engine->irq_enable = gen6_irq_enable; in setup_irq()
1118 engine->irq_disable = gen6_irq_disable; in setup_irq()
1120 engine->irq_enable = gen5_irq_enable; in setup_irq()
1121 engine->irq_disable = gen5_irq_disable; in setup_irq()
1123 engine->irq_enable = gen2_irq_enable; in setup_irq()
1124 engine->irq_disable = gen2_irq_disable; in setup_irq()
1130 lockdep_assert_held(&rq->engine->sched_engine->lock); in add_to_engine()
1131 list_move_tail(&rq->sched.link, &rq->engine->sched_engine->requests); in add_to_engine()
1136 spin_lock_irq(&rq->engine->sched_engine->lock); in remove_from_engine()
1137 list_del_init(&rq->sched.link); in remove_from_engine()
1140 set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); in remove_from_engine()
1142 spin_unlock_irq(&rq->engine->sched_engine->lock); in remove_from_engine()
1149 struct drm_i915_private *i915 = engine->i915; in setup_common()
1156 engine->resume = xcs_resume; in setup_common()
1157 engine->sanitize = xcs_sanitize; in setup_common()
1159 engine->reset.prepare = reset_prepare; in setup_common()
1160 engine->reset.rewind = reset_rewind; in setup_common()
1161 engine->reset.cancel = reset_cancel; in setup_common()
1162 engine->reset.finish = reset_finish; in setup_common()
1164 engine->add_active_request = add_to_engine; in setup_common()
1165 engine->remove_active_request = remove_from_engine; in setup_common()
1167 engine->cops = &ring_context_ops; in setup_common()
1168 engine->request_alloc = ring_request_alloc; in setup_common()
1173 * engine->emit_init_breadcrumb(). in setup_common()
1175 engine->emit_fini_breadcrumb = gen2_emit_breadcrumb; in setup_common()
1177 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; in setup_common()
1179 engine->set_default_submission = i9xx_set_default_submission; in setup_common()
1182 engine->emit_bb_start = gen6_emit_bb_start; in setup_common()
1184 engine->emit_bb_start = gen4_emit_bb_start; in setup_common()
1186 engine->emit_bb_start = i830_emit_bb_start; in setup_common()
1188 engine->emit_bb_start = gen2_emit_bb_start; in setup_common()
1193 struct drm_i915_private *i915 = engine->i915; in setup_rcs()
1196 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; in setup_rcs()
1198 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; in setup_rcs()
1201 engine->emit_flush = gen7_emit_flush_rcs; in setup_rcs()
1202 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; in setup_rcs()
1204 engine->emit_flush = gen6_emit_flush_rcs; in setup_rcs()
1205 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; in setup_rcs()
1207 engine->emit_flush = gen4_emit_flush_rcs; in setup_rcs()
1210 engine->emit_flush = gen2_emit_flush; in setup_rcs()
1212 engine->emit_flush = gen4_emit_flush_rcs; in setup_rcs()
1213 engine->irq_enable_mask = I915_USER_INTERRUPT; in setup_rcs()
1217 engine->emit_bb_start = hsw_emit_bb_start; in setup_rcs()
1222 struct drm_i915_private *i915 = engine->i915; in setup_vcs()
1227 engine->set_default_submission = gen6_bsd_set_default_submission; in setup_vcs()
1228 engine->emit_flush = gen6_emit_flush_vcs; in setup_vcs()
1229 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; in setup_vcs()
1232 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; in setup_vcs()
1234 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_vcs()
1236 engine->emit_flush = gen4_emit_flush_vcs; in setup_vcs()
1238 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; in setup_vcs()
1240 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; in setup_vcs()
1246 struct drm_i915_private *i915 = engine->i915; in setup_bcs()
1248 engine->emit_flush = gen6_emit_flush_xcs; in setup_bcs()
1249 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; in setup_bcs()
1252 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; in setup_bcs()
1254 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_bcs()
1259 struct drm_i915_private *i915 = engine->i915; in setup_vecs()
1263 engine->emit_flush = gen6_emit_flush_xcs; in setup_vecs()
1264 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; in setup_vecs()
1265 engine->irq_enable = hsw_irq_enable_vecs; in setup_vecs()
1266 engine->irq_disable = hsw_irq_disable_vecs; in setup_vecs()
1268 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; in setup_vecs()
1295 engine->wa_ctx.vma = vma; in gen7_ctx_switch_bb_init()
1309 if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS) in gen7_ctx_vma()
1320 obj = i915_gem_object_create_internal(engine->i915, size); in gen7_ctx_vma()
1324 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in gen7_ctx_vma()
1330 vma->private = intel_context_create(engine); /* dummy residuals */ in gen7_ctx_vma()
1331 if (IS_ERR(vma->private)) { in gen7_ctx_vma()
1332 err = PTR_ERR(vma->private); in gen7_ctx_vma()
1333 vma->private = NULL; in gen7_ctx_vma()
1351 switch (engine->class) { in intel_ring_submission_setup()
1365 MISSING_CASE(engine->class); in intel_ring_submission_setup()
1366 return -ENODEV; in intel_ring_submission_setup()
1375 GEM_BUG_ON(timeline->has_initial_breadcrumb); in intel_ring_submission_setup()
1383 GEM_BUG_ON(engine->legacy.ring); in intel_ring_submission_setup()
1384 engine->legacy.ring = ring; in intel_ring_submission_setup()
1385 engine->legacy.timeline = timeline; in intel_ring_submission_setup()
1396 err = i915_gem_object_lock(timeline->hwsp_ggtt->obj, &ww); in intel_ring_submission_setup()
1398 err = i915_gem_object_lock(gen7_wa_vma->obj, &ww); in intel_ring_submission_setup()
1400 err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww); in intel_ring_submission_setup()
1411 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); in intel_ring_submission_setup()
1422 if (err == -EDEADLK) { in intel_ring_submission_setup()
1432 engine->release = ring_release; in intel_ring_submission_setup()
1438 intel_context_put(gen7_wa_vma->private); in intel_ring_submission_setup()
1439 i915_gem_object_put(gen7_wa_vma->obj); in intel_ring_submission_setup()