Lines Matching +full:hpd +full:- +full:reliable +full:- +full:delay

53  * Since Haswell Display controller supports Panel Self-Refresh on display
67 * The implementation uses the hardware-based PSR support which automatically
68 * enters/exits self-refresh mode. The hardware takes care of sending the
71 * changes to know when to exit self-refresh mode again. Unfortunately that
76 * issues the self-refresh re-enable code is done from a work queue, which
84 * entry/exit allows the HW to enter a low-power state even when page flipping
100 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
164 * In standby mode (as opposed to link-off) this makes no difference
178 * The rest of the bits are more self-explanatory and/or
198 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
199 (intel_dp)->psr.source_support)
203 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) in intel_encoder_can_psr()
215 * the output is enabled. For non-eDP outputs the main link is always in intel_psr_needs_aux_io_power()
216 * on, hence it doesn't require the HW initiated AUX wake-up signaling used in intel_psr_needs_aux_io_power()
220 * - Consider leaving AUX IO disabled for eDP / PR as well, in case in intel_psr_needs_aux_io_power()
221 * the ALPM with main-link off mode is not enabled. in intel_psr_needs_aux_io_power()
222 * - Leave AUX IO enabled for DP / PR, once support for ALPM with in intel_psr_needs_aux_io_power()
223 * main-link off mode is added for it and this mode gets enabled. in intel_psr_needs_aux_io_power()
232 struct intel_connector *connector = intel_dp->attached_connector; in psr_global_enabled()
234 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr_global_enabled()
236 if (display->params.enable_psr == -1) in psr_global_enabled()
238 connector->panel.vbt.psr.enable : in psr_global_enabled()
240 return display->params.enable_psr; in psr_global_enabled()
252 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr2_global_enabled()
257 if (display->params.enable_psr == 1) in psr2_global_enabled()
267 if (display->params.enable_psr != -1) in psr2_su_region_et_global_enabled()
277 if ((display->params.enable_psr != -1) || in panel_replay_global_enabled()
278 (intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE)) in panel_replay_global_enabled()
288 EDP_PSR_ERROR(intel_dp->psr.transcoder); in psr_irq_psr_error_bit_get()
296 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); in psr_irq_post_exit_bit_get()
304 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); in psr_irq_pre_entry_bit_get()
312 EDP_PSR_MASK(intel_dp->psr.transcoder); in psr_irq_mask_get()
390 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_irq_control()
393 if (intel_dp->psr.panel_replay_enabled) in psr_irq_control()
397 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
408 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); in psr_event_print()
410 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); in psr_event_print()
412 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); in psr_event_print()
414 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); in psr_event_print()
416 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); in psr_event_print()
418 drm_dbg_kms(display->drm, "\tGraphics reset\n"); in psr_event_print()
420 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); in psr_event_print()
422 drm_dbg_kms(display->drm, "\tMemory up\n"); in psr_event_print()
424 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); in psr_event_print()
426 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); in psr_event_print()
428 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); in psr_event_print()
430 drm_dbg_kms(display->drm, "\tRegister updated\n"); in psr_event_print()
432 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); in psr_event_print()
434 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); in psr_event_print()
436 drm_dbg_kms(display->drm, "\tVBI enabled\n"); in psr_event_print()
438 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); in psr_event_print()
440 drm_dbg_kms(display->drm, "\tPSR disabled\n"); in psr_event_print()
446 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_irq_handler()
447 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
451 intel_dp->psr.last_entry_attempt = time_ns; in intel_psr_irq_handler()
452 drm_dbg_kms(display->drm, in intel_psr_irq_handler()
458 intel_dp->psr.last_exit = time_ns; in intel_psr_irq_handler()
459 drm_dbg_kms(display->drm, in intel_psr_irq_handler()
470 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); in intel_psr_irq_handler()
475 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", in intel_psr_irq_handler()
478 intel_dp->psr.irq_aux_error = true; in intel_psr_irq_handler()
491 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in intel_psr_irq_handler()
500 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_get_sink_sync_latency()
504 drm_dbg_kms(display->drm, in intel_dp_get_sink_sync_latency()
513 if (intel_dp->psr.sink_panel_replay_su_support) in intel_dp_get_su_capability()
514 drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_get_su_capability()
518 su_capability = intel_dp->psr_dpcd[1]; in intel_dp_get_su_capability()
526 return intel_dp->psr.sink_panel_replay_su_support ? in intel_dp_get_su_x_granularity_offset()
534 return intel_dp->psr.sink_panel_replay_su_support ? in intel_dp_get_su_y_granularity_offset()
567 r = drm_dp_dpcd_read(&intel_dp->aux, in intel_dp_get_su_granularity()
571 drm_dbg_kms(display->drm, in intel_dp_get_su_granularity()
580 r = drm_dp_dpcd_read(&intel_dp->aux, in intel_dp_get_su_granularity()
584 drm_dbg_kms(display->drm, in intel_dp_get_su_granularity()
592 intel_dp->psr.su_w_granularity = w; in intel_dp_get_su_granularity()
593 intel_dp->psr.su_y_granularity = y; in intel_dp_get_su_granularity()
602 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
603 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); in _panel_replay_init_dpcd()
607 if (!(intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { in _panel_replay_init_dpcd()
608 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
614 intel_dp->psr.sink_panel_replay_support = true; in _panel_replay_init_dpcd()
616 if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT) in _panel_replay_init_dpcd()
617 intel_dp->psr.sink_panel_replay_su_support = true; in _panel_replay_init_dpcd()
619 drm_dbg_kms(display->drm, in _panel_replay_init_dpcd()
621 intel_dp->psr.sink_panel_replay_su_support ? in _panel_replay_init_dpcd()
629 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", in _psr_init_dpcd()
630 intel_dp->psr_dpcd[0]); in _psr_init_dpcd()
632 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { in _psr_init_dpcd()
633 drm_dbg_kms(display->drm, in _psr_init_dpcd()
638 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { in _psr_init_dpcd()
639 drm_dbg_kms(display->drm, in _psr_init_dpcd()
644 intel_dp->psr.sink_support = true; in _psr_init_dpcd()
645 intel_dp->psr.sink_sync_latency = in _psr_init_dpcd()
649 intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { in _psr_init_dpcd()
650 bool y_req = intel_dp->psr_dpcd[1] & in _psr_init_dpcd()
655 * Y-coordinate) can handle Y-coordinates in VSC but we are in _psr_init_dpcd()
661 * Y-coordinate requirement panels we would need to enable in _psr_init_dpcd()
664 intel_dp->psr.sink_psr2_support = y_req && in _psr_init_dpcd()
666 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", in _psr_init_dpcd()
667 intel_dp->psr.sink_psr2_support ? "" : "not "); in _psr_init_dpcd()
673 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, in intel_psr_init_dpcd()
674 sizeof(intel_dp->psr_dpcd)); in intel_psr_init_dpcd()
675 drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, in intel_psr_init_dpcd()
676 &intel_dp->pr_dpcd); in intel_psr_init_dpcd()
678 if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT) in intel_psr_init_dpcd()
681 if (intel_dp->psr_dpcd[0]) in intel_psr_init_dpcd()
684 if (intel_dp->psr.sink_psr2_support || in intel_psr_init_dpcd()
685 intel_dp->psr.sink_panel_replay_su_support) in intel_psr_init_dpcd()
692 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_psr_setup_aux()
693 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_psr_setup_aux()
700 [3] = 1 - 1, in hsw_psr_setup_aux()
709 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); in hsw_psr_setup_aux()
711 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); in hsw_psr_setup_aux()
714 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), in hsw_psr_setup_aux()
732 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) in psr2_su_region_et_valid()
736 intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : in psr2_su_region_et_valid()
737 intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && in psr2_su_region_et_valid()
751 if (crtc_state->has_sel_update) in _panel_replay_enable_sink()
754 if (crtc_state->enable_psr2_su_region_et) in _panel_replay_enable_sink()
757 if (crtc_state->req_psr2_sdp_prior_scanline) in _panel_replay_enable_sink()
761 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); in _panel_replay_enable_sink()
763 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, in _panel_replay_enable_sink()
773 if (crtc_state->has_sel_update) { in _psr_enable_sink()
776 if (intel_dp->psr.link_standby) in _psr_enable_sink()
783 if (crtc_state->req_psr2_sdp_prior_scanline) in _psr_enable_sink()
786 if (crtc_state->enable_psr2_su_region_et) in _psr_enable_sink()
789 if (intel_dp->psr.entry_setup_frames > 0) in _psr_enable_sink()
791 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); in _psr_enable_sink()
794 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); in _psr_enable_sink()
806 if (!intel_dp_is_edp(intel_dp) || (!crtc_state->has_panel_replay && in intel_psr_enable_sink_alpm()
807 !crtc_state->has_sel_update)) in intel_psr_enable_sink_alpm()
812 if (crtc_state->has_panel_replay) in intel_psr_enable_sink_alpm()
815 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); in intel_psr_enable_sink_alpm()
823 crtc_state->has_panel_replay ? in intel_psr_enable_sink()
828 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_enable_sink()
834 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, in intel_psr_panel_replay_enable_sink()
841 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr1_get_tp_time()
842 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr1_get_tp_time()
848 if (display->params.psr_safest_params) { in intel_psr1_get_tp_time()
854 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) in intel_psr1_get_tp_time()
856 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
858 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
863 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
865 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
867 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
877 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && in intel_psr1_get_tp_time()
878 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
883 drm_dp_tps3_supported(intel_dp->dpcd)) in intel_psr1_get_tp_time()
894 struct intel_connector *connector = intel_dp->attached_connector; in psr_compute_idle_frames()
898 * off-by-one issue that HW has in some cases. in psr_compute_idle_frames()
900 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); in psr_compute_idle_frames()
901 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); in psr_compute_idle_frames()
903 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) in psr_compute_idle_frames()
912 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_activate_psr1()
913 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr1()
925 if (intel_dp->psr.link_standby) in hsw_activate_psr1()
934 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); in hsw_activate_psr1()
943 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr2_get_tp_time()
946 if (display->params.psr_safest_params) in intel_psr2_get_tp_time()
949 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && in intel_psr2_get_tp_time()
950 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) in intel_psr2_get_tp_time()
952 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) in intel_psr2_get_tp_time()
954 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) in intel_psr2_get_tp_time()
964 return intel_dp->alpm_parameters.io_wake_lines < 9 && in psr2_block_count_lines()
965 intel_dp->alpm_parameters.fast_wake_lines < 9 ? 8 : 12; in psr2_block_count_lines()
978 intel_dp->psr.sink_sync_latency + 1, in frames_before_su_entry()
982 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) in frames_before_su_entry()
983 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; in frames_before_su_entry()
991 struct intel_psr *psr = &intel_dp->psr; in dg2_activate_panel_replay()
992 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in dg2_activate_panel_replay()
994 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { in dg2_activate_panel_replay()
995 u32 val = psr->su_region_et_enabled ? in dg2_activate_panel_replay()
998 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in dg2_activate_panel_replay()
1006 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), in dg2_activate_panel_replay()
1009 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, in dg2_activate_panel_replay()
1016 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_activate_psr2()
1017 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr2()
1040 /* Wa_22012278275:adl-p */ in hsw_activate_psr2()
1058 tmp = map[intel_dp->alpm_parameters.io_wake_lines - in hsw_activate_psr2()
1062 tmp = map[intel_dp->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; in hsw_activate_psr2()
1065 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); in hsw_activate_psr2()
1067 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); in hsw_activate_psr2()
1068 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines); in hsw_activate_psr2()
1070 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); in hsw_activate_psr2()
1071 val |= EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines); in hsw_activate_psr2()
1074 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in hsw_activate_psr2()
1078 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); in hsw_activate_psr2()
1080 if (intel_dp->psr.psr2_sel_fetch_enabled) { in hsw_activate_psr2()
1085 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); in hsw_activate_psr2()
1091 if (intel_dp->psr.su_region_et_enabled) in hsw_activate_psr2()
1106 struct drm_i915_private *dev_priv = to_i915(display->drm); in transcoder_has_psr2()
1120 if (!crtc_state->hw.active) in intel_get_frame_time_us()
1124 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); in intel_get_frame_time_us()
1131 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr2_program_idle_frames()
1159 mutex_lock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
1161 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) in tgl_dc3co_disable_work()
1166 mutex_unlock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
1171 if (!intel_dp->psr.dc3co_exitline) in tgl_disallow_dc3co_on_psr2_exit()
1174 cancel_delayed_work(&intel_dp->psr.dc3co_work); in tgl_disallow_dc3co_on_psr2_exit()
1185 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in dc3co_is_pipe_port_compatible()
1186 struct drm_i915_private *dev_priv = to_i915(display->drm); in dc3co_is_pipe_port_compatible()
1187 enum port port = dig_port->base.port; in dc3co_is_pipe_port_compatible()
1200 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_dc3co_exitline_compute_config()
1201 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; in tgl_dc3co_exitline_compute_config()
1202 struct i915_power_domains *power_domains = &display->power.domains; in tgl_dc3co_exitline_compute_config()
1216 if (crtc_state->enable_psr2_sel_fetch) in tgl_dc3co_exitline_compute_config()
1219 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) in tgl_dc3co_exitline_compute_config()
1225 /* Wa_16011303918:adl-p */ in tgl_dc3co_exitline_compute_config()
1234 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; in tgl_dc3co_exitline_compute_config()
1236 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) in tgl_dc3co_exitline_compute_config()
1239 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; in tgl_dc3co_exitline_compute_config()
1247 if (!display->params.enable_psr2_sel_fetch && in intel_psr2_sel_fetch_config_valid()
1248 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { in intel_psr2_sel_fetch_config_valid()
1249 drm_dbg_kms(display->drm, in intel_psr2_sel_fetch_config_valid()
1254 if (crtc_state->uapi.async_flip) { in intel_psr2_sel_fetch_config_valid()
1255 drm_dbg_kms(display->drm, in intel_psr2_sel_fetch_config_valid()
1260 return crtc_state->enable_psr2_sel_fetch = true; in intel_psr2_sel_fetch_config_valid()
1267 struct drm_i915_private *dev_priv = to_i915(display->drm); in psr2_granularity_check()
1268 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check()
1269 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in psr2_granularity_check()
1270 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in psr2_granularity_check()
1274 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) in psr2_granularity_check()
1277 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) in psr2_granularity_check()
1281 if (!crtc_state->enable_psr2_sel_fetch) in psr2_granularity_check()
1282 return intel_dp->psr.su_y_granularity == 4; in psr2_granularity_check()
1290 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
1291 else if (intel_dp->psr.su_y_granularity <= 2) in psr2_granularity_check()
1293 else if ((intel_dp->psr.su_y_granularity % 4) == 0) in psr2_granularity_check()
1294 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
1299 if (crtc_state->dsc.compression_enable && in psr2_granularity_check()
1300 vdsc_cfg->slice_height % y_granularity) in psr2_granularity_check()
1303 crtc_state->su_y_granularity = y_granularity; in psr2_granularity_check()
1311 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; in _compute_psr2_sdp_prior_scanline_indication()
1314 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; in _compute_psr2_sdp_prior_scanline_indication()
1315 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); in _compute_psr2_sdp_prior_scanline_indication()
1318 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
1320 if ((hblank_ns - req_ns) > 100) in _compute_psr2_sdp_prior_scanline_indication()
1323 /* Not supported <13 / Wa_22012279113:adl-p */ in _compute_psr2_sdp_prior_scanline_indication()
1324 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) in _compute_psr2_sdp_prior_scanline_indication()
1327 crtc_state->req_psr2_sdp_prior_scanline = true; in _compute_psr2_sdp_prior_scanline_indication()
1335 int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); in intel_psr_entry_setup_frames()
1339 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1341 intel_dp->psr_dpcd[1]); in intel_psr_entry_setup_frames()
1342 return -ETIME; in intel_psr_entry_setup_frames()
1346 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { in intel_psr_entry_setup_frames()
1350 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1354 drm_dbg_kms(display->drm, in intel_psr_entry_setup_frames()
1357 return -ETIME; in intel_psr_entry_setup_frames()
1369 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - in wake_lines_fit_into_vblank()
1370 crtc_state->hw.adjusted_mode.crtc_vblank_start; in wake_lines_fit_into_vblank()
1374 wake_lines = intel_dp->alpm_parameters.aux_less_wake_lines; in wake_lines_fit_into_vblank()
1378 intel_dp->alpm_parameters.io_wake_lines; in wake_lines_fit_into_vblank()
1380 if (crtc_state->req_psr2_sdp_prior_scanline) in wake_lines_fit_into_vblank()
1381 vblank -= 1; in wake_lines_fit_into_vblank()
1397 drm_dbg_kms(display->drm, in alpm_config_valid()
1403 drm_dbg_kms(display->drm, in alpm_config_valid()
1415 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr2_config_valid()
1416 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in intel_psr2_config_valid()
1417 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_psr2_config_valid()
1420 if (!intel_dp->psr.sink_psr2_support) in intel_psr2_config_valid()
1425 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); in intel_psr2_config_valid()
1432 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1438 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1443 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { in intel_psr2_config_valid()
1444 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1446 transcoder_name(crtc_state->cpu_transcoder)); in intel_psr2_config_valid()
1455 if (crtc_state->dsc.compression_enable && in intel_psr2_config_valid()
1457 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1465 max_bpp = crtc_state->pipe_bpp; in intel_psr2_config_valid()
1480 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1481 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1483 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
1487 /* Wa_16011303918:adl-p */ in intel_psr2_config_valid()
1488 if (crtc_state->vrr.enable && in intel_psr2_config_valid()
1490 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1498 if (!crtc_state->enable_psr2_sel_fetch && in intel_psr2_config_valid()
1500 drm_dbg_kms(display->drm, in intel_psr2_config_valid()
1520 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1526 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1531 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) in intel_sel_update_config_valid()
1535 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1540 if (crtc_state->has_panel_replay && (DISPLAY_VER(display) < 14 || in intel_sel_update_config_valid()
1541 !intel_dp->psr.sink_panel_replay_su_support)) in intel_sel_update_config_valid()
1544 if (crtc_state->crc_enabled) { in intel_sel_update_config_valid()
1545 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1551 drm_dbg_kms(display->drm, in intel_sel_update_config_valid()
1556 crtc_state->enable_psr2_su_region_et = in intel_sel_update_config_valid()
1557 psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay); in intel_sel_update_config_valid()
1562 crtc_state->enable_psr2_sel_fetch = false; in intel_sel_update_config_valid()
1570 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in _psr_compute_config()
1579 intel_dp->psr.entry_setup_frames = entry_setup_frames; in _psr_compute_config()
1581 drm_dbg_kms(display->drm, in _psr_compute_config()
1596 to_intel_connector(conn_state->connector); in _panel_replay_compute_config()
1597 struct intel_hdcp *hdcp = &connector->hdcp; in _panel_replay_compute_config()
1603 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); in _panel_replay_compute_config()
1612 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A && in _panel_replay_compute_config()
1613 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) in _panel_replay_compute_config()
1618 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1624 if (conn_state->content_protection == in _panel_replay_compute_config()
1626 (conn_state->content_protection == in _panel_replay_compute_config()
1627 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == in _panel_replay_compute_config()
1629 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1637 if (crtc_state->crc_enabled) { in _panel_replay_compute_config()
1638 drm_dbg_kms(display->drm, in _panel_replay_compute_config()
1651 return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 && in intel_psr_needs_wa_18037818876()
1652 !crtc_state->has_sel_update); in intel_psr_needs_wa_18037818876()
1660 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_psr_compute_config()
1663 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); in intel_psr_compute_config()
1667 if (intel_dp->psr.sink_not_reliable) { in intel_psr_compute_config()
1668 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1669 "PSR sink implementation is not reliable\n"); in intel_psr_compute_config()
1673 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_psr_compute_config()
1674 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1684 if (crtc_state->joiner_pipes) { in intel_psr_compute_config()
1685 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1693 if (crtc_state->vrr.enable) in intel_psr_compute_config()
1696 crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp, in intel_psr_compute_config()
1700 crtc_state->has_psr = crtc_state->has_panel_replay ? true : in intel_psr_compute_config()
1703 if (!crtc_state->has_psr) in intel_psr_compute_config()
1706 crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
1710 crtc_state->has_psr = false; in intel_psr_compute_config()
1711 drm_dbg_kms(display->drm, in intel_psr_compute_config()
1721 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_psr_get_config()
1728 intel_dp = &dig_port->dp; in intel_psr_get_config()
1732 mutex_lock(&intel_dp->psr.lock); in intel_psr_get_config()
1733 if (!intel_dp->psr.enabled) in intel_psr_get_config()
1736 if (intel_dp->psr.panel_replay_enabled) { in intel_psr_get_config()
1737 pipe_config->has_psr = pipe_config->has_panel_replay = true; in intel_psr_get_config()
1743 pipe_config->has_psr = true; in intel_psr_get_config()
1746 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; in intel_psr_get_config()
1747 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_get_config()
1749 if (!intel_dp->psr.sel_update_enabled) in intel_psr_get_config()
1756 pipe_config->enable_psr2_sel_fetch = true; in intel_psr_get_config()
1759 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; in intel_psr_get_config()
1764 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); in intel_psr_get_config()
1767 mutex_unlock(&intel_dp->psr.lock); in intel_psr_get_config()
1773 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_activate()
1775 drm_WARN_ON(display->drm, in intel_psr_activate()
1779 drm_WARN_ON(display->drm, in intel_psr_activate()
1782 drm_WARN_ON(display->drm, intel_dp->psr.active); in intel_psr_activate()
1784 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_activate()
1786 /* psr1, psr2 and panel-replay are mutually exclusive.*/ in intel_psr_activate()
1787 if (intel_dp->psr.panel_replay_enabled) in intel_psr_activate()
1789 else if (intel_dp->psr.sel_update_enabled) in intel_psr_activate()
1794 intel_dp->psr.active = true; in intel_psr_activate()
1805 enum pipe pipe = intel_dp->psr.pipe; in wm_optimization_wa()
1809 if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) in wm_optimization_wa()
1814 crtc_state->hw.adjusted_mode.crtc_vblank_start != in wm_optimization_wa()
1815 crtc_state->hw.adjusted_mode.crtc_vdisplay) in wm_optimization_wa()
1830 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_enable_source()
1831 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_enable_source()
1842 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also in intel_psr_enable_source()
1862 * For some unknown reason on HSW non-ULT (or at least on in intel_psr_enable_source()
1895 if (intel_dp->psr.dc3co_exitline) in intel_psr_enable_source()
1899 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); in intel_psr_enable_source()
1903 intel_dp->psr.psr2_sel_fetch_enabled ? in intel_psr_enable_source()
1915 if (intel_dp->psr.sel_update_enabled) { in intel_psr_enable_source()
1923 * All supported adlp panels have 1-based X granularity, this may in intel_psr_enable_source()
1924 * cause issues if non-supported panels are used. in intel_psr_enable_source()
1926 if (!intel_dp->psr.panel_replay_enabled && in intel_psr_enable_source()
1933 if (!intel_dp->psr.panel_replay_enabled && in intel_psr_enable_source()
1948 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_interrupt_error_check()
1951 if (intel_dp->psr.panel_replay_enabled) in psr_interrupt_error_check()
1965 intel_dp->psr.sink_not_reliable = true; in psr_interrupt_error_check()
1966 drm_dbg_kms(display->drm, in psr_interrupt_error_check()
1982 drm_WARN_ON(display->drm, intel_dp->psr.enabled); in intel_psr_enable_locked()
1984 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; in intel_psr_enable_locked()
1985 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; in intel_psr_enable_locked()
1986 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_enable_locked()
1987 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in intel_psr_enable_locked()
1988 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1991 intel_dp->psr.dc3co_exit_delay = val; in intel_psr_enable_locked()
1992 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; in intel_psr_enable_locked()
1993 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; in intel_psr_enable_locked()
1994 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; in intel_psr_enable_locked()
1995 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_enable_locked()
1996 intel_dp->psr.req_psr2_sdp_prior_scanline = in intel_psr_enable_locked()
1997 crtc_state->req_psr2_sdp_prior_scanline; in intel_psr_enable_locked()
2002 if (intel_dp->psr.panel_replay_enabled) in intel_psr_enable_locked()
2003 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); in intel_psr_enable_locked()
2005 drm_dbg_kms(display->drm, "Enabling PSR%s\n", in intel_psr_enable_locked()
2006 intel_dp->psr.sel_update_enabled ? "2" : "1"); in intel_psr_enable_locked()
2012 * - Selective Update in intel_psr_enable_locked()
2013 * - Region Early Transport in intel_psr_enable_locked()
2014 * - Selective Update Region Scanline Capture in intel_psr_enable_locked()
2015 * - VSC_SDP_CRC in intel_psr_enable_locked()
2016 * - HPD on different Errors in intel_psr_enable_locked()
2017 * - CRC verification in intel_psr_enable_locked()
2023 intel_snps_phy_update_psr_power_state(&dig_port->base, true); in intel_psr_enable_locked()
2026 intel_dp->psr.enabled = true; in intel_psr_enable_locked()
2027 intel_dp->psr.paused = false; in intel_psr_enable_locked()
2036 intel_dp->psr.link_ok = true; in intel_psr_enable_locked()
2044 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_exit()
2047 if (!intel_dp->psr.active) { in intel_psr_exit()
2051 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); in intel_psr_exit()
2056 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); in intel_psr_exit()
2061 if (intel_dp->psr.panel_replay_enabled) { in intel_psr_exit()
2062 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), in intel_psr_exit()
2064 } else if (intel_dp->psr.sel_update_enabled) { in intel_psr_exit()
2071 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); in intel_psr_exit()
2077 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); in intel_psr_exit()
2079 intel_dp->psr.active = false; in intel_psr_exit()
2085 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_wait_exit_locked()
2089 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || in intel_psr_wait_exit_locked()
2090 intel_dp->psr.panel_replay_enabled)) { in intel_psr_wait_exit_locked()
2101 drm_err(display->drm, "Timed out waiting PSR idle state\n"); in intel_psr_wait_exit_locked()
2107 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_disable_locked()
2108 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_disable_locked()
2110 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_disable_locked()
2112 if (!intel_dp->psr.enabled) in intel_psr_disable_locked()
2115 if (intel_dp->psr.panel_replay_enabled) in intel_psr_disable_locked()
2116 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); in intel_psr_disable_locked()
2118 drm_dbg_kms(display->drm, "Disabling PSR%s\n", in intel_psr_disable_locked()
2119 intel_dp->psr.sel_update_enabled ? "2" : "1"); in intel_psr_disable_locked()
2130 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); in intel_psr_disable_locked()
2132 if (intel_dp->psr.sel_update_enabled) { in intel_psr_disable_locked()
2134 if (!intel_dp->psr.panel_replay_enabled && in intel_psr_disable_locked()
2145 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); in intel_psr_disable_locked()
2148 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { in intel_psr_disable_locked()
2159 if (!intel_dp->psr.panel_replay_enabled) { in intel_psr_disable_locked()
2160 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); in intel_psr_disable_locked()
2162 if (intel_dp->psr.sel_update_enabled) in intel_psr_disable_locked()
2163 drm_dp_dpcd_writeb(&intel_dp->aux, in intel_psr_disable_locked()
2167 intel_dp->psr.enabled = false; in intel_psr_disable_locked()
2168 intel_dp->psr.panel_replay_enabled = false; in intel_psr_disable_locked()
2169 intel_dp->psr.sel_update_enabled = false; in intel_psr_disable_locked()
2170 intel_dp->psr.psr2_sel_fetch_enabled = false; in intel_psr_disable_locked()
2171 intel_dp->psr.su_region_et_enabled = false; in intel_psr_disable_locked()
2172 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_disable_locked()
2176 * intel_psr_disable - Disable PSR
2187 if (!old_crtc_state->has_psr) in intel_psr_disable()
2190 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && in intel_psr_disable()
2194 mutex_lock(&intel_dp->psr.lock); in intel_psr_disable()
2198 intel_dp->psr.link_ok = false; in intel_psr_disable()
2200 mutex_unlock(&intel_dp->psr.lock); in intel_psr_disable()
2201 cancel_work_sync(&intel_dp->psr.work); in intel_psr_disable()
2202 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); in intel_psr_disable()
2206 * intel_psr_pause - Pause PSR
2214 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pause()
2219 mutex_lock(&psr->lock); in intel_psr_pause()
2221 if (!psr->enabled) { in intel_psr_pause()
2222 mutex_unlock(&psr->lock); in intel_psr_pause()
2227 drm_WARN_ON(display->drm, psr->paused); in intel_psr_pause()
2231 psr->paused = true; in intel_psr_pause()
2233 mutex_unlock(&psr->lock); in intel_psr_pause()
2235 cancel_work_sync(&psr->work); in intel_psr_pause()
2236 cancel_delayed_work_sync(&psr->dc3co_work); in intel_psr_pause()
2240 * intel_psr_resume - Resume PSR
2247 struct intel_psr *psr = &intel_dp->psr; in intel_psr_resume()
2252 mutex_lock(&psr->lock); in intel_psr_resume()
2254 if (!psr->paused) in intel_psr_resume()
2257 psr->paused = false; in intel_psr_resume()
2261 mutex_unlock(&psr->lock); in intel_psr_resume()
2265 * intel_psr_needs_block_dc_vblank - Check if block dc entry is needed
2271 * user-space is polling for vblank events.
2275 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_psr_needs_block_dc_vblank()
2278 for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { in intel_psr_needs_block_dc_vblank()
2295 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event
2310 if (crtc_state->has_psr) in intel_psr_trigger_frame_change_event()
2312 CURSURFLIVE(display, crtc->pipe), 0); in intel_psr_trigger_frame_change_event()
2317 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_enable_bit_get()
2325 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_single_full_frame_bit_get()
2334 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_partial_frame_bit_get()
2343 struct drm_i915_private *dev_priv = to_i915(display->drm); in man_trk_ctl_continuos_full_frame()
2358 * instead of disabling and re-enabling. in intel_psr_force_update()
2367 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); in intel_psr_force_update()
2374 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_psr2_program_trans_man_trk_ctl()
2375 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_psr2_program_trans_man_trk_ctl()
2378 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_trans_man_trk_ctl()
2381 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr2_program_trans_man_trk_ctl()
2382 crtc_state->uapi.encoder_mask) { in intel_psr2_program_trans_man_trk_ctl()
2386 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr2_program_trans_man_trk_ctl()
2388 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) in intel_psr2_program_trans_man_trk_ctl()
2395 crtc_state->psr2_man_track_ctl); in intel_psr2_program_trans_man_trk_ctl()
2397 if (!crtc_state->enable_psr2_su_region_et) in intel_psr2_program_trans_man_trk_ctl()
2400 intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), in intel_psr2_program_trans_man_trk_ctl()
2401 crtc_state->pipe_srcsz_early_tpt); in intel_psr2_program_trans_man_trk_ctl()
2408 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in psr2_man_trk_ctl_calc()
2409 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in psr2_man_trk_ctl_calc()
2420 if (crtc_state->psr2_su_area.y1 == -1) in psr2_man_trk_ctl_calc()
2424 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); in psr2_man_trk_ctl_calc()
2425 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); in psr2_man_trk_ctl_calc()
2427 drm_WARN_ON(crtc_state->uapi.crtc->dev, in psr2_man_trk_ctl_calc()
2428 crtc_state->psr2_su_area.y1 % 4 || in psr2_man_trk_ctl_calc()
2429 crtc_state->psr2_su_area.y2 % 4); in psr2_man_trk_ctl_calc()
2432 crtc_state->psr2_su_area.y1 / 4 + 1); in psr2_man_trk_ctl_calc()
2434 crtc_state->psr2_su_area.y2 / 4 + 1); in psr2_man_trk_ctl_calc()
2437 crtc_state->psr2_man_track_ctl = val; in psr2_man_trk_ctl_calc()
2445 if (!crtc_state->enable_psr2_su_region_et || full_update) in psr2_pipe_srcsz_early_tpt_calc()
2448 width = drm_rect_width(&crtc_state->psr2_su_area); in psr2_pipe_srcsz_early_tpt_calc()
2449 height = drm_rect_height(&crtc_state->psr2_su_area); in psr2_pipe_srcsz_early_tpt_calc()
2451 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); in psr2_pipe_srcsz_early_tpt_calc()
2461 if (overlap_damage_area->y1 == -1) { in clip_area_update()
2462 overlap_damage_area->y1 = damage_area->y1; in clip_area_update()
2463 overlap_damage_area->y2 = damage_area->y2; in clip_area_update()
2467 if (damage_area->y1 < overlap_damage_area->y1) in clip_area_update()
2468 overlap_damage_area->y1 = damage_area->y1; in clip_area_update()
2470 if (damage_area->y2 > overlap_damage_area->y2) in clip_area_update()
2471 overlap_damage_area->y2 = damage_area->y2; in clip_area_update()
2477 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_sel_fetch_pipe_alignment()
2478 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment()
2482 if (crtc_state->dsc.compression_enable && in intel_psr2_sel_fetch_pipe_alignment()
2484 y_alignment = vdsc_cfg->slice_height; in intel_psr2_sel_fetch_pipe_alignment()
2486 y_alignment = crtc_state->su_y_granularity; in intel_psr2_sel_fetch_pipe_alignment()
2488 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; in intel_psr2_sel_fetch_pipe_alignment()
2489 if (crtc_state->psr2_su_area.y2 % y_alignment) in intel_psr2_sel_fetch_pipe_alignment()
2490 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / in intel_psr2_sel_fetch_pipe_alignment()
2508 if (!crtc_state->enable_psr2_su_region_et) in intel_psr2_sel_fetch_et_alignment()
2514 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) in intel_psr2_sel_fetch_et_alignment()
2517 if (plane->id != PLANE_CURSOR) in intel_psr2_sel_fetch_et_alignment()
2520 if (!new_plane_state->uapi.visible) in intel_psr2_sel_fetch_et_alignment()
2523 inter = crtc_state->psr2_su_area; in intel_psr2_sel_fetch_et_alignment()
2524 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) in intel_psr2_sel_fetch_et_alignment()
2527 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, in intel_psr2_sel_fetch_et_alignment()
2528 &crtc_state->pipe_src); in intel_psr2_sel_fetch_et_alignment()
2544 if (plane_state->uapi.dst.y1 < 0 || in psr2_sel_fetch_plane_state_supported()
2545 plane_state->uapi.dst.x1 < 0 || in psr2_sel_fetch_plane_state_supported()
2546 plane_state->scaler_id >= 0 || in psr2_sel_fetch_plane_state_supported()
2547 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) in psr2_sel_fetch_plane_state_supported()
2562 if (crtc_state->scaler_state.scaler_id >= 0) in psr2_sel_fetch_pipe_state_supported()
2575 if (crtc_state->psr2_su_area.y1 != 0 || in intel_psr_apply_pr_link_on_su_wa()
2576 crtc_state->psr2_su_area.y2 != 0) in intel_psr_apply_pr_link_on_su_wa()
2579 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_psr_apply_pr_link_on_su_wa()
2584 if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) in intel_psr_apply_pr_link_on_su_wa()
2587 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_apply_pr_link_on_su_wa()
2588 crtc_state->uapi.encoder_mask) { in intel_psr_apply_pr_link_on_su_wa()
2592 intel_dp->psr.panel_replay_enabled && in intel_psr_apply_pr_link_on_su_wa()
2593 intel_dp->psr.sel_update_enabled) { in intel_psr_apply_pr_link_on_su_wa()
2594 crtc_state->psr2_su_area.y2++; in intel_psr_apply_pr_link_on_su_wa()
2604 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_psr_apply_su_area_workarounds()
2607 if (!crtc_state->has_panel_replay && in intel_psr_apply_su_area_workarounds()
2610 crtc_state->splitter.enable) in intel_psr_apply_su_area_workarounds()
2611 crtc_state->psr2_su_area.y1 = 0; in intel_psr_apply_su_area_workarounds()
2628 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_sel_fetch_update()
2636 crtc_state->psr2_su_area.x1 = 0; in intel_psr2_sel_fetch_update()
2637 crtc_state->psr2_su_area.y1 = -1; in intel_psr2_sel_fetch_update()
2638 crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2639 crtc_state->psr2_su_area.y2 = -1; in intel_psr2_sel_fetch_update()
2649 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, in intel_psr2_sel_fetch_update()
2652 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) in intel_psr2_sel_fetch_update()
2655 if (!new_plane_state->uapi.visible && in intel_psr2_sel_fetch_update()
2656 !old_plane_state->uapi.visible) in intel_psr2_sel_fetch_update()
2669 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || in intel_psr2_sel_fetch_update()
2670 !drm_rect_equals(&new_plane_state->uapi.dst, in intel_psr2_sel_fetch_update()
2671 &old_plane_state->uapi.dst)) { in intel_psr2_sel_fetch_update()
2672 if (old_plane_state->uapi.visible) { in intel_psr2_sel_fetch_update()
2673 damaged_area.y1 = old_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2674 damaged_area.y2 = old_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2675 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, in intel_psr2_sel_fetch_update()
2676 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2679 if (new_plane_state->uapi.visible) { in intel_psr2_sel_fetch_update()
2680 damaged_area.y1 = new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2681 damaged_area.y2 = new_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2682 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, in intel_psr2_sel_fetch_update()
2683 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2686 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { in intel_psr2_sel_fetch_update()
2688 damaged_area.y1 = new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2689 damaged_area.y2 = new_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2690 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, in intel_psr2_sel_fetch_update()
2691 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2695 src = drm_plane_state_src(&new_plane_state->uapi); in intel_psr2_sel_fetch_update()
2698 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, in intel_psr2_sel_fetch_update()
2699 &new_plane_state->uapi, &damaged_area)) in intel_psr2_sel_fetch_update()
2702 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; in intel_psr2_sel_fetch_update()
2703 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; in intel_psr2_sel_fetch_update()
2704 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; in intel_psr2_sel_fetch_update()
2705 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; in intel_psr2_sel_fetch_update()
2707 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2716 if (crtc_state->psr2_su_area.y1 == -1) { in intel_psr2_sel_fetch_update()
2717 drm_info_once(display->drm, in intel_psr2_sel_fetch_update()
2719 pipe_name(crtc->pipe)); in intel_psr2_sel_fetch_update()
2728 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); in intel_psr2_sel_fetch_update()
2749 struct intel_plane *linked = new_plane_state->planar_linked_plane; in intel_psr2_sel_fetch_update()
2751 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || in intel_psr2_sel_fetch_update()
2752 !new_plane_state->uapi.visible) in intel_psr2_sel_fetch_update()
2755 inter = crtc_state->psr2_su_area; in intel_psr2_sel_fetch_update()
2756 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2757 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { in intel_psr2_sel_fetch_update()
2758 sel_fetch_area->y1 = -1; in intel_psr2_sel_fetch_update()
2759 sel_fetch_area->y2 = -1; in intel_psr2_sel_fetch_update()
2761 * if plane sel fetch was previously enabled -> in intel_psr2_sel_fetch_update()
2764 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) in intel_psr2_sel_fetch_update()
2765 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
2775 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2776 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2777 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2778 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
2792 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2793 linked_sel_fetch_area->y1 = sel_fetch_area->y1; in intel_psr2_sel_fetch_update()
2794 linked_sel_fetch_area->y2 = sel_fetch_area->y2; in intel_psr2_sel_fetch_update()
2795 crtc_state->update_planes |= BIT(linked->id); in intel_psr2_sel_fetch_update()
2801 crtc_state->pipe_srcsz_early_tpt = in intel_psr2_sel_fetch_update()
2810 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_psr_pre_plane_update()
2820 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, in intel_psr_pre_plane_update()
2821 old_crtc_state->uapi.encoder_mask) { in intel_psr_pre_plane_update()
2823 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pre_plane_update()
2825 mutex_lock(&psr->lock); in intel_psr_pre_plane_update()
2827 if (psr->enabled) { in intel_psr_pre_plane_update()
2830 * - PSR disabled in new state in intel_psr_pre_plane_update()
2831 * - All planes will go inactive in intel_psr_pre_plane_update()
2832 * - Changing between PSR versions in intel_psr_pre_plane_update()
2833 * - Region Early Transport changing in intel_psr_pre_plane_update()
2834 * - Display WA #1136: skl, bxt in intel_psr_pre_plane_update()
2837 !new_crtc_state->has_psr || in intel_psr_pre_plane_update()
2838 !new_crtc_state->active_planes || in intel_psr_pre_plane_update()
2839 new_crtc_state->has_sel_update != psr->sel_update_enabled || in intel_psr_pre_plane_update()
2840 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || in intel_psr_pre_plane_update()
2841 new_crtc_state->has_panel_replay != psr->panel_replay_enabled || in intel_psr_pre_plane_update()
2842 (DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled)) in intel_psr_pre_plane_update()
2844 else if (new_crtc_state->wm_level_disabled) in intel_psr_pre_plane_update()
2849 mutex_unlock(&psr->lock); in intel_psr_pre_plane_update()
2861 if (!crtc_state->has_psr) in intel_psr_post_plane_update()
2864 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, in intel_psr_post_plane_update()
2865 crtc_state->uapi.encoder_mask) { in intel_psr_post_plane_update()
2867 struct intel_psr *psr = &intel_dp->psr; in intel_psr_post_plane_update()
2870 mutex_lock(&psr->lock); in intel_psr_post_plane_update()
2872 drm_WARN_ON(display->drm, in intel_psr_post_plane_update()
2873 psr->enabled && !crtc_state->active_planes); in intel_psr_post_plane_update()
2875 keep_disabled |= psr->sink_not_reliable; in intel_psr_post_plane_update()
2876 keep_disabled |= !crtc_state->active_planes; in intel_psr_post_plane_update()
2880 crtc_state->wm_level_disabled; in intel_psr_post_plane_update()
2882 if (!psr->enabled && !keep_disabled) in intel_psr_post_plane_update()
2884 else if (psr->enabled && !crtc_state->wm_level_disabled) in intel_psr_post_plane_update()
2889 if (crtc_state->crc_enabled && psr->enabled) in intel_psr_post_plane_update()
2894 * invalidate -> flip -> flush sequence. in intel_psr_post_plane_update()
2896 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_post_plane_update()
2898 mutex_unlock(&psr->lock); in intel_psr_post_plane_update()
2905 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr2_ready_for_pipe_update_locked()
2920 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr1_ready_for_pipe_update_locked()
2934 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
2945 if (!new_crtc_state->has_psr) in intel_psr_wait_for_idle_locked()
2948 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_wait_for_idle_locked()
2949 new_crtc_state->uapi.encoder_mask) { in intel_psr_wait_for_idle_locked()
2953 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_wait_for_idle_locked()
2955 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) in intel_psr_wait_for_idle_locked()
2958 if (intel_dp->psr.sel_update_enabled) in intel_psr_wait_for_idle_locked()
2964 drm_err(display->drm, in intel_psr_wait_for_idle_locked()
2972 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in __psr_wait_for_idle_locked()
2977 if (!intel_dp->psr.enabled) in __psr_wait_for_idle_locked()
2980 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || in __psr_wait_for_idle_locked()
2981 intel_dp->psr.panel_replay_enabled)) { in __psr_wait_for_idle_locked()
2989 mutex_unlock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2993 drm_err(display->drm, in __psr_wait_for_idle_locked()
2994 "Timed out waiting for PSR Idle for re-enable\n"); in __psr_wait_for_idle_locked()
2997 mutex_lock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2998 return err == 0 && intel_dp->psr.enabled; in __psr_wait_for_idle_locked()
3009 state = drm_atomic_state_alloc(display->drm); in intel_psr_fastset_force()
3011 return -ENOMEM; in intel_psr_fastset_force()
3015 state->acquire_ctx = &ctx; in intel_psr_fastset_force()
3016 to_intel_atomic_state(state)->internal = true; in intel_psr_fastset_force()
3019 drm_connector_list_iter_begin(display->drm, &conn_iter); in intel_psr_fastset_force()
3024 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) in intel_psr_fastset_force()
3033 if (!conn_state->crtc) in intel_psr_fastset_force()
3036 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); in intel_psr_fastset_force()
3042 /* Mark mode as changed to trigger a pipe->update() */ in intel_psr_fastset_force()
3043 crtc_state->mode_changed = true; in intel_psr_fastset_force()
3050 if (err == -EDEADLK) { in intel_psr_fastset_force()
3077 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); in intel_psr_debug_set()
3078 return -EINVAL; in intel_psr_debug_set()
3081 ret = mutex_lock_interruptible(&intel_dp->psr.lock); in intel_psr_debug_set()
3085 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; in intel_psr_debug_set()
3086 old_disable_bits = intel_dp->psr.debug & in intel_psr_debug_set()
3090 intel_dp->psr.debug = val; in intel_psr_debug_set()
3096 if (intel_dp->psr.enabled) in intel_psr_debug_set()
3099 mutex_unlock(&intel_dp->psr.lock); in intel_psr_debug_set()
3109 struct intel_psr *psr = &intel_dp->psr; in intel_psr_handle_irq()
3112 psr->sink_not_reliable = true; in intel_psr_handle_irq()
3114 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_handle_irq()
3122 mutex_lock(&intel_dp->psr.lock); in intel_psr_work()
3124 if (!intel_dp->psr.enabled) in intel_psr_work()
3127 if (READ_ONCE(intel_dp->psr.irq_aux_error)) in intel_psr_work()
3131 * We have to make sure PSR is ready for re-enable in intel_psr_work()
3134 * and be ready for re-enable. in intel_psr_work()
3144 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) in intel_psr_work()
3149 mutex_unlock(&intel_dp->psr.lock); in intel_psr_work()
3155 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_configure_full_frame_update()
3157 if (!intel_dp->psr.psr2_sel_fetch_enabled) in intel_psr_configure_full_frame_update()
3174 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_invalidate_handle()
3175 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_invalidate_handle()
3176 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; in _psr_invalidate_handle()
3187 * intel_psr_invalidate - Invalidate PSR
3207 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_psr_invalidate()
3211 mutex_lock(&intel_dp->psr.lock); in intel_psr_invalidate()
3212 if (!intel_dp->psr.enabled) { in intel_psr_invalidate()
3213 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
3218 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_invalidate()
3219 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; in intel_psr_invalidate()
3224 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
3238 struct drm_i915_private *i915 = to_i915(display->drm); in tgl_dc3co_flush_locked()
3240 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || in tgl_dc3co_flush_locked()
3241 !intel_dp->psr.active) in tgl_dc3co_flush_locked()
3245 * At every frontbuffer flush flip event modified delay of delayed work, in tgl_dc3co_flush_locked()
3249 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) in tgl_dc3co_flush_locked()
3253 mod_delayed_work(i915->unordered_wq, &intel_dp->psr.dc3co_work, in tgl_dc3co_flush_locked()
3254 intel_dp->psr.dc3co_exit_delay); in tgl_dc3co_flush_locked()
3260 struct drm_i915_private *dev_priv = to_i915(display->drm); in _psr_flush_handle()
3262 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_flush_handle()
3263 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_flush_handle()
3265 if (intel_dp->psr.busy_frontbuffer_bits == 0) in _psr_flush_handle()
3266 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in _psr_flush_handle()
3283 if (!intel_dp->psr.psr2_sel_fetch_enabled && !intel_dp->psr.active && in _psr_flush_handle()
3284 !intel_dp->psr.busy_frontbuffer_bits) in _psr_flush_handle()
3285 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in _psr_flush_handle()
3289 * intel_psr_flush - Flush PSR
3306 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_psr_flush()
3310 mutex_lock(&intel_dp->psr.lock); in intel_psr_flush()
3311 if (!intel_dp->psr.enabled) { in intel_psr_flush()
3312 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
3317 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_flush()
3318 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; in intel_psr_flush()
3325 if (intel_dp->psr.paused) in intel_psr_flush()
3330 !intel_dp->psr.psr2_sel_fetch_enabled)) { in intel_psr_flush()
3341 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
3346 * intel_psr_init - Init basic PSR work and mutex.
3356 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr_init()
3371 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { in intel_psr_init()
3372 drm_dbg_kms(display->drm, in intel_psr_init()
3379 intel_dp->psr.source_panel_replay_support = true; in intel_psr_init()
3382 intel_dp->psr.source_support = true; in intel_psr_init()
3387 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; in intel_psr_init()
3389 INIT_WORK(&intel_dp->psr.work, intel_psr_work); in intel_psr_init()
3390 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); in intel_psr_init()
3391 mutex_init(&intel_dp->psr.lock); in intel_psr_init()
3397 struct drm_dp_aux *aux = &intel_dp->aux; in psr_get_status_and_error_status()
3401 offset = intel_dp->psr.panel_replay_enabled ? in psr_get_status_and_error_status()
3408 offset = intel_dp->psr.panel_replay_enabled ? in psr_get_status_and_error_status()
3423 struct drm_dp_aux *aux = &intel_dp->aux; in psr_alpm_check()
3424 struct intel_psr *psr = &intel_dp->psr; in psr_alpm_check()
3428 if (!psr->sel_update_enabled) in psr_alpm_check()
3433 drm_err(display->drm, "Error reading ALPM status\n"); in psr_alpm_check()
3439 psr->sink_not_reliable = true; in psr_alpm_check()
3440 drm_dbg_kms(display->drm, in psr_alpm_check()
3451 struct intel_psr *psr = &intel_dp->psr; in psr_capability_changed_check()
3455 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); in psr_capability_changed_check()
3457 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); in psr_capability_changed_check()
3463 psr->sink_not_reliable = true; in psr_capability_changed_check()
3464 drm_dbg_kms(display->drm, in psr_capability_changed_check()
3468 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); in psr_capability_changed_check()
3482 struct intel_psr *psr = &intel_dp->psr; in intel_psr_short_pulse()
3491 mutex_lock(&psr->lock); in intel_psr_short_pulse()
3493 psr->link_ok = false; in intel_psr_short_pulse()
3495 if (!psr->enabled) in intel_psr_short_pulse()
3499 drm_err(display->drm, in intel_psr_short_pulse()
3504 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || in intel_psr_short_pulse()
3507 psr->sink_not_reliable = true; in intel_psr_short_pulse()
3510 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && in intel_psr_short_pulse()
3512 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3515 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3518 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3521 drm_dbg_kms(display->drm, in intel_psr_short_pulse()
3525 drm_err(display->drm, in intel_psr_short_pulse()
3529 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); in intel_psr_short_pulse()
3531 if (!psr->panel_replay_enabled) { in intel_psr_short_pulse()
3537 mutex_unlock(&psr->lock); in intel_psr_short_pulse()
3547 mutex_lock(&intel_dp->psr.lock); in intel_psr_enabled()
3548 ret = intel_dp->psr.enabled; in intel_psr_enabled()
3549 mutex_unlock(&intel_dp->psr.lock); in intel_psr_enabled()
3555 * intel_psr_link_ok - return psr->link_ok
3558 * We are seeing unexpected link re-trainings with some panels. This is caused
3574 mutex_lock(&intel_dp->psr.lock); in intel_psr_link_ok()
3575 ret = intel_dp->psr.link_ok; in intel_psr_link_ok()
3576 mutex_unlock(&intel_dp->psr.lock); in intel_psr_link_ok()
3582 * intel_psr_lock - grab PSR lock
3594 if (!crtc_state->has_psr) in intel_psr_lock()
3597 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_lock()
3598 crtc_state->uapi.encoder_mask) { in intel_psr_lock()
3601 mutex_lock(&intel_dp->psr.lock); in intel_psr_lock()
3607 * intel_psr_unlock - release PSR lock
3617 if (!crtc_state->has_psr) in intel_psr_unlock()
3620 for_each_intel_encoder_mask_with_psr(display->drm, encoder, in intel_psr_unlock()
3621 crtc_state->uapi.encoder_mask) { in intel_psr_unlock()
3624 mutex_unlock(&intel_dp->psr.lock); in intel_psr_unlock()
3633 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_source_status()
3637 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || in psr_source_status()
3638 intel_dp->psr.panel_replay_enabled)) { in psr_source_status()
3681 struct intel_psr *psr = &intel_dp->psr; in intel_psr_sink_capability()
3684 str_yes_no(psr->sink_support)); in intel_psr_sink_capability()
3686 if (psr->sink_support) in intel_psr_sink_capability()
3687 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); in intel_psr_sink_capability()
3688 if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) in intel_psr_sink_capability()
3690 seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); in intel_psr_sink_capability()
3692 str_yes_no(psr->sink_panel_replay_su_support)); in intel_psr_sink_capability()
3693 if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) in intel_psr_sink_capability()
3701 struct intel_psr *psr = &intel_dp->psr; in intel_psr_print_mode()
3704 if (psr->enabled) in intel_psr_print_mode()
3709 if (psr->panel_replay_enabled && psr->sel_update_enabled) in intel_psr_print_mode()
3711 else if (psr->panel_replay_enabled) in intel_psr_print_mode()
3713 else if (psr->sel_update_enabled) in intel_psr_print_mode()
3715 else if (psr->enabled) in intel_psr_print_mode()
3720 if (psr->su_region_et_enabled) in intel_psr_print_mode()
3731 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_psr_status()
3732 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_status()
3733 struct intel_psr *psr = &intel_dp->psr; in intel_psr_status()
3740 if (!(psr->sink_support || psr->sink_panel_replay_support)) in intel_psr_status()
3743 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_psr_status()
3744 mutex_lock(&psr->lock); in intel_psr_status()
3748 if (!psr->enabled) { in intel_psr_status()
3749 seq_printf(m, "PSR sink not reliable: %s\n", in intel_psr_status()
3750 str_yes_no(psr->sink_not_reliable)); in intel_psr_status()
3755 if (psr->panel_replay_enabled) { in intel_psr_status()
3764 } else if (psr->sel_update_enabled) { in intel_psr_status()
3774 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) in intel_psr_status()
3779 psr->busy_frontbuffer_bits); in intel_psr_status()
3788 if (psr->debug & I915_PSR_DEBUG_IRQ) { in intel_psr_status()
3790 psr->last_entry_attempt); in intel_psr_status()
3791 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); in intel_psr_status()
3794 if (psr->sel_update_enabled) { in intel_psr_status()
3820 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); in intel_psr_status()
3824 mutex_unlock(&psr->lock); in intel_psr_status()
3825 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in intel_psr_status()
3832 struct intel_display *display = m->private; in i915_edp_psr_status_show()
3837 return -ENODEV; in i915_edp_psr_status_show()
3840 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_status_show()
3846 return -ENODEV; in i915_edp_psr_status_show()
3856 struct drm_i915_private *dev_priv = to_i915(display->drm); in i915_edp_psr_debug_set()
3859 int ret = -ENODEV; in i915_edp_psr_debug_set()
3864 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_debug_set()
3867 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); in i915_edp_psr_debug_set()
3869 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in i915_edp_psr_debug_set()
3874 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in i915_edp_psr_debug_set()
3887 return -ENODEV; in i915_edp_psr_debug_get()
3889 for_each_intel_encoder_with_psr(display->drm, encoder) { in i915_edp_psr_debug_get()
3893 *val = READ_ONCE(intel_dp->psr.debug); in i915_edp_psr_debug_get()
3897 return -ENODEV; in i915_edp_psr_debug_get()
3906 struct drm_minor *minor = display->drm->primary; in intel_psr_debugfs_register()
3908 debugfs_create_file("i915_edp_psr_debug", 0644, minor->debugfs_root, in intel_psr_debugfs_register()
3911 debugfs_create_file("i915_edp_psr_status", 0444, minor->debugfs_root, in intel_psr_debugfs_register()
3917 if (intel_dp->psr.panel_replay_enabled) in psr_mode_str()
3918 return "PANEL-REPLAY"; in psr_mode_str()
3919 else if (intel_dp->psr.enabled) in psr_mode_str()
3927 struct intel_connector *connector = m->private; in i915_psr_sink_status_show()
3934 "transition to inactive, capture and display, timing re-sync", in i915_psr_sink_status_show()
3944 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); in i915_psr_sink_status_show()
3945 return -ENODEV; in i915_psr_sink_status_show()
3948 if (connector->base.status != connector_status_connected) in i915_psr_sink_status_show()
3949 return -ENODEV; in i915_psr_sink_status_show()
3984 struct intel_connector *connector = m->private; in i915_psr_status_show()
3994 struct dentry *root = connector->base.debugfs_entry; in intel_psr_connector_debugfs_add()
3996 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && in intel_psr_connector_debugfs_add()
3997 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) in intel_psr_connector_debugfs_add()