60 #define OCMD_TILED_SURFACE	(0x1<<19)
61 #define OCMD_MIRROR_MASK	(0x3<<17)
62 #define OCMD_MIRROR_MODE	(0x3<<17)
63 #define OCMD_MIRROR_HORIZONTAL	(0x1<<17)
64 #define OCMD_MIRROR_VERTICAL	(0x2<<17)
65 #define OCMD_MIRROR_BOTH	(0x3<<17)
66 #define OCMD_BYTEORDER_MASK	(0x3<<14) /* zero for YUYV or FOURCC YUY2 */
67 #define OCMD_UV_SWAP		(0x1<<14) /* YVYU */
68 #define OCMD_Y_SWAP		(0x2<<14) /* UYVY or FOURCC UYVY */
69 #define OCMD_Y_AND_UV_SWAP	(0x3<<14) /* VYUY */
70 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
71 #define OCMD_RGB_888		(0x1<<10) /* not in i965 Intel docs */
72 #define OCMD_RGB_555		(0x2<<10) /* not in i965 Intel docs */
73 #define OCMD_RGB_565		(0x3<<10) /* not in i965 Intel docs */
74 #define OCMD_YUV_422_PACKED	(0x8<<10)
75 #define OCMD_YUV_411_PACKED	(0x9<<10) /* not in i965 Intel docs */
76 #define OCMD_YUV_420_PLANAR	(0xc<<10)
77 #define OCMD_YUV_422_PLANAR	(0xd<<10)
78 #define OCMD_YUV_410_PLANAR	(0xe<<10) /* also 411 */
79 #define OCMD_TVSYNCFLIP_PARITY	(0x1<<9)
80 #define OCMD_TVSYNCFLIP_ENABLE	(0x1<<7)
81 #define OCMD_BUF_TYPE_MASK	(0x1<<5)
82 #define OCMD_BUF_TYPE_FRAME	(0x0<<5)
83 #define OCMD_BUF_TYPE_FIELD	(0x1<<5)
84 #define OCMD_TEST_MODE		(0x1<<4)
85 #define OCMD_BUFFER_SELECT	(0x3<<2)
86 #define OCMD_BUFFER0		(0x0<<2)
87 #define OCMD_BUFFER1		(0x1<<2)
88 #define OCMD_FIELD_SELECT	(0x1<<2)
89 #define OCMD_FIELD0		(0x0<<1)
90 #define OCMD_FIELD1		(0x1<<1)
91 #define OCMD_ENABLE		(0x1<<0)
94 #define OCONF_PIPE_MASK		(0x1<<18)
95 #define OCONF_PIPE_A		(0x0<<18)
96 #define OCONF_PIPE_B		(0x1<<18)
97 #define OCONF_GAMMA2_ENABLE	(0x1<<16)
98 #define OCONF_CSC_MODE_BT601	(0x0<<5)
99 #define OCONF_CSC_MODE_BT709	(0x1<<5)
100 #define OCONF_CSC_BYPASS	(0x1<<4)
101 #define OCONF_CC_OUT_8BIT	(0x1<<3)
102 #define OCONF_TEST_MODE		(0x1<<2)
103 #define OCONF_THREE_LINE_BUFFER	(0x1<<0)
104 #define OCONF_TWO_LINE_BUFFER	(0x0<<0)
107 #define DST_KEY_ENABLE		(0x1<<31)
108 #define CLK_RGB24_MASK		0x0
109 #define CLK_RGB16_MASK		0x070307
110 #define CLK_RGB15_MASK		0x070707
113 	((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2))
115 	((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3))
117 	((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3))
119 	((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0))
122 #define OFC_UPDATE		0x1
161 	u32 RESERVED1; /* 0x6C */
174 	u32 FASTHSCALE; /* 0xA0 */
175 	u32 UVSCALEV; /* 0xA4 */
176 	u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
177 	u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
178 	u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
179 	u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
180 	u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
181 	u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
182 	u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
183 	u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
184 	u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
218 		intel_de_write(display, DSPCLK_GATE_D(display), 0);  in i830_overlay_clock_gating()
225 				 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);  in i830_overlay_clock_gating()
231 				  PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);  in i830_overlay_clock_gating()
356 	return 0;  in intel_overlay_continue()
474 		return 0;  in intel_overlay_release_old_vid()
478 		return 0;  in intel_overlay_release_old_vid()
507 	overlay->old_xscale = 0;  in intel_overlay_reset()
508 	overlay->old_yscale = 0;  in intel_overlay_reset()
572 	if (sw == 0)  in calc_swidthsw()
573 		return 0;  in calc_swidthsw()
579 	[ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
580 	[ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
581 	[ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
582 	[ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
583 	[ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
584 	[ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
585 	[ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
586 	[ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
587 	[ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
588 	[ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
589 	[10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
590 	[11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
591 	[12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
592 	[13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
593 	[14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
594 	[15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
595 	[16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
599 	[ 0] = { 0x3000, 0x1800, 0x1800, },
600 	[ 1] = { 0xb000, 0x18d0, 0x2e60, },
601 	[ 2] = { 0xb000, 0x1990, 0x2ce0, },
602 	[ 3] = { 0xb020, 0x1a68, 0x2b40, },
603 	[ 4] = { 0xb040, 0x1b20, 0x29e0, },
604 	[ 5] = { 0xb060, 0x1bd8, 0x2880, },
605 	[ 6] = { 0xb080, 0x1c88, 0x3e60, },
606 	[ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
607 	[ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
608 	[ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
609 	[10] = { 0xb100, 0x1eb8, 0x3620, },
610 	[11] = { 0xb100, 0x1f18, 0x34a0, },
611 	[12] = { 0xb100, 0x1f68, 0x3360, },
612 	[13] = { 0xb0e0, 0x1fa8, 0x3240, },
613 	[14] = { 0xb0c0, 0x1fe0, 0x3140, },
614 	[15] = { 0xb060, 0x1ff0, 0x30a0, },
615 	[16] = { 0x3000, 0x0800, 0x3000, },
632 #define FRACT_MASK 0xfff  in update_scaling_factors()
656 	  xscale_UV = 0;  in update_scaling_factors()
657 	  yscale_UV = 0;  in update_scaling_factors()
676 		   ((yscale_UV >> FP_SHIFT) << 0)),  in update_scaling_factors()
691 	u32 format = 0;  in update_colorkey()
692 	u32 flags = 0;  in update_colorkey()
782 		vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 0,  in intel_overlay_pin_fb()
814 	if (ret != 0)  in intel_overlay_do_put_image()
830 		u32 oconfig = 0;  in intel_overlay_do_put_image()
839 		oconfig |= pipe == 0 ?  in intel_overlay_do_put_image()
844 		if (ret != 0)  in intel_overlay_do_put_image()
900 	return 0;  in intel_overlay_do_put_image()
919 	if (ret != 0)  in intel_overlay_switch_off()
923 		return 0;  in intel_overlay_switch_off()
926 	if (ret != 0)  in intel_overlay_switch_off()
929 	iowrite32(0, &overlay->regs->OCMD);  in intel_overlay_switch_off()
944 	return 0;  in check_overlay_possible_on_crtc()
992 	return 0;  in check_overlay_dst()
1008 	return 0;  in check_overlay_scaling()
1048 		if (depth < 0)  in check_overlay_src()
1052 		rec->stride_UV = 0;  in check_overlay_src()
1053 		rec->offset_U = 0;  in check_overlay_src()
1054 		rec->offset_V = 0;  in check_overlay_src()
1061 		if (uv_vscale < 0 || uv_hscale < 0)  in check_overlay_src()
1119 	return 0;  in check_overlay_src()
1166 	if (ret != 0)  in intel_overlay_put_image_ioctl()
1171 		if (ret != 0)  in intel_overlay_put_image_ioctl()
1175 		if (ret != 0)  in intel_overlay_put_image_ioctl()
1191 	if (ret != 0)  in intel_overlay_put_image_ioctl()
1209 	if (ret != 0)  in intel_overlay_put_image_ioctl()
1214 	if (ret != 0)  in intel_overlay_put_image_ioctl()
1218 	if (ret != 0)  in intel_overlay_put_image_ioctl()
1224 	return 0;  in intel_overlay_put_image_ioctl()
1236 	iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),  in update_reg_attrs()
1245 	if (gamma1 & 0xff000000 || gamma2 & 0xff000000)  in check_gamma_bounds()
1248 	for (i = 0; i < 3; i++) {  in check_gamma_bounds()
1249 		if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))  in check_gamma_bounds()
1260 	for (i = 0; i < 3; i++) {  in check_gamma5_errata()
1261 		if (((gamma5 >> i*8) & 0xff) == 0x80)  in check_gamma5_errata()
1270 	if (!check_gamma_bounds(0, attrs->gamma0) ||  in check_gamma()
1276 	    !check_gamma_bounds(attrs->gamma5, 0x00ffffff))  in check_gamma()
1282 	return 0;  in check_gamma()
1352 	overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;  in intel_overlay_attrs_ioctl()
1354 	ret = 0;  in intel_overlay_attrs_ioctl()
1376 	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);  in get_registers()
1395 	return 0;  in get_registers()
1422 	overlay->color_key = 0x0101fe;  in intel_overlay_setup()
1429 			 NULL, intel_overlay_last_flip_retire, 0);  in intel_overlay_setup()
1435 	memset_io(overlay->regs, 0, sizeof(struct overlay_registers));  in intel_overlay_setup()
1511 	drm_printf(p, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",  in intel_overlay_snapshot_print()
1513 	drm_printf(p, "  Register file at 0x%08lx:\n", error->base);  in intel_overlay_snapshot_print()
1515 #define P(x) drm_printf(p, "    " #x ": 0x%08x\n", error->regs.x)  in intel_overlay_snapshot_print()