Lines Matching +full:lvds +full:- +full:4 +full:bits

1 /* SPDX-License-Identifier: MIT */
11 /* LVDS port control */
12 #define LVDS		_MMIO(0x61180)  macro
14  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
15  * the DPLL semantics change when the LVDS is assigned to that pipe.
18 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
23 /* LVDS dithering flag on 965/g4x platform */
25 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
29 /* Enable border for unscaled (or aspect-scaled) display */
32  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
50 #define   LVDS_CLKB_POWER_MASK		REG_GENMASK(5, 4)
54  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
55  * setting for whether we are in dual-channel mode.  The B3 pair will