47  * occurrence until the next modeset on a given pipe.
50  * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
62 	enum pipe pipe;  in ivb_can_enable_err_int()  local
66 	for_each_pipe(display, pipe) {  in ivb_can_enable_err_int()
67 		crtc = intel_crtc_for_pipe(display, pipe);  in ivb_can_enable_err_int()
79 	enum pipe pipe;  in cpt_can_enable_serr_int()  local
84 	for_each_pipe(display, pipe) {  in cpt_can_enable_serr_int()
85 		crtc = intel_crtc_for_pipe(display, pipe);  in cpt_can_enable_serr_int()
98 	i915_reg_t reg = PIPESTAT(display, crtc->pipe);  in i9xx_check_fifo_underruns()
106 	enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);  in i9xx_check_fifo_underruns()
110 	trace_intel_cpu_fifo_underrun(display, crtc->pipe);  in i9xx_check_fifo_underruns()
111 	drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));  in i9xx_check_fifo_underruns()
115 					     enum pipe pipe,  in i9xx_set_fifo_underrun_reporting()  argument
119 	i915_reg_t reg = PIPESTAT(display, pipe);  in i9xx_set_fifo_underrun_reporting()
124 		u32 enable_mask = i915_pipestat_enable_mask(display, pipe);  in i9xx_set_fifo_underrun_reporting()
131 			drm_err(display->drm, "pipe %c underrun\n",  in i9xx_set_fifo_underrun_reporting()
132 				pipe_name(pipe));  in i9xx_set_fifo_underrun_reporting()
137 					    enum pipe pipe, bool enable)  in ilk_set_fifo_underrun_reporting()  argument
140 	u32 bit = (pipe == PIPE_A) ?  in ilk_set_fifo_underrun_reporting()
153 	enum pipe pipe = crtc->pipe;  in ivb_check_fifo_underruns()  local
158 	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)  in ivb_check_fifo_underruns()
161 	intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_check_fifo_underruns()
164 	trace_intel_cpu_fifo_underrun(display, pipe);  in ivb_check_fifo_underruns()
165 	drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));  in ivb_check_fifo_underruns()
169 					    enum pipe pipe, bool enable,  in ivb_set_fifo_underrun_reporting()  argument
175 			       ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_set_fifo_underrun_reporting()
185 		    intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {  in ivb_set_fifo_underrun_reporting()
187 				"uncleared fifo underrun on pipe %c\n",  in ivb_set_fifo_underrun_reporting()
188 				pipe_name(pipe));  in ivb_set_fifo_underrun_reporting()
194 					    enum pipe pipe, bool enable)  in bdw_set_fifo_underrun_reporting()  argument
199 		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);  in bdw_set_fifo_underrun_reporting()
201 		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);  in bdw_set_fifo_underrun_reporting()
205 					    enum pipe pch_transcoder,  in ibx_set_fifo_underrun_reporting()
222 	enum pipe pch_transcoder = crtc->pipe;  in cpt_check_pch_fifo_underruns()
240 					    enum pipe pch_transcoder,  in cpt_set_fifo_underrun_reporting()
266 						    enum pipe pipe, bool enable)  in __intel_set_cpu_fifo_underrun_reporting()  argument
269 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);  in __intel_set_cpu_fifo_underrun_reporting()
278 		i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
280 		ilk_set_fifo_underrun_reporting(display, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
282 		ivb_set_fifo_underrun_reporting(display, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
284 		bdw_set_fifo_underrun_reporting(display, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
292  * @pipe: (CPU) pipe to set state for
295  * This function sets the fifo underrun state for @pipe. It is used in the
297  * expected when disabling or enabling the pipe.
299  * Notice that on some platforms disabling underrun reports for one pipe
300  * disables for all due to shared interrupts. Actual reporting is still per-pipe
306 					   enum pipe pipe, bool enable)  in intel_set_cpu_fifo_underrun_reporting()  argument
313 	ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);  in intel_set_cpu_fifo_underrun_reporting()
322  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
334 					   enum pipe pch_transcoder,  in intel_set_pch_fifo_underrun_reporting()
343 	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT  in intel_set_pch_fifo_underrun_reporting()
345 	 * pch transcoder -> pipe lookups from interrupt code simply store the  in intel_set_pch_fifo_underrun_reporting()
372  * @pipe: (CPU) pipe to set state for
379 					 enum pipe pipe)  in intel_cpu_fifo_underrun_irq_handler()  argument
381 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);  in intel_cpu_fifo_underrun_irq_handler()
392 	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {  in intel_cpu_fifo_underrun_irq_handler()
393 		trace_intel_cpu_fifo_underrun(display, pipe);  in intel_cpu_fifo_underrun_irq_handler()
395 		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));  in intel_cpu_fifo_underrun_irq_handler()
404  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
411 					 enum pipe pch_transcoder)  in intel_pch_fifo_underrun_irq_handler()
486 	 * within the crtc. With crtc for pipe A housing the underrun  in intel_init_fifo_underrun_reporting()
487 	 * reporting state for PCH transcoder A, crtc for pipe B housing  in intel_init_fifo_underrun_reporting()
493 	if (intel_has_pch_trancoder(i915, crtc->pipe))  in intel_init_fifo_underrun_reporting()