Lines Matching +full:preemphasis +full:- +full:level
1 // SPDX-License-Identifier: MIT
37 * so pipe->transcoder cast is fine here. in assert_fdi_tx()
86 if (display->platform.ironlake) in assert_fdi_tx_pll_enabled()
124 display->funcs.fdi->fdi_link_train(crtc, crtc_state); in intel_fdi_link_train()
128 * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs
145 if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3) in intel_fdi_add_affected_crtcs()
157 if (!old_crtc_state->fdi_lanes) in intel_fdi_add_affected_crtcs()
161 new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_fdi_add_affected_crtcs()
166 if (!old_crtc_state->fdi_lanes) in intel_fdi_add_affected_crtcs()
177 if (crtc_state->hw.enable && crtc_state->has_pch_encoder) in pipe_required_fdi_lanes()
178 return crtc_state->fdi_lanes; in pipe_required_fdi_lanes()
187 struct drm_atomic_state *state = pipe_config->uapi.state; in ilk_check_fdi_lanes()
193 drm_dbg_kms(display->drm, in ilk_check_fdi_lanes()
195 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
196 if (pipe_config->fdi_lanes > 4) { in ilk_check_fdi_lanes()
197 drm_dbg_kms(display->drm, in ilk_check_fdi_lanes()
199 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
200 return -EINVAL; in ilk_check_fdi_lanes()
203 if (display->platform.haswell || display->platform.broadwell) { in ilk_check_fdi_lanes()
204 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
205 drm_dbg_kms(display->drm, in ilk_check_fdi_lanes()
207 pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
208 return -EINVAL; in ilk_check_fdi_lanes()
222 if (pipe_config->fdi_lanes <= 2) in ilk_check_fdi_lanes()
232 drm_dbg_kms(display->drm, in ilk_check_fdi_lanes()
234 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
235 return -EINVAL; in ilk_check_fdi_lanes()
239 if (pipe_config->fdi_lanes > 2) { in ilk_check_fdi_lanes()
240 drm_dbg_kms(display->drm, in ilk_check_fdi_lanes()
242 pipe_name(pipe), pipe_config->fdi_lanes); in ilk_check_fdi_lanes()
243 return -EINVAL; in ilk_check_fdi_lanes()
253 drm_dbg_kms(display->drm, in ilk_check_fdi_lanes()
258 return -EINVAL; in ilk_check_fdi_lanes()
269 if (display->platform.ironlake) { in intel_fdi_pll_freq_update()
274 display->fdi.pll_freq = (fdi_pll_clk + 2) * 10000; in intel_fdi_pll_freq_update()
275 } else if (display->platform.sandybridge || display->platform.ivybridge) { in intel_fdi_pll_freq_update()
276 display->fdi.pll_freq = 270000; in intel_fdi_pll_freq_update()
281 drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq); in intel_fdi_pll_freq_update()
288 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()
290 return display->fdi.pll_freq; in intel_fdi_link_freq()
294 * intel_fdi_compute_pipe_bpp - compute pipe bpp limited by max link bpp
299 * link bpp will always match the pipe bpp. This is the case for all non-DP
308 int pipe_bpp = min(crtc_state->pipe_bpp, in intel_fdi_compute_pipe_bpp()
309 fxp_q4_to_int(crtc_state->max_link_bpp_x16)); in intel_fdi_compute_pipe_bpp()
316 crtc_state->pipe_bpp = pipe_bpp; in intel_fdi_compute_pipe_bpp()
325 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in ilk_fdi_compute_config()
337 fdi_dotclock = adjusted_mode->crtc_clock; in ilk_fdi_compute_config()
340 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
342 pipe_config->fdi_lanes = lane; in ilk_fdi_compute_config()
344 intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp), in ilk_fdi_compute_config()
348 &pipe_config->fdi_m_n); in ilk_fdi_compute_config()
362 ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config, in intel_fdi_atomic_check_bw()
364 if (ret != -EINVAL) in intel_fdi_atomic_check_bw()
371 return ret ? : -EAGAIN; in intel_fdi_atomic_check_bw()
375 * intel_fdi_atomic_check_link - check all modeset FDI link configuration
385 * - 0 if the configuration is valid
386 * - %-EAGAIN, if the configuration is invalid and @limits got updated
389 * - Other negative error, if the configuration is invalid without a
402 if (!crtc_state->has_pch_encoder || in intel_fdi_atomic_check_link()
404 !crtc_state->hw.enable) in intel_fdi_atomic_check_link()
423 drm_WARN_ON(display->drm, in cpt_set_fdi_bc_bifurcation()
426 drm_WARN_ON(display->drm, in cpt_set_fdi_bc_bifurcation()
434 drm_dbg_kms(display->drm, "%sabling fdi C rx\n", in cpt_set_fdi_bc_bifurcation()
443 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ivb_update_fdi_bc_bifurcation()
445 switch (crtc->pipe) { in ivb_update_fdi_bc_bifurcation()
449 if (crtc_state->fdi_lanes > 2) in ivb_update_fdi_bc_bifurcation()
460 MISSING_CASE(crtc->pipe); in ivb_update_fdi_bc_bifurcation()
467 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_fdi_normal_train()
468 enum pipe pipe = crtc->pipe; in intel_fdi_normal_train()
475 if (display->platform.ivybridge) { in intel_fdi_normal_train()
500 if (display->platform.ivybridge) in intel_fdi_normal_train()
509 enum pipe pipe = crtc->pipe; in ilk_fdi_link_train()
521 assert_transcoder_enabled(display, crtc_state->cpu_transcoder); in ilk_fdi_link_train()
537 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in ilk_fdi_link_train()
560 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); in ilk_fdi_link_train()
563 drm_dbg_kms(display->drm, "FDI train 1 done.\n"); in ilk_fdi_link_train()
569 drm_err(display->drm, "FDI train 1 fail!\n"); in ilk_fdi_link_train()
582 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); in ilk_fdi_link_train()
587 drm_dbg_kms(display->drm, "FDI train 2 done.\n"); in ilk_fdi_link_train()
592 drm_err(display->drm, "FDI train 2 fail!\n"); in ilk_fdi_link_train()
594 drm_dbg_kms(display->drm, "FDI train done\n"); in ilk_fdi_link_train()
610 struct drm_i915_private *dev_priv = to_i915(display->drm); in gen6_fdi_link_train()
611 enum pipe pipe = crtc->pipe; in gen6_fdi_link_train()
637 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in gen6_fdi_link_train()
641 /* SNB-B */ in gen6_fdi_link_train()
671 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); in gen6_fdi_link_train()
675 drm_dbg_kms(display->drm, in gen6_fdi_link_train()
685 drm_err(display->drm, "FDI train 1 fail!\n"); in gen6_fdi_link_train()
692 if (display->platform.sandybridge) { in gen6_fdi_link_train()
694 /* SNB-B */ in gen6_fdi_link_train()
722 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); in gen6_fdi_link_train()
726 drm_dbg_kms(display->drm, in gen6_fdi_link_train()
736 drm_err(display->drm, "FDI train 2 fail!\n"); in gen6_fdi_link_train()
738 drm_dbg_kms(display->drm, "FDI train done.\n"); in gen6_fdi_link_train()
746 enum pipe pipe = crtc->pipe; in ivb_manual_fdi_link_train()
770 drm_dbg_kms(display->drm, "FDI_RX_IIR before link train 0x%x\n", in ivb_manual_fdi_link_train()
773 /* Try each vswing and preemphasis setting twice before moving on */ in ivb_manual_fdi_link_train()
793 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in ivb_manual_fdi_link_train()
815 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); in ivb_manual_fdi_link_train()
821 drm_dbg_kms(display->drm, in ivb_manual_fdi_link_train()
822 "FDI train 1 done, level %i.\n", in ivb_manual_fdi_link_train()
829 drm_dbg_kms(display->drm, in ivb_manual_fdi_link_train()
847 drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); in ivb_manual_fdi_link_train()
853 drm_dbg_kms(display->drm, in ivb_manual_fdi_link_train()
854 "FDI train 2 done, level %i.\n", in ivb_manual_fdi_link_train()
861 drm_dbg_kms(display->drm, in ivb_manual_fdi_link_train()
866 drm_dbg_kms(display->drm, "FDI train done.\n"); in ivb_manual_fdi_link_train()
870 * connection to the PCH-located connectors. For this, it is necessary to train
884 encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_fdi_link_train()
890 * - TP1 to TP2 time with the default value in hsw_fdi_link_train()
891 * - FDI delay to 90h in hsw_fdi_link_train()
902 rx_ctl_val = display->fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | in hsw_fdi_link_train()
904 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in hsw_fdi_link_train()
914 drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); in hsw_fdi_link_train()
920 /* Configure DP_TP_CTL with auto-training */ in hsw_fdi_link_train()
933 ((crtc_state->fdi_lanes - 1) << 1) | in hsw_fdi_link_train()
942 /* Enable PCH FDI Receiver with auto-training */ in hsw_fdi_link_train()
960 drm_dbg_kms(display->drm, in hsw_fdi_link_train()
969 if (i == n_entries * 2 - 1) { in hsw_fdi_link_train()
970 drm_err(display->drm, "FDI link training failed!\n"); in hsw_fdi_link_train()
1026 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_fdi_pll_enable()
1027 enum pipe pipe = crtc->pipe; in ilk_fdi_pll_enable()
1035 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in ilk_fdi_pll_enable()
1061 enum pipe pipe = crtc->pipe; in ilk_fdi_pll_disable()
1080 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_fdi_disable()
1081 enum pipe pipe = crtc->pipe; in ilk_fdi_disable()
1140 if (display->platform.ironlake) { in intel_fdi_init_hook()
1141 display->funcs.fdi = &ilk_funcs; in intel_fdi_init_hook()
1142 } else if (display->platform.sandybridge) { in intel_fdi_init_hook()
1143 display->funcs.fdi = &gen6_funcs; in intel_fdi_init_hook()
1144 } else if (display->platform.ivybridge) { in intel_fdi_init_hook()
1146 display->funcs.fdi = &ivb_funcs; in intel_fdi_init_hook()