Lines Matching full:dpll

34 	for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
35 		     ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
47  * enum intel_dpll_id - possible DPLL ids
49  * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
53 	 * @DPLL_ID_PRIVATE: non-shared dpll in use
58 	 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
62 	 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
184 	u32 dpll;  member
197 	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
200 	 * the DPLL.
283  * struct intel_shared_dpll_state - hold the DPLL atomic state
285  * This structure holds an atomic state for the DPLL, that can represent
294 	 * @pipe_mask: mask of pipes using this DPLL, active or not
299 	 * @hw_state: hardware configuration for the DPLL stored in
310 	 * @name: DPLL name; used for logging
320 	 * @id: unique identifier for this DPLL
325 	 * @power_domain: extra power domain required by the DPLL
332 	 * Inform the state checker that the DPLL is kept enabled even if
340 	 * Inform the state checker that the DPLL can be used as a fallback
364 	 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
380 	 * need to be grabbed to disable DC states while this DPLL is enabled
390 /* shared dpll functions */