Lines Matching +full:ssc +full:- +full:internal
2 * Copyright © 2006-2016 Intel Corporation
47 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
129 shared_dpll[pll->index] = pll->state; in intel_atomic_duplicate_dpll_state()
138 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
140 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
141 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
144 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
147 return state->shared_dpll; in intel_atomic_get_shared_dpll_state()
151 * intel_get_shared_dpll_by_id - get a DPLL given its id
166 if (pll->info->id == id) in intel_get_shared_dpll_by_id()
182 if (drm_WARN(display->drm, !pll, in assert_shared_dpll()
189 pll->info->name, str_on_off(state), in assert_shared_dpll()
195 return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1; in icl_pll_id_to_tc_port()
200 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1; in icl_tc_port_to_pll_id()
207 if (display->platform.dg1) in intel_combo_pll_enable_reg()
208 return DG1_DPLL_ENABLE(pll->info->id); in intel_combo_pll_enable_reg()
209 else if ((display->platform.jasperlake || display->platform.elkhartlake) && in intel_combo_pll_enable_reg()
210 (pll->info->id == DPLL_ID_EHL_DPLL4)) in intel_combo_pll_enable_reg()
213 return ICL_DPLL_ENABLE(pll->info->id); in intel_combo_pll_enable_reg()
220 const enum intel_dpll_id id = pll->info->id; in intel_tc_pll_enable_reg()
223 if (display->platform.alderlake_p) in intel_tc_pll_enable_reg()
232 if (pll->info->power_domain) in _intel_enable_shared_dpll()
233 pll->wakeref = intel_display_power_get(display, pll->info->power_domain); in _intel_enable_shared_dpll()
235 pll->info->funcs->enable(display, pll, &pll->state.hw_state); in _intel_enable_shared_dpll()
236 pll->on = true; in _intel_enable_shared_dpll()
242 pll->info->funcs->disable(display, pll); in _intel_disable_shared_dpll()
243 pll->on = false; in _intel_disable_shared_dpll()
245 if (pll->info->power_domain) in _intel_disable_shared_dpll()
246 intel_display_power_put(display, pll->info->power_domain, pll->wakeref); in _intel_disable_shared_dpll()
250 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
258 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_enable_shared_dpll()
259 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll()
260 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll()
263 if (drm_WARN_ON(display->drm, !pll)) in intel_enable_shared_dpll()
266 mutex_lock(&display->dpll.lock); in intel_enable_shared_dpll()
267 old_mask = pll->active_mask; in intel_enable_shared_dpll()
269 if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
270 drm_WARN_ON(display->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
273 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
275 drm_dbg_kms(display->drm, in intel_enable_shared_dpll()
277 pll->info->name, pll->active_mask, pll->on, in intel_enable_shared_dpll()
278 crtc->base.base.id, crtc->base.name); in intel_enable_shared_dpll()
281 drm_WARN_ON(display->drm, !pll->on); in intel_enable_shared_dpll()
285 drm_WARN_ON(display->drm, pll->on); in intel_enable_shared_dpll()
287 drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name); in intel_enable_shared_dpll()
292 mutex_unlock(&display->dpll.lock); in intel_enable_shared_dpll()
296 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_disable_shared_dpll()
305 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll()
306 unsigned int pipe_mask = BIT(crtc->pipe); in intel_disable_shared_dpll()
315 mutex_lock(&display->dpll.lock); in intel_disable_shared_dpll()
316 if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
317 "%s not used by [CRTC:%d:%s]\n", pll->info->name, in intel_disable_shared_dpll()
318 crtc->base.base.id, crtc->base.name)) in intel_disable_shared_dpll()
321 drm_dbg_kms(display->drm, in intel_disable_shared_dpll()
323 pll->info->name, pll->active_mask, pll->on, in intel_disable_shared_dpll()
324 crtc->base.base.id, crtc->base.name); in intel_disable_shared_dpll()
327 drm_WARN_ON(display->drm, !pll->on); in intel_disable_shared_dpll()
329 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
330 if (pll->active_mask) in intel_disable_shared_dpll()
333 drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name); in intel_disable_shared_dpll()
338 mutex_unlock(&display->dpll.lock); in intel_disable_shared_dpll()
349 drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id)); in intel_dpll_mask_all()
351 dpll_mask |= BIT(pll->info->id); in intel_dpll_mask_all()
369 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_find_shared_dpll()
371 drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all); in intel_find_shared_dpll()
381 if (shared_dpll[pll->index].pipe_mask == 0) { in intel_find_shared_dpll()
388 &shared_dpll[pll->index].hw_state, in intel_find_shared_dpll()
390 drm_dbg_kms(display->drm, in intel_find_shared_dpll()
392 crtc->base.base.id, crtc->base.name, in intel_find_shared_dpll()
393 pll->info->name, in intel_find_shared_dpll()
394 shared_dpll[pll->index].pipe_mask, in intel_find_shared_dpll()
395 pll->active_mask); in intel_find_shared_dpll()
402 drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n", in intel_find_shared_dpll()
403 crtc->base.base.id, crtc->base.name, in intel_find_shared_dpll()
404 unused_pll->info->name); in intel_find_shared_dpll()
412 * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
426 drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); in intel_reference_shared_dpll_crtc()
428 shared_dpll_state->pipe_mask |= BIT(crtc->pipe); in intel_reference_shared_dpll_crtc()
430 drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n", in intel_reference_shared_dpll_crtc()
431 crtc->base.base.id, crtc->base.name, pll->info->name); in intel_reference_shared_dpll_crtc()
442 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_reference_shared_dpll()
444 if (shared_dpll[pll->index].pipe_mask == 0) in intel_reference_shared_dpll()
445 shared_dpll[pll->index].hw_state = *dpll_hw_state; in intel_reference_shared_dpll()
447 intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); in intel_reference_shared_dpll()
451 * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
465 drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); in intel_unreference_shared_dpll_crtc()
467 shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe); in intel_unreference_shared_dpll_crtc()
469 drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n", in intel_unreference_shared_dpll_crtc()
470 crtc->base.base.id, crtc->base.name, pll->info->name); in intel_unreference_shared_dpll_crtc()
479 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_unreference_shared_dpll()
481 intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); in intel_unreference_shared_dpll()
492 new_crtc_state->shared_dpll = NULL; in intel_put_dpll()
494 if (!old_crtc_state->shared_dpll) in intel_put_dpll()
497 intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll); in intel_put_dpll()
501 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
505 * helper does not handle driver-specific global state.
514 struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; in intel_shared_dpll_swap_state()
518 if (!state->dpll_set) in intel_shared_dpll_swap_state()
522 swap(pll->state, shared_dpll[pll->index]); in intel_shared_dpll_swap_state()
529 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in ibx_pch_dpll_get_hw_state()
530 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_get_hw_state()
540 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
541 hw_state->fp0 = intel_de_read(display, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
542 hw_state->fp1 = intel_de_read(display, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
565 const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in ibx_pch_dpll_enable()
566 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_enable()
571 intel_de_write(display, PCH_FP0(id), hw_state->fp0); in ibx_pch_dpll_enable()
572 intel_de_write(display, PCH_FP1(id), hw_state->fp1); in ibx_pch_dpll_enable()
574 intel_de_write(display, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
585 intel_de_write(display, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
593 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_disable()
612 struct drm_i915_private *i915 = to_i915(display->drm); in ibx_get_dpll()
619 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ in ibx_get_dpll()
620 id = (enum intel_dpll_id) crtc->pipe; in ibx_get_dpll()
623 drm_dbg_kms(display->drm, in ibx_get_dpll()
624 "[CRTC:%d:%s] using pre-allocated %s\n", in ibx_get_dpll()
625 crtc->base.base.id, crtc->base.name, in ibx_get_dpll()
626 pll->info->name); in ibx_get_dpll()
629 &crtc_state->dpll_hw_state, in ibx_get_dpll()
635 return -EINVAL; in ibx_get_dpll()
639 pll, &crtc_state->dpll_hw_state); in ibx_get_dpll()
641 crtc_state->shared_dpll = pll; in ibx_get_dpll()
649 const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in ibx_dump_hw_state()
653 hw_state->dpll, in ibx_dump_hw_state()
654 hw_state->dpll_md, in ibx_dump_hw_state()
655 hw_state->fp0, in ibx_dump_hw_state()
656 hw_state->fp1); in ibx_dump_hw_state()
662 const struct i9xx_dpll_hw_state *a = &_a->i9xx; in ibx_compare_hw_state()
663 const struct i9xx_dpll_hw_state *b = &_b->i9xx; in ibx_compare_hw_state()
665 return a->dpll == b->dpll && in ibx_compare_hw_state()
666 a->dpll_md == b->dpll_md && in ibx_compare_hw_state()
667 a->fp0 == b->fp0 && in ibx_compare_hw_state()
668 a->fp1 == b->fp1; in ibx_compare_hw_state()
696 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_wrpll_enable()
697 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_enable()
699 intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll); in hsw_ddi_wrpll_enable()
708 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_spll_enable()
710 intel_de_write(display, SPLL_CTL, hw_state->spll); in hsw_ddi_spll_enable()
718 struct drm_i915_private *i915 = to_i915(display->drm); in hsw_ddi_wrpll_disable()
719 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_disable()
728 if (display->dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
735 struct drm_i915_private *i915 = to_i915(display->drm); in hsw_ddi_spll_disable()
736 enum intel_dpll_id id = pll->info->id; in hsw_ddi_spll_disable()
745 if (display->dpll.pch_ssc_use & BIT(id)) in hsw_ddi_spll_disable()
753 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_wrpll_get_hw_state()
754 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_get_hw_state()
764 hw_state->wrpll = val; in hsw_ddi_wrpll_get_hw_state()
775 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_spll_get_hw_state()
785 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
881 if (best->p == 0) { in hsw_wrpll_update_rnp()
882 best->p = p; in hsw_wrpll_update_rnp()
883 best->n2 = n2; in hsw_wrpll_update_rnp()
884 best->r2 = r2; in hsw_wrpll_update_rnp()
893 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / in hsw_wrpll_update_rnp()
898 * If the discrepancy is above the PPM-based budget, always prefer to in hsw_wrpll_update_rnp()
903 b = freq2k * budget * best->p * best->r2; in hsw_wrpll_update_rnp()
905 diff_best = abs_diff(freq2k * best->p * best->r2, in hsw_wrpll_update_rnp()
906 LC_FREQ_2K * best->n2); in hsw_wrpll_update_rnp()
912 if (best->p * best->r2 * diff < p * r2 * diff_best) { in hsw_wrpll_update_rnp()
913 best->p = p; in hsw_wrpll_update_rnp()
914 best->n2 = n2; in hsw_wrpll_update_rnp()
915 best->r2 = r2; in hsw_wrpll_update_rnp()
919 best->p = p; in hsw_wrpll_update_rnp()
920 best->n2 = n2; in hsw_wrpll_update_rnp()
921 best->r2 = r2; in hsw_wrpll_update_rnp()
924 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { in hsw_wrpll_update_rnp()
925 best->p = p; in hsw_wrpll_update_rnp()
926 best->n2 = n2; in hsw_wrpll_update_rnp()
927 best->r2 = r2; in hsw_wrpll_update_rnp()
1002 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_wrpll_get_freq()
1005 u32 wrpll = hw_state->wrpll; in hsw_ddi_wrpll_get_freq()
1009 /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */ in hsw_ddi_wrpll_get_freq()
1010 if (display->platform.haswell && !display->platform.haswell_ult) { in hsw_ddi_wrpll_get_freq()
1011 refclk = display->dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
1021 refclk = display->dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1046 struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; in hsw_ddi_wrpll_compute_dpll()
1049 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_compute_dpll()
1051 hw_state->wrpll = in hsw_ddi_wrpll_compute_dpll()
1056 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL, in hsw_ddi_wrpll_compute_dpll()
1057 &crtc_state->dpll_hw_state); in hsw_ddi_wrpll_compute_dpll()
1070 &crtc_state->dpll_hw_state, in hsw_ddi_wrpll_get_dpll()
1079 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1087 drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n", in hsw_ddi_lcpll_compute_dpll()
1089 return -EINVAL; in hsw_ddi_lcpll_compute_dpll()
1099 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1130 switch (pll->info->id) { in hsw_ddi_lcpll_get_freq()
1141 drm_WARN(display->drm, 1, "bad port clock sel\n"); in hsw_ddi_lcpll_get_freq()
1154 struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; in hsw_ddi_spll_compute_dpll()
1156 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_compute_dpll()
1157 return -EINVAL; in hsw_ddi_spll_compute_dpll()
1159 hw_state->spll = in hsw_ddi_spll_compute_dpll()
1172 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, in hsw_ddi_spll_get_dpll()
1180 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_spll_get_freq()
1183 switch (hw_state->spll & SPLL_FREQ_MASK) { in hsw_ddi_spll_get_freq()
1194 drm_WARN(display->drm, 1, "bad spll freq\n"); in hsw_ddi_spll_get_freq()
1215 return -EINVAL; in hsw_compute_dpll()
1234 return -EINVAL; in hsw_get_dpll()
1237 pll, &crtc_state->dpll_hw_state); in hsw_get_dpll()
1239 crtc_state->shared_dpll = pll; in hsw_get_dpll()
1246 display->dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1247 /* Non-SSC is only used on non-ULT HSW. */ in hsw_update_dpll_ref_clks()
1249 display->dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1251 display->dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1257 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_dump_hw_state()
1260 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()
1266 const struct hsw_dpll_hw_state *a = &_a->hsw; in hsw_compare_hw_state()
1267 const struct hsw_dpll_hw_state *b = &_b->hsw; in hsw_compare_hw_state()
1269 return a->wrpll == b->wrpll && in hsw_compare_hw_state()
1270 a->spll == b->spll; in hsw_compare_hw_state()
1370 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_write_ctrl1()
1376 hw_state->ctrl1 << (id * 6)); in skl_ddi_pll_write_ctrl1()
1384 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_enable()
1386 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_enable()
1390 intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1); in skl_ddi_pll_enable()
1391 intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2); in skl_ddi_pll_enable()
1399 drm_err(display->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1406 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_enable()
1415 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_disable()
1431 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_hw_state()
1433 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_get_hw_state()
1450 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()
1454 hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1455 hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1469 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_get_hw_state()
1471 const enum intel_dpll_id id = pll->info->id; in skl_ddi_dpll0_get_hw_state()
1485 if (drm_WARN_ON(display->drm, !(val & LCPLL_PLL_ENABLE))) in skl_ddi_dpll0_get_hw_state()
1489 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()
1506 /* DCO freq must be within +1%/-6% of the DCO central freq */
1523 deviation < ctx->min_deviation) { in skl_wrpll_try_divider()
1524 ctx->min_deviation = deviation; in skl_wrpll_try_divider()
1525 ctx->central_freq = central_freq; in skl_wrpll_try_divider()
1526 ctx->dco_freq = dco_freq; in skl_wrpll_try_divider()
1527 ctx->p = divider; in skl_wrpll_try_divider()
1531 deviation < ctx->min_deviation) { in skl_wrpll_try_divider()
1532 ctx->min_deviation = deviation; in skl_wrpll_try_divider()
1533 ctx->central_freq = central_freq; in skl_wrpll_try_divider()
1534 ctx->dco_freq = dco_freq; in skl_wrpll_try_divider()
1535 ctx->p = divider; in skl_wrpll_try_divider()
1608 params->central_freq = 0; in skl_wrpll_params_populate()
1611 params->central_freq = 1; in skl_wrpll_params_populate()
1614 params->central_freq = 3; in skl_wrpll_params_populate()
1619 params->pdiv = 0; in skl_wrpll_params_populate()
1622 params->pdiv = 1; in skl_wrpll_params_populate()
1625 params->pdiv = 2; in skl_wrpll_params_populate()
1628 params->pdiv = 4; in skl_wrpll_params_populate()
1636 params->kdiv = 0; in skl_wrpll_params_populate()
1639 params->kdiv = 1; in skl_wrpll_params_populate()
1642 params->kdiv = 2; in skl_wrpll_params_populate()
1645 params->kdiv = 3; in skl_wrpll_params_populate()
1651 params->qdiv_ratio = p1; in skl_wrpll_params_populate()
1652 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; in skl_wrpll_params_populate()
1660 params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1)); in skl_wrpll_params_populate()
1661 params->dco_fraction = in skl_wrpll_params_populate()
1662 div_u64((div_u64(dco_freq, ref_clock / KHz(1)) - in skl_wrpll_params_populate()
1663 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); in skl_wrpll_params_populate()
1724 return -EINVAL; in skl_ddi_calculate_wrpll()
1742 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_wrpll_get_freq()
1743 int ref_clock = display->dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1746 p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; in skl_ddi_wrpll_get_freq()
1747 p2 = hw_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; in skl_ddi_wrpll_get_freq()
1749 if (hw_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) in skl_ddi_wrpll_get_freq()
1750 p1 = (hw_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; in skl_ddi_wrpll_get_freq()
1767 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0, in skl_ddi_wrpll_get_freq()
1770 drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); in skl_ddi_wrpll_get_freq()
1798 dco_freq = (hw_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) * in skl_ddi_wrpll_get_freq()
1801 dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * in skl_ddi_wrpll_get_freq()
1804 if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0)) in skl_ddi_wrpll_get_freq()
1813 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; in skl_ddi_hdmi_pll_dividers()
1817 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock, in skl_ddi_hdmi_pll_dividers()
1818 display->dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1826 hw_state->ctrl1 = in skl_ddi_hdmi_pll_dividers()
1830 hw_state->cfgcr1 = in skl_ddi_hdmi_pll_dividers()
1835 hw_state->cfgcr2 = in skl_ddi_hdmi_pll_dividers()
1842 crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL, in skl_ddi_hdmi_pll_dividers()
1843 &crtc_state->dpll_hw_state); in skl_ddi_hdmi_pll_dividers()
1851 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; in skl_ddi_dp_set_dpll_hw_state()
1859 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
1881 hw_state->ctrl1 = ctrl1; in skl_ddi_dp_set_dpll_hw_state()
1890 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_lcpll_get_freq()
1893 switch ((hw_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >> in skl_ddi_lcpll_get_freq()
1914 drm_WARN(display->drm, 1, "Unsupported link rate\n"); in skl_ddi_lcpll_get_freq()
1933 return -EINVAL; in skl_compute_dpll()
1946 &crtc_state->dpll_hw_state, in skl_get_dpll()
1950 &crtc_state->dpll_hw_state, in skl_get_dpll()
1955 return -EINVAL; in skl_get_dpll()
1958 pll, &crtc_state->dpll_hw_state); in skl_get_dpll()
1960 crtc_state->shared_dpll = pll; in skl_get_dpll()
1969 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_freq()
1973 * the internal shift for each field in skl_ddi_pll_get_freq()
1975 if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) in skl_ddi_pll_get_freq()
1983 /* No SSC ref */ in skl_update_dpll_ref_clks()
1984 display->dpll.ref_clks.nssc = display->cdclk.hw.ref; in skl_update_dpll_ref_clks()
1990 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_dump_hw_state()
1993 hw_state->ctrl1, hw_state->cfgcr1, hw_state->cfgcr2); in skl_dump_hw_state()
1999 const struct skl_dpll_hw_state *a = &_a->skl; in skl_compare_hw_state()
2000 const struct skl_dpll_hw_state *b = &_b->skl; in skl_compare_hw_state()
2002 return a->ctrl1 == b->ctrl1 && in skl_compare_hw_state()
2003 a->cfgcr1 == b->cfgcr1 && in skl_compare_hw_state()
2004 a->cfgcr2 == b->cfgcr2; in skl_compare_hw_state()
2044 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; in bxt_ddi_pll_enable()
2045 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_enable()
2052 /* Non-SSC reference */ in bxt_ddi_pll_enable()
2055 if (display->platform.geminilake) { in bxt_ddi_pll_enable()
2061 drm_err(display->drm, in bxt_ddi_pll_enable()
2071 PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0); in bxt_ddi_pll_enable()
2075 PORT_PLL_M2_INT_MASK, hw_state->pll0); in bxt_ddi_pll_enable()
2079 PORT_PLL_N_MASK, hw_state->pll1); in bxt_ddi_pll_enable()
2083 PORT_PLL_M2_FRAC_MASK, hw_state->pll2); in bxt_ddi_pll_enable()
2087 PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3); in bxt_ddi_pll_enable()
2094 temp |= hw_state->pll6; in bxt_ddi_pll_enable()
2099 PORT_PLL_TARGET_CNT_MASK, hw_state->pll8); in bxt_ddi_pll_enable()
2102 PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9); in bxt_ddi_pll_enable()
2107 temp |= hw_state->pll10; in bxt_ddi_pll_enable()
2115 temp |= hw_state->ebb4; in bxt_ddi_pll_enable()
2124 drm_err(display->drm, "PLL %d not locked\n", port); in bxt_ddi_pll_enable()
2126 if (display->platform.geminilake) { in bxt_ddi_pll_enable()
2139 temp |= hw_state->pcsdw12; in bxt_ddi_pll_enable()
2146 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_disable()
2151 if (display->platform.geminilake) { in bxt_ddi_pll_disable()
2157 drm_err(display->drm, in bxt_ddi_pll_disable()
2166 struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; in bxt_ddi_pll_get_hw_state()
2167 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_get_hw_state()
2187 hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch)); in bxt_ddi_pll_get_hw_state()
2188 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; in bxt_ddi_pll_get_hw_state()
2190 hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_get_hw_state()
2191 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_pll_get_hw_state()
2193 hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2194 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()
2196 hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2197 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
2199 hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2200 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
2202 hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2203 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
2205 hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2206 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | in bxt_ddi_pll_get_hw_state()
2210 hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2211 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; in bxt_ddi_pll_get_hw_state()
2213 hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2214 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2216 hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_get_hw_state()
2217 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | in bxt_ddi_pll_get_hw_state()
2225 hw_state->pcsdw12 = intel_de_read(display, in bxt_ddi_pll_get_hw_state()
2227 if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) in bxt_ddi_pll_get_hw_state()
2228 drm_dbg(display->drm, in bxt_ddi_pll_get_hw_state()
2230 hw_state->pcsdw12, in bxt_ddi_pll_get_hw_state()
2233 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; in bxt_ddi_pll_get_hw_state()
2243 /* pre-calculated values for DP linkrates */
2267 return -EINVAL; in bxt_ddi_hdmi_pll_dividers()
2269 drm_WARN_ON(display->drm, clk_div->m1 != 2); in bxt_ddi_hdmi_pll_dividers()
2282 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2288 chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2290 drm_WARN_ON(display->drm, clk_div->vco == 0 || in bxt_ddi_dp_pll_dividers()
2291 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
2298 struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt; in bxt_ddi_set_dpll_hw_state()
2299 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2300 int vco = clk_div->vco; in bxt_ddi_set_dpll_hw_state()
2321 drm_err(display->drm, "Invalid VCO\n"); in bxt_ddi_set_dpll_hw_state()
2322 return -EINVAL; in bxt_ddi_set_dpll_hw_state()
2336 hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2); in bxt_ddi_set_dpll_hw_state()
2337 hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22); in bxt_ddi_set_dpll_hw_state()
2338 hw_state->pll1 = PORT_PLL_N(clk_div->n); in bxt_ddi_set_dpll_hw_state()
2339 hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff); in bxt_ddi_set_dpll_hw_state()
2341 if (clk_div->m2 & 0x3fffff) in bxt_ddi_set_dpll_hw_state()
2342 hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
2344 hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) | in bxt_ddi_set_dpll_hw_state()
2348 hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt); in bxt_ddi_set_dpll_hw_state()
2350 hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5); in bxt_ddi_set_dpll_hw_state()
2352 hw_state->pll10 = PORT_PLL_DCO_AMP(15) | in bxt_ddi_set_dpll_hw_state()
2355 hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_set_dpll_hw_state()
2357 hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger; in bxt_ddi_set_dpll_hw_state()
2366 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; in bxt_ddi_pll_get_freq()
2370 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22; in bxt_ddi_pll_get_freq()
2371 if (hw_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_ddi_pll_get_freq()
2373 hw_state->pll2); in bxt_ddi_pll_get_freq()
2374 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, hw_state->pll1); in bxt_ddi_pll_get_freq()
2375 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0); in bxt_ddi_pll_get_freq()
2376 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0); in bxt_ddi_pll_get_freq()
2378 return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2404 crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2405 &crtc_state->dpll_hw_state); in bxt_ddi_hdmi_set_dpll_hw_state()
2422 return -EINVAL; in bxt_compute_dpll()
2436 id = (enum intel_dpll_id) encoder->port; in bxt_get_dpll()
2439 drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n", in bxt_get_dpll()
2440 crtc->base.base.id, crtc->base.name, pll->info->name); in bxt_get_dpll()
2443 pll, &crtc_state->dpll_hw_state); in bxt_get_dpll()
2445 crtc_state->shared_dpll = pll; in bxt_get_dpll()
2452 display->dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2453 display->dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2454 /* DSI non-SSC ref 19.2MHz */ in bxt_update_dpll_ref_clks()
2460 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; in bxt_dump_hw_state()
2465 hw_state->ebb0, hw_state->ebb4, in bxt_dump_hw_state()
2466 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2467 hw_state->pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10, in bxt_dump_hw_state()
2468 hw_state->pcsdw12); in bxt_dump_hw_state()
2474 const struct bxt_dpll_hw_state *a = &_a->bxt; in bxt_compare_hw_state()
2475 const struct bxt_dpll_hw_state *b = &_b->bxt; in bxt_compare_hw_state()
2477 return a->ebb0 == b->ebb0 && in bxt_compare_hw_state()
2478 a->ebb4 == b->ebb4 && in bxt_compare_hw_state()
2479 a->pll0 == b->pll0 && in bxt_compare_hw_state()
2480 a->pll1 == b->pll1 && in bxt_compare_hw_state()
2481 a->pll2 == b->pll2 && in bxt_compare_hw_state()
2482 a->pll3 == b->pll3 && in bxt_compare_hw_state()
2483 a->pll6 == b->pll6 && in bxt_compare_hw_state()
2484 a->pll8 == b->pll8 && in bxt_compare_hw_state()
2485 a->pll10 == b->pll10 && in bxt_compare_hw_state()
2486 a->pcsdw12 == b->pcsdw12; in bxt_compare_hw_state()
2560 params->kdiv = 1; in icl_wrpll_params_populate()
2563 params->kdiv = 2; in icl_wrpll_params_populate()
2566 params->kdiv = 4; in icl_wrpll_params_populate()
2574 params->pdiv = 1; in icl_wrpll_params_populate()
2577 params->pdiv = 2; in icl_wrpll_params_populate()
2580 params->pdiv = 4; in icl_wrpll_params_populate()
2583 params->pdiv = 8; in icl_wrpll_params_populate()
2591 params->qdiv_ratio = qdiv; in icl_wrpll_params_populate()
2592 params->qdiv_mode = (qdiv == 1) ? 0 : 1; in icl_wrpll_params_populate()
2596 params->dco_integer = dco >> 15; in icl_wrpll_params_populate()
2597 params->dco_fraction = dco & 0x7fff; in icl_wrpll_params_populate()
2601 * Display WA #22010492432: ehl, tgl, adl-s, adl-p
2607 return ((display->platform.elkhartlake && in ehl_combo_pll_div_frac_wa_needed()
2609 display->platform.tigerlake || in ehl_combo_pll_div_frac_wa_needed()
2610 display->platform.alderlake_s || in ehl_combo_pll_div_frac_wa_needed()
2611 display->platform.alderlake_p) && in ehl_combo_pll_div_frac_wa_needed()
2612 display->dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2706 display->dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2709 int clock = crtc_state->port_clock; in icl_calc_dp_combo_pll()
2720 return -EINVAL; in icl_calc_dp_combo_pll()
2729 switch (display->dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2731 MISSING_CASE(display->dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2742 switch (display->dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2744 MISSING_CASE(display->dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2767 drm_WARN_ON(display->drm, 1); in icl_ddi_tbt_pll_get_freq()
2774 int ref_clock = display->dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2792 u32 afe_clock = crtc_state->port_clock * 5; in icl_calc_wrpll()
2810 dco_centrality = abs(dco - dco_mid); in icl_calc_wrpll()
2821 return -EINVAL; in icl_calc_wrpll()
2834 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_ddi_combo_pll_get_freq()
2839 p0 = hw_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; in icl_ddi_combo_pll_get_freq()
2840 p2 = hw_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; in icl_ddi_combo_pll_get_freq()
2842 if (hw_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) in icl_ddi_combo_pll_get_freq()
2843 p1 = (hw_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> in icl_ddi_combo_pll_get_freq()
2875 dco_freq = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in icl_ddi_combo_pll_get_freq()
2878 dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in icl_ddi_combo_pll_get_freq()
2886 if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0)) in icl_ddi_combo_pll_get_freq()
2896 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_calc_dpll_state()
2897 u32 dco_fraction = pll_params->dco_fraction; in icl_calc_dpll_state()
2902 hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | in icl_calc_dpll_state()
2903 pll_params->dco_integer; in icl_calc_dpll_state()
2905 hw_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) | in icl_calc_dpll_state()
2906 DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) | in icl_calc_dpll_state()
2907 DPLL_CFGCR1_KDIV(pll_params->kdiv) | in icl_calc_dpll_state()
2908 DPLL_CFGCR1_PDIV(pll_params->pdiv); in icl_calc_dpll_state()
2911 hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; in icl_calc_dpll_state()
2913 hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; in icl_calc_dpll_state()
2915 if (display->vbt.override_afc_startup) in icl_calc_dpll_state()
2916 hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val); in icl_calc_dpll_state()
2935 for (div2 = 10; div2 > 0; div2--) { in icl_mg_pll_find_divisors()
2947 * working on HW for DP alt-mode at least in icl_mg_pll_find_divisors()
2977 hw_state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1); in icl_mg_pll_find_divisors()
2979 hw_state->mg_clktop2_coreclkctl1 = in icl_mg_pll_find_divisors()
2982 hw_state->mg_clktop2_hsclkctl = in icl_mg_pll_find_divisors()
2992 return -EINVAL; in icl_mg_pll_find_divisors()
2997 * adapted to integer-only calculation, that's why it looks so different.
3003 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_calc_mg_pll_state()
3004 int refclk_khz = display->dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3005 int clock = crtc_state->port_clock; in icl_calc_mg_pll_state()
3031 return -EINVAL; in icl_calc_mg_pll_state()
3057 return -EINVAL; in icl_calc_mg_pll_state()
3108 hw_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) | in icl_calc_mg_pll_state()
3112 if (display->vbt.override_afc_startup) { in icl_calc_mg_pll_state()
3113 u8 val = display->vbt.override_afc_startup_val; in icl_calc_mg_pll_state()
3115 hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val); in icl_calc_mg_pll_state()
3118 hw_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) | in icl_calc_mg_pll_state()
3121 hw_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) | in icl_calc_mg_pll_state()
3126 hw_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) | in icl_calc_mg_pll_state()
3129 hw_state->mg_pll_tdc_coldst_bias = in icl_calc_mg_pll_state()
3134 hw_state->mg_pll_div0 = in icl_calc_mg_pll_state()
3139 hw_state->mg_pll_div1 = in icl_calc_mg_pll_state()
3145 hw_state->mg_pll_lf = in icl_calc_mg_pll_state()
3152 hw_state->mg_pll_frac_lock = in icl_calc_mg_pll_state()
3159 hw_state->mg_pll_frac_lock |= in icl_calc_mg_pll_state()
3162 hw_state->mg_pll_ssc = in icl_calc_mg_pll_state()
3170 hw_state->mg_pll_tdc_coldst_bias = in icl_calc_mg_pll_state()
3177 hw_state->mg_pll_bias = in icl_calc_mg_pll_state()
3187 hw_state->mg_pll_tdc_coldst_bias_mask = in icl_calc_mg_pll_state()
3189 hw_state->mg_pll_bias_mask = 0; in icl_calc_mg_pll_state()
3191 hw_state->mg_pll_tdc_coldst_bias_mask = -1U; in icl_calc_mg_pll_state()
3192 hw_state->mg_pll_bias_mask = -1U; in icl_calc_mg_pll_state()
3195 hw_state->mg_pll_tdc_coldst_bias &= in icl_calc_mg_pll_state()
3196 hw_state->mg_pll_tdc_coldst_bias_mask; in icl_calc_mg_pll_state()
3197 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; in icl_calc_mg_pll_state()
3207 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_ddi_mg_pll_get_freq()
3211 ref_clock = display->dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3214 m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3216 m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3218 if (hw_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { in icl_ddi_mg_pll_get_freq()
3219 m2_frac = hw_state->mg_pll_bias & in icl_ddi_mg_pll_get_freq()
3226 m1 = hw_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3227 m2_int = hw_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3229 if (hw_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { in icl_ddi_mg_pll_get_freq()
3230 m2_frac = hw_state->mg_pll_div0 & in icl_ddi_mg_pll_get_freq()
3238 switch (hw_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3253 MISSING_CASE(hw_state->mg_clktop2_hsclkctl); in icl_ddi_mg_pll_get_freq()
3257 div2 = (hw_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3277 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3288 &crtc_state->icl_port_dplls[port_dpll_id]; in icl_set_active_port_dpll()
3290 crtc_state->shared_dpll = port_dpll->pll; in icl_set_active_port_dpll()
3291 crtc_state->dpll_hw_state = port_dpll->hw_state; in icl_set_active_port_dpll()
3303 primary_port = encoder->type == INTEL_OUTPUT_DP_MST ? in icl_update_active_dpll()
3304 enc_to_mst(encoder)->primary : in icl_update_active_dpll()
3322 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_combo_phy_dpll()
3335 icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3340 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL, in icl_compute_combo_phy_dpll()
3341 &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3354 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_combo_phy_dpll()
3355 enum port port = encoder->port; in icl_get_combo_phy_dpll()
3358 if (display->platform.alderlake_s) { in icl_get_combo_phy_dpll()
3364 } else if (display->platform.dg1) { in icl_get_combo_phy_dpll()
3374 } else if (display->platform.rocketlake) { in icl_get_combo_phy_dpll()
3379 } else if ((display->platform.jasperlake || in icl_get_combo_phy_dpll()
3380 display->platform.elkhartlake) && in icl_get_combo_phy_dpll()
3393 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_combo_phy_dpll()
3394 &port_dpll->hw_state, in icl_get_combo_phy_dpll()
3396 if (!port_dpll->pll) in icl_get_combo_phy_dpll()
3397 return -EINVAL; in icl_get_combo_phy_dpll()
3400 port_dpll->pll, &port_dpll->hw_state); in icl_get_combo_phy_dpll()
3416 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3420 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3425 icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3427 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; in icl_compute_tc_phy_dplls()
3428 ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3433 if (old_crtc_state->shared_dpll && in icl_compute_tc_phy_dplls()
3434 old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) in icl_compute_tc_phy_dplls()
3439 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL, in icl_compute_tc_phy_dplls()
3440 &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3452 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3456 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3457 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_tc_phy_dplls()
3458 &port_dpll->hw_state, in icl_get_tc_phy_dplls()
3460 if (!port_dpll->pll) in icl_get_tc_phy_dplls()
3461 return -EINVAL; in icl_get_tc_phy_dplls()
3463 port_dpll->pll, &port_dpll->hw_state); in icl_get_tc_phy_dplls()
3466 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; in icl_get_tc_phy_dplls()
3468 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_tc_phy_dplls()
3469 &port_dpll->hw_state, in icl_get_tc_phy_dplls()
3471 if (!port_dpll->pll) { in icl_get_tc_phy_dplls()
3472 ret = -EINVAL; in icl_get_tc_phy_dplls()
3476 port_dpll->pll, &port_dpll->hw_state); in icl_get_tc_phy_dplls()
3483 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3484 intel_unreference_shared_dpll(state, crtc, port_dpll->pll); in icl_get_tc_phy_dplls()
3498 MISSING_CASE(encoder->port); in icl_compute_dplls()
3512 MISSING_CASE(encoder->port); in icl_get_dplls()
3514 return -EINVAL; in icl_get_dplls()
3526 new_crtc_state->shared_dpll = NULL; in icl_put_dplls()
3530 &old_crtc_state->icl_port_dplls[id]; in icl_put_dplls()
3532 &new_crtc_state->icl_port_dplls[id]; in icl_put_dplls()
3534 new_port_dpll->pll = NULL; in icl_put_dplls()
3536 if (!old_port_dpll->pll) in icl_put_dplls()
3539 intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll); in icl_put_dplls()
3547 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in mg_pll_get_hw_state()
3548 const enum intel_dpll_id id = pll->info->id; in mg_pll_get_hw_state()
3565 hw_state->mg_refclkin_ctl = intel_de_read(display, in mg_pll_get_hw_state()
3567 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in mg_pll_get_hw_state()
3569 hw_state->mg_clktop2_coreclkctl1 = in mg_pll_get_hw_state()
3571 hw_state->mg_clktop2_coreclkctl1 &= in mg_pll_get_hw_state()
3574 hw_state->mg_clktop2_hsclkctl = in mg_pll_get_hw_state()
3576 hw_state->mg_clktop2_hsclkctl &= in mg_pll_get_hw_state()
3582 hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3583 hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3584 hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port)); in mg_pll_get_hw_state()
3585 hw_state->mg_pll_frac_lock = intel_de_read(display, in mg_pll_get_hw_state()
3587 hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port)); in mg_pll_get_hw_state()
3589 hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port)); in mg_pll_get_hw_state()
3590 hw_state->mg_pll_tdc_coldst_bias = in mg_pll_get_hw_state()
3593 if (display->dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3594 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; in mg_pll_get_hw_state()
3595 hw_state->mg_pll_bias_mask = 0; in mg_pll_get_hw_state()
3597 hw_state->mg_pll_tdc_coldst_bias_mask = -1U; in mg_pll_get_hw_state()
3598 hw_state->mg_pll_bias_mask = -1U; in mg_pll_get_hw_state()
3601 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask; in mg_pll_get_hw_state()
3602 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; in mg_pll_get_hw_state()
3614 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in dkl_pll_get_hw_state()
3615 const enum intel_dpll_id id = pll->info->id; in dkl_pll_get_hw_state()
3634 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display, in dkl_pll_get_hw_state()
3636 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in dkl_pll_get_hw_state()
3638 hw_state->mg_clktop2_hsclkctl = in dkl_pll_get_hw_state()
3640 hw_state->mg_clktop2_hsclkctl &= in dkl_pll_get_hw_state()
3646 hw_state->mg_clktop2_coreclkctl1 = in dkl_pll_get_hw_state()
3648 hw_state->mg_clktop2_coreclkctl1 &= in dkl_pll_get_hw_state()
3651 hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3653 if (display->vbt.override_afc_startup) in dkl_pll_get_hw_state()
3655 hw_state->mg_pll_div0 &= val; in dkl_pll_get_hw_state()
3657 hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3658 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()
3661 hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port)); in dkl_pll_get_hw_state()
3662 hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | in dkl_pll_get_hw_state()
3667 hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port)); in dkl_pll_get_hw_state()
3668 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | in dkl_pll_get_hw_state()
3671 hw_state->mg_pll_tdc_coldst_bias = in dkl_pll_get_hw_state()
3673 hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | in dkl_pll_get_hw_state()
3687 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_pll_get_hw_state()
3688 const enum intel_dpll_id id = pll->info->id; in icl_pll_get_hw_state()
3702 if (display->platform.alderlake_s) { in icl_pll_get_hw_state()
3703 hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3704 hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3705 } else if (display->platform.dg1) { in icl_pll_get_hw_state()
3706 hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3707 hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3708 } else if (display->platform.rocketlake) { in icl_pll_get_hw_state()
3709 hw_state->cfgcr0 = intel_de_read(display, in icl_pll_get_hw_state()
3711 hw_state->cfgcr1 = intel_de_read(display, in icl_pll_get_hw_state()
3714 hw_state->cfgcr0 = intel_de_read(display, in icl_pll_get_hw_state()
3716 hw_state->cfgcr1 = intel_de_read(display, in icl_pll_get_hw_state()
3718 if (display->vbt.override_afc_startup) { in icl_pll_get_hw_state()
3719 hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id)); in icl_pll_get_hw_state()
3720 hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK; in icl_pll_get_hw_state()
3723 if ((display->platform.jasperlake || display->platform.elkhartlake) && in icl_pll_get_hw_state()
3725 hw_state->cfgcr0 = intel_de_read(display, in icl_pll_get_hw_state()
3727 hw_state->cfgcr1 = intel_de_read(display, in icl_pll_get_hw_state()
3730 hw_state->cfgcr0 = intel_de_read(display, in icl_pll_get_hw_state()
3732 hw_state->cfgcr1 = intel_de_read(display, in icl_pll_get_hw_state()
3763 const enum intel_dpll_id id = pll->info->id; in icl_dpll_write()
3766 if (display->platform.alderlake_s) { in icl_dpll_write()
3769 } else if (display->platform.dg1) { in icl_dpll_write()
3772 } else if (display->platform.rocketlake) { in icl_dpll_write()
3780 if ((display->platform.jasperlake || display->platform.elkhartlake) && in icl_dpll_write()
3790 intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
3791 intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1); in icl_dpll_write()
3792 drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup && in icl_dpll_write()
3794 if (display->vbt.override_afc_startup && in icl_dpll_write()
3797 TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); in icl_dpll_write()
3805 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in icl_mg_pll_write()
3814 MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl); in icl_mg_pll_write()
3818 hw_state->mg_clktop2_coreclkctl1); in icl_mg_pll_write()
3825 hw_state->mg_clktop2_hsclkctl); in icl_mg_pll_write()
3827 intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); in icl_mg_pll_write()
3828 intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3829 intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); in icl_mg_pll_write()
3831 hw_state->mg_pll_frac_lock); in icl_mg_pll_write()
3832 intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); in icl_mg_pll_write()
3835 hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias); in icl_mg_pll_write()
3838 hw_state->mg_pll_tdc_coldst_bias_mask, in icl_mg_pll_write()
3839 hw_state->mg_pll_tdc_coldst_bias); in icl_mg_pll_write()
3848 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in dkl_pll_write()
3858 val |= hw_state->mg_refclkin_ctl; in dkl_pll_write()
3863 val |= hw_state->mg_clktop2_coreclkctl1; in dkl_pll_write()
3871 val |= hw_state->mg_clktop2_hsclkctl; in dkl_pll_write()
3875 if (display->vbt.override_afc_startup) in dkl_pll_write()
3878 hw_state->mg_pll_div0); in dkl_pll_write()
3883 val |= hw_state->mg_pll_div1; in dkl_pll_write()
3891 val |= hw_state->mg_pll_ssc; in dkl_pll_write()
3897 val |= hw_state->mg_pll_bias; in dkl_pll_write()
3903 val |= hw_state->mg_pll_tdc_coldst_bias; in dkl_pll_write()
3920 drm_err(display->drm, "PLL %d Power not enabled\n", in icl_pll_power_enable()
3921 pll->info->id); in icl_pll_power_enable()
3932 drm_err(display->drm, "PLL %d not locked\n", pll->info->id); in icl_pll_enable()
3939 if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) || in adlp_cmtg_clock_gating_wa()
3940 pll->info->id != DPLL_ID_ICL_DPLL0) in adlp_cmtg_clock_gating_wa()
3943 * Wa_16011069516:adl-p[a0] in adlp_cmtg_clock_gating_wa()
3955 if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING)) in adlp_cmtg_clock_gating_wa()
3956 drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); in adlp_cmtg_clock_gating_wa()
3963 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in combo_pll_enable()
3987 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in tbt_pll_enable()
4008 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in mg_pll_enable()
4045 drm_err(display->drm, "PLL %d locked\n", pll->info->id); in icl_pll_disable()
4056 drm_err(display->drm, "PLL %d Power not disabled\n", in icl_pll_disable()
4057 pll->info->id); in icl_pll_disable()
4084 /* No SSC ref */ in icl_update_dpll_ref_clks()
4085 display->dpll.ref_clks.nssc = display->cdclk.hw.ref; in icl_update_dpll_ref_clks()
4091 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_dump_hw_state()
4099 hw_state->cfgcr0, hw_state->cfgcr1, hw_state->div0, in icl_dump_hw_state()
4100 hw_state->mg_refclkin_ctl, in icl_dump_hw_state()
4101 hw_state->mg_clktop2_coreclkctl1, in icl_dump_hw_state()
4102 hw_state->mg_clktop2_hsclkctl, in icl_dump_hw_state()
4103 hw_state->mg_pll_div0, in icl_dump_hw_state()
4104 hw_state->mg_pll_div1, in icl_dump_hw_state()
4105 hw_state->mg_pll_lf, in icl_dump_hw_state()
4106 hw_state->mg_pll_frac_lock, in icl_dump_hw_state()
4107 hw_state->mg_pll_ssc, in icl_dump_hw_state()
4108 hw_state->mg_pll_bias, in icl_dump_hw_state()
4109 hw_state->mg_pll_tdc_coldst_bias); in icl_dump_hw_state()
4115 const struct icl_dpll_hw_state *a = &_a->icl; in icl_compare_hw_state()
4116 const struct icl_dpll_hw_state *b = &_b->icl; in icl_compare_hw_state()
4119 return a->cfgcr0 == b->cfgcr0 && in icl_compare_hw_state()
4120 a->cfgcr1 == b->cfgcr1 && in icl_compare_hw_state()
4121 a->div0 == b->div0 && in icl_compare_hw_state()
4122 a->mg_refclkin_ctl == b->mg_refclkin_ctl && in icl_compare_hw_state()
4123 a->mg_clktop2_coreclkctl1 == b->mg_clktop2_coreclkctl1 && in icl_compare_hw_state()
4124 a->mg_clktop2_hsclkctl == b->mg_clktop2_hsclkctl && in icl_compare_hw_state()
4125 a->mg_pll_div0 == b->mg_pll_div0 && in icl_compare_hw_state()
4126 a->mg_pll_div1 == b->mg_pll_div1 && in icl_compare_hw_state()
4127 a->mg_pll_lf == b->mg_pll_lf && in icl_compare_hw_state()
4128 a->mg_pll_frac_lock == b->mg_pll_frac_lock && in icl_compare_hw_state()
4129 a->mg_pll_ssc == b->mg_pll_ssc && in icl_compare_hw_state()
4130 a->mg_pll_bias == b->mg_pll_bias && in icl_compare_hw_state()
4131 a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias; in icl_compare_hw_state()
4305 * intel_shared_dpll_init - Initialize shared DPLLs
4312 struct drm_i915_private *i915 = to_i915(display->drm); in intel_shared_dpll_init()
4317 mutex_init(&display->dpll.lock); in intel_shared_dpll_init()
4319 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) in intel_shared_dpll_init()
4322 else if (display->platform.alderlake_p) in intel_shared_dpll_init()
4324 else if (display->platform.alderlake_s) in intel_shared_dpll_init()
4326 else if (display->platform.dg1) in intel_shared_dpll_init()
4328 else if (display->platform.rocketlake) in intel_shared_dpll_init()
4332 else if (display->platform.jasperlake || display->platform.elkhartlake) in intel_shared_dpll_init()
4336 else if (display->platform.geminilake || display->platform.broxton) in intel_shared_dpll_init()
4348 dpll_info = dpll_mgr->dpll_info; in intel_shared_dpll_init()
4351 if (drm_WARN_ON(display->drm, in intel_shared_dpll_init()
4352 i >= ARRAY_SIZE(display->dpll.shared_dplls))) in intel_shared_dpll_init()
4356 if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32)) in intel_shared_dpll_init()
4359 display->dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4360 display->dpll.shared_dplls[i].index = i; in intel_shared_dpll_init()
4363 display->dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4364 display->dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4368 * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
4386 const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; in intel_compute_shared_dplls()
4388 if (drm_WARN_ON(display->drm, !dpll_mgr)) in intel_compute_shared_dplls()
4389 return -EINVAL; in intel_compute_shared_dplls()
4391 return dpll_mgr->compute_dplls(state, crtc, encoder); in intel_compute_shared_dplls()
4395 * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
4419 const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; in intel_reserve_shared_dplls()
4421 if (drm_WARN_ON(display->drm, !dpll_mgr)) in intel_reserve_shared_dplls()
4422 return -EINVAL; in intel_reserve_shared_dplls()
4424 return dpll_mgr->get_dplls(state, crtc, encoder); in intel_reserve_shared_dplls()
4428 * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
4442 const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; in intel_release_shared_dplls()
4453 dpll_mgr->put_dplls(state, crtc); in intel_release_shared_dplls()
4457 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4471 const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; in intel_update_active_dpll()
4473 if (drm_WARN_ON(display->drm, !dpll_mgr)) in intel_update_active_dpll()
4476 dpll_mgr->update_active_dpll(state, crtc, encoder); in intel_update_active_dpll()
4480 * intel_dpll_get_freq - calculate the DPLL's output frequency
4491 if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq)) in intel_dpll_get_freq()
4494 return pll->info->funcs->get_freq(display, pll, dpll_hw_state); in intel_dpll_get_freq()
4498 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4509 return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state); in intel_dpll_get_hw_state()
4517 pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state); in readout_dpll_hw_state()
4519 if (pll->on && pll->info->power_domain) in readout_dpll_hw_state()
4520 pll->wakeref = intel_display_power_get(display, pll->info->power_domain); in readout_dpll_hw_state()
4522 pll->state.pipe_mask = 0; in readout_dpll_hw_state()
4523 for_each_intel_crtc(display->drm, crtc) { in readout_dpll_hw_state()
4525 to_intel_crtc_state(crtc->base.state); in readout_dpll_hw_state()
4527 if (crtc_state->hw.active && crtc_state->shared_dpll == pll) in readout_dpll_hw_state()
4528 intel_reference_shared_dpll_crtc(crtc, pll, &pll->state); in readout_dpll_hw_state()
4530 pll->active_mask = pll->state.pipe_mask; in readout_dpll_hw_state()
4532 drm_dbg_kms(display->drm, in readout_dpll_hw_state()
4534 pll->info->name, pll->state.pipe_mask, pll->on); in readout_dpll_hw_state()
4539 if (display->dpll.mgr && display->dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4540 display->dpll.mgr->update_ref_clks(display); in intel_dpll_update_ref_clks()
4555 if (!pll->on) in sanitize_dpll_state()
4560 if (pll->active_mask) in sanitize_dpll_state()
4563 drm_dbg_kms(display->drm, in sanitize_dpll_state()
4565 pll->info->name); in sanitize_dpll_state()
4582 * intel_dpll_dump_hw_state - dump hw_state
4593 if (display->dpll.mgr) { in intel_dpll_dump_hw_state()
4594 display->dpll.mgr->dump_hw_state(p, dpll_hw_state); in intel_dpll_dump_hw_state()
4604 * intel_dpll_compare_hw_state - compare the two states
4617 if (display->dpll.mgr) { in intel_dpll_compare_hw_state()
4618 return display->dpll.mgr->compare_hw_state(a, b); in intel_dpll_compare_hw_state()
4639 if (!pll->info->always_on) { in verify_single_dpll_state()
4640 INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask, in verify_single_dpll_state()
4642 pll->info->name); in verify_single_dpll_state()
4643 INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask, in verify_single_dpll_state()
4645 pll->info->name); in verify_single_dpll_state()
4646 INTEL_DISPLAY_STATE_WARN(display, pll->on != active, in verify_single_dpll_state()
4648 pll->info->name, pll->on, active); in verify_single_dpll_state()
4653 pll->active_mask & ~pll->state.pipe_mask, in verify_single_dpll_state()
4655 pll->info->name, pll->active_mask, pll->state.pipe_mask); in verify_single_dpll_state()
4660 pipe_mask = BIT(crtc->pipe); in verify_single_dpll_state()
4662 if (new_crtc_state->hw.active) in verify_single_dpll_state()
4663 INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask), in verify_single_dpll_state()
4665 pll->info->name, pipe_name(crtc->pipe), pll->active_mask); in verify_single_dpll_state()
4667 INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask, in verify_single_dpll_state()
4669 pll->info->name, pipe_name(crtc->pipe), pll->active_mask); in verify_single_dpll_state()
4671 INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
4673 pll->info->name, pipe_mask, pll->state.pipe_mask); in verify_single_dpll_state()
4676 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, in verify_single_dpll_state()
4679 pll->info->name); in verify_single_dpll_state()
4686 (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll); in has_alt_port_dpll()
4698 if (new_crtc_state->shared_dpll) in intel_shared_dpll_state_verify()
4699 verify_single_dpll_state(display, new_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4702 if (old_crtc_state->shared_dpll && in intel_shared_dpll_state_verify()
4703 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { in intel_shared_dpll_state_verify()
4704 u8 pipe_mask = BIT(crtc->pipe); in intel_shared_dpll_state_verify()
4705 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; in intel_shared_dpll_state_verify()
4707 INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask, in intel_shared_dpll_state_verify()
4709 pll->info->name, pipe_name(crtc->pipe), pll->active_mask); in intel_shared_dpll_state_verify()
4712 INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4713 new_crtc_state->shared_dpll) && in intel_shared_dpll_state_verify()
4714 pll->state.pipe_mask & pipe_mask, in intel_shared_dpll_state_verify()
4716 pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask); in intel_shared_dpll_state_verify()