Lines Matching +full:dp +full:- +full:phy0
2 * Copyright © 2014-2016 Intel Corporation
40 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
46 * IOSF-SB port.
50 * logic. CH0 common lane also contains the IOSF-SB logic for the
60 * each spline is made up of one Physical Access Coding Sub-Layer
62 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
66 * for each channel. This is used for DP AUX communication, but
104 * ---------------------------------
107 * |---------------|---------------| Display PHY
109 * |-------|-------|-------|-------|
111 * ---------------------------------
112 * | DDI0 | DDI1 | DP/HDMI ports
113 * ---------------------------------
116 * -----------------
119 * |---------------| Display PHY
121 * |-------|-------|
123 * -----------------
124 * | DDI2 | DP/HDMI port
125 * -----------------
129 * struct bxt_dpio_phy_info - Hold info for a broxton DDI phy
138 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
180 .rcomp_phy = -1,
202 .rcomp_phy = -1,
225 struct drm_i915_private *dev_priv = to_i915(display->drm); in bxt_get_phy_list()
257 if (port == phy_info->channel[DPIO_CH0].port) { in bxt_port_to_phy_channel()
263 if (phy_info->dual_channel && in bxt_port_to_phy_channel()
264 port == phy_info->channel[DPIO_CH1].port) { in bxt_port_to_phy_channel()
271 drm_WARN(display->drm, 1, "PHY not found for PORT %c", in bxt_port_to_phy_channel()
278 * Like intel_de_rmw() but reads from a single per-lane register and
304 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in bxt_dpio_phy_set_signal_levels()
305 if (drm_WARN_ON_ONCE(display->drm, !trans)) in bxt_dpio_phy_set_signal_levels()
308 bxt_port_to_phy_channel(display, encoder->port, &phy, &ch); in bxt_dpio_phy_set_signal_levels()
318 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
323 MARGIN_000(trans->entries[level].bxt.margin) | in bxt_dpio_phy_set_signal_levels()
324 UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale)); in bxt_dpio_phy_set_signal_levels()
327 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
333 trans->entries[level].bxt.enable ? in bxt_dpio_phy_set_signal_levels()
338 drm_err(display->drm, in bxt_dpio_phy_set_signal_levels()
342 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
347 DE_EMPHASIS(trans->entries[level].bxt.deemphasis)); in bxt_dpio_phy_set_signal_levels()
362 if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_dpio_phy_is_enabled()
367 drm_dbg(display->drm, in bxt_dpio_phy_is_enabled()
374 drm_dbg(display->drm, in bxt_dpio_phy_is_enabled()
394 drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy); in bxt_phy_wait_grc_done()
406 if (phy_info->rcomp_phy != -1) in _bxt_dpio_phy_init()
407 display->state.bxt_phy_grc = bxt_get_grc(display, phy); in _bxt_dpio_phy_init()
410 drm_dbg(display->drm, "DDI PHY %d already enabled, " in _bxt_dpio_phy_init()
415 drm_dbg(display->drm, in _bxt_dpio_phy_init()
420 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); in _bxt_dpio_phy_init()
432 drm_err(display->drm, "timeout during PHY%d power on\n", in _bxt_dpio_phy_init()
446 if (phy_info->dual_channel) in _bxt_dpio_phy_init()
450 if (phy_info->rcomp_phy != -1) { in _bxt_dpio_phy_init()
453 bxt_phy_wait_grc_done(display, phy_info->rcomp_phy); in _bxt_dpio_phy_init()
456 * PHY0 isn't connected to an RCOMP resistor so copy over in _bxt_dpio_phy_init()
458 * the automatic calibration on PHY0. in _bxt_dpio_phy_init()
460 val = bxt_get_grc(display, phy_info->rcomp_phy); in _bxt_dpio_phy_init()
461 display->state.bxt_phy_grc = val; in _bxt_dpio_phy_init()
471 if (phy_info->reset_delay) in _bxt_dpio_phy_init()
472 udelay(phy_info->reset_delay); in _bxt_dpio_phy_init()
485 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0); in bxt_dpio_phy_uninit()
491 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; in bxt_dpio_phy_init()
494 lockdep_assert_held(&display->power.domains.lock); in bxt_dpio_phy_init()
497 if (rcomp_phy != -1) in bxt_dpio_phy_init()
530 drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " in __phy_reg_verify_state()
571 if (phy_info->dual_channel) in bxt_dpio_phy_verify_state()
576 if (phy_info->rcomp_phy != -1) { in bxt_dpio_phy_verify_state()
577 u32 grc_code = display->state.bxt_phy_grc; in bxt_dpio_phy_verify_state()
617 enum port port = encoder->port; in bxt_dpio_phy_set_lane_optim_mask()
639 enum port port = encoder->port; in bxt_dpio_phy_get_lane_lat_optim_mask()
661 switch (dig_port->base.port) { in vlv_dig_port_to_channel()
663 MISSING_CASE(dig_port->base.port); in vlv_dig_port_to_channel()
675 switch (dig_port->base.port) { in vlv_dig_port_to_phy()
677 MISSING_CASE(dig_port->base.port); in vlv_dig_port_to_phy()
720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_set_phy_signal_level()
736 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
749 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
757 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
765 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
788 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
802 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_data_lane_soft_reset()
828 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
845 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_pre_pll_enable()
862 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_phy_pre_pll_enable()
865 enum pipe pipe = crtc->pipe; in chv_phy_pre_pll_enable()
867 intel_dp_unused_lane_mask(crtc_state->lane_count); in chv_phy_pre_pll_enable()
875 dig_port->release_cl2_override = in chv_phy_pre_pll_enable()
913 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable()
943 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_pre_encoder_enable()
956 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
963 for (i = 0; i < crtc_state->lane_count; i++) { in chv_phy_pre_encoder_enable()
965 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable()
973 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
975 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
977 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
979 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
988 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
1001 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
1021 if (dig_port->release_cl2_override) { in chv_phy_release_cl2_override()
1023 dig_port->release_cl2_override = false; in chv_phy_release_cl2_override()
1030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_post_pll_disable()
1032 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; in chv_phy_post_pll_disable()
1067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_set_phy_signal_level()
1094 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_pre_pll_enable()
1110 /* Fix up inter-pair skew failure */ in vlv_phy_pre_pll_enable()
1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_pre_encoder_enable()
1124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_phy_pre_encoder_enable()
1127 enum pipe pipe = crtc->pipe; in vlv_phy_pre_encoder_enable()
1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_reset_lanes()
1167 switch (encoder->port) { in vlv_wait_port_ready()
1169 MISSING_CASE(encoder->port); in vlv_wait_port_ready()
1187 drm_WARN(display->drm, 1, in vlv_wait_port_ready()
1189 encoder->base.base.id, encoder->base.name, in vlv_wait_port_ready()