385 /* 128b/132b */
489 		       "128b/132b, lanes: %d, "  in intel_dp_get_adjust_train()
601 		       "128b/132b, lanes: %d, "  in intel_dp_set_signal_levels()
648 /* 128b/132b */
799 	 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate  in intel_dp_prepare_link_train()
938  * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
949 	/* UHBR+ use separate 128b/132b TPS2 */  in intel_dp_training_pattern()
1121 		lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");  in intel_dp_stop_link_train()
1354  * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1)
1367 	 * Reset signal levels. Start transmitting 128b/132b TPS1.  in intel_dp_128b132b_lane_eq()
1374 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");  in intel_dp_128b132b_lane_eq()
1393 	/* Start transmitting 128b/132b TPS2. */  in intel_dp_128b132b_lane_eq()
1396 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");  in intel_dp_128b132b_lane_eq()
1486  * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2)
1498 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");  in intel_dp_128b132b_lane_cds()
1542  * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.)
1552 		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");  in intel_dp_128b132b_link_train()
1561 	       "128b/132b Link Training %s at link rate = %d, lane count = %d\n",  in intel_dp_128b132b_link_train()
1674 	/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */  in intel_dp_128b132b_sdp_crc16()
1679 	lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");  in intel_dp_128b132b_sdp_crc16()