97 /* DP DSC throughput values used for slice count calculations KPixels/s */
105 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
108 /* Constants for DP DSC configurations */
126  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
127  * @intel_dp: DP struct
129  * If a CPU or PCH DP output is attached to an eDP panel, this function
138 	return dig_port->base.type == INTEL_OUTPUT_EDP;  in intel_dp_is_edp()
146 	return drm_dp_is_uhbr_rate(crtc_state->port_clock);  in intel_dp_is_uhbr()
150  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
154  * rate -> channel coding.
162  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
176 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in max_dprx_rate()
180 		max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);  in max_dprx_rate()
182 		max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);  in max_dprx_rate()
189 	if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {  in max_dprx_rate()
190 		drm_dbg_kms(display->drm,  in max_dprx_rate()
192 			    encoder->base.base.id, encoder->base.name);  in max_dprx_rate()
202 		return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);  in max_dprx_lane_count()
204 	return drm_dp_max_lane_count(intel_dp->dpcd);  in max_dprx_lane_count()
209 	intel_dp->sink_rates[0] = 162000;  in intel_dp_set_default_sink_rates()
210 	intel_dp->num_sink_rates = 1;  in intel_dp_set_default_sink_rates()
222 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {  in intel_dp_set_dpcd_sink_rates()
226 		memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));  in intel_dp_set_dpcd_sink_rates()
227 		intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);  in intel_dp_set_dpcd_sink_rates()
236 	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);  in intel_dp_set_dpcd_sink_rates()
243 		intel_dp->sink_rates[i] = dp_rates[i];  in intel_dp_set_dpcd_sink_rates()
250 	if (drm_dp_128b132b_supported(intel_dp->dpcd)) {  in intel_dp_set_dpcd_sink_rates()
253 		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);  in intel_dp_set_dpcd_sink_rates()
255 		drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_set_dpcd_sink_rates()
258 		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {  in intel_dp_set_dpcd_sink_rates()
260 			if (intel_dp->lttpr_common_caps[0] >= 0x20 &&  in intel_dp_set_dpcd_sink_rates()
261 			    intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -  in intel_dp_set_dpcd_sink_rates()
265 				uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -  in intel_dp_set_dpcd_sink_rates()
274 			intel_dp->sink_rates[i++] = 1000000;  in intel_dp_set_dpcd_sink_rates()
276 			intel_dp->sink_rates[i++] = 1350000;  in intel_dp_set_dpcd_sink_rates()
278 			intel_dp->sink_rates[i++] = 2000000;  in intel_dp_set_dpcd_sink_rates()
281 	intel_dp->num_sink_rates = i;  in intel_dp_set_dpcd_sink_rates()
287 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_sink_rates()  local
289 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_set_sink_rates()
293 	if (intel_dp->num_sink_rates)  in intel_dp_set_sink_rates()
296 	drm_err(display->drm,  in intel_dp_set_sink_rates()
297 		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",  in intel_dp_set_sink_rates()
298 		connector->base.base.id, connector->base.name,  in intel_dp_set_sink_rates()
299 		encoder->base.base.id, encoder->base.name);  in intel_dp_set_sink_rates()
306 	intel_dp->max_sink_lane_count = 1;  in intel_dp_set_default_max_sink_lane_count()
312 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_max_sink_lane_count()  local
314 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_set_max_sink_lane_count()
316 	intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);  in intel_dp_set_max_sink_lane_count()
318 	switch (intel_dp->max_sink_lane_count) {  in intel_dp_set_max_sink_lane_count()
325 	drm_err(display->drm,  in intel_dp_set_max_sink_lane_count()
326 		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",  in intel_dp_set_max_sink_lane_count()
327 		connector->base.base.id, connector->base.name,  in intel_dp_set_max_sink_lane_count()
328 		encoder->base.base.id, encoder->base.name,  in intel_dp_set_max_sink_lane_count()
329 		intel_dp->max_sink_lane_count);  in intel_dp_set_max_sink_lane_count()
341 		if (rates[len - i - 1] <= max_rate)  in intel_dp_rate_limit_len()
342 			return len - i;  in intel_dp_rate_limit_len()
352 	return intel_dp_rate_limit_len(intel_dp->common_rates,  in intel_dp_common_len_rate_limit()
353 				       intel_dp->num_common_rates, max_rate);  in intel_dp_common_len_rate_limit()
360 	if (drm_WARN_ON(display->drm,  in intel_dp_common_rate()
361 			index < 0 || index >= intel_dp->num_common_rates))  in intel_dp_common_rate()
364 	return intel_dp->common_rates[index];  in intel_dp_common_rate()
370 	return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);  in intel_dp_max_common_rate()
375 	int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);  in intel_dp_max_source_lane_count()
376 	int max_lanes = dig_port->max_lanes;  in intel_dp_max_source_lane_count()
389 	int sink_max = intel_dp->max_sink_lane_count;  in intel_dp_max_common_lane_count()
391 	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);  in intel_dp_max_common_lane_count()
401 	return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));  in forced_lane_count()
408 	if (intel_dp->link.force_lane_count)  in intel_dp_max_lane_count()
411 		lane_count = intel_dp->link.max_lane_count;  in intel_dp_max_lane_count()
426 	if (intel_dp->link.force_lane_count)  in intel_dp_min_lane_count()
447  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
464  * @intel_dp: Intel DP object
469  * account any BW limitations by a DP tunnel attached to @intel_dp.
480 			       drm_dp_tunnel_available_bw(intel_dp->tunnel));  in intel_dp_max_link_data_rate()
489 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_has_joiner()
492 	if (intel_dp->mso_link_count)  in intel_dp_has_joiner()
497 		 encoder->port != PORT_A);  in intel_dp_has_joiner()
507 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in icl_max_source_rate()
526 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in mtl_max_source_rate()
539 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in vbt_max_link_rate()
542 	max_rate = intel_bios_dp_max_link_rate(encoder->devdata);  in vbt_max_link_rate()
545 		struct intel_connector *connector = intel_dp->attached_connector;  in vbt_max_link_rate()  local
546 		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;  in vbt_max_link_rate()
590 	drm_WARN_ON(display->drm,  in intel_dp_set_source_rates()
591 		    intel_dp->source_rates || intel_dp->num_source_rates);  in intel_dp_set_source_rates()
594 		if (display->platform.battlemage) {  in intel_dp_set_source_rates()
605 		if (display->platform.dg2)  in intel_dp_set_source_rates()
607 		else if (display->platform.alderlake_p || display->platform.alderlake_s ||  in intel_dp_set_source_rates()
608 			 display->platform.dg1 || display->platform.rocketlake)  in intel_dp_set_source_rates()
610 		else if (display->platform.jasperlake || display->platform.elkhartlake)  in intel_dp_set_source_rates()
614 	} else if (display->platform.geminilake || display->platform.broxton) {  in intel_dp_set_source_rates()
620 	} else if ((display->platform.haswell && !display->platform.haswell_ulx) ||  in intel_dp_set_source_rates()
621 		   display->platform.broadwell) {  in intel_dp_set_source_rates()
638 	intel_dp->source_rates = source_rates;  in intel_dp_set_source_rates()
639 	intel_dp->num_source_rates = size;  in intel_dp_set_source_rates()
665 /* return index of rate in rates array, or -1 if not found */
674 	return -1;  in intel_dp_rate_index()
680 	return intel_dp_common_rate(intel_dp, lc->link_rate_idx);  in intel_dp_link_config_rate()
685 	return 1 << lc->lane_count_exp;  in intel_dp_link_config_lane_count()
704 		return bw_a - bw_b;  in link_config_cmp_by_bw()
706 	return intel_dp_link_config_rate(intel_dp, lc_a) -  in link_config_cmp_by_bw()
718 	if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))  in intel_dp_link_config_init()
723 	if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >  in intel_dp_link_config_init()
724 				    ARRAY_SIZE(intel_dp->link.configs)))  in intel_dp_link_config_init()
727 	intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;  in intel_dp_link_config_init()
729 	lc = &intel_dp->link.configs[0];  in intel_dp_link_config_init()
730 	for (i = 0; i < intel_dp->num_common_rates; i++) {  in intel_dp_link_config_init()
732 			lc->lane_count_exp = j;  in intel_dp_link_config_init()
733 			lc->link_rate_idx = i;  in intel_dp_link_config_init()
739 	sort_r(intel_dp->link.configs, intel_dp->link.num_configs,  in intel_dp_link_config_init()
740 	       sizeof(intel_dp->link.configs[0]),  in intel_dp_link_config_init()
750 	if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))  in intel_dp_link_config_get()
753 	lc = &intel_dp->link.configs[idx];  in intel_dp_link_config_get()
761 	int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,  in intel_dp_link_config_index()
766 	for (i = 0; i < intel_dp->link.num_configs; i++) {  in intel_dp_link_config_index()
767 		const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];  in intel_dp_link_config_index()
769 		if (lc->lane_count_exp == lane_count_exp &&  in intel_dp_link_config_index()
770 		    lc->link_rate_idx == link_rate_idx)  in intel_dp_link_config_index()
774 	return -1;  in intel_dp_link_config_index()
781 	drm_WARN_ON(display->drm,  in intel_dp_set_common_rates()
782 		    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);  in intel_dp_set_common_rates()
784 	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,  in intel_dp_set_common_rates()
785 						     intel_dp->num_source_rates,  in intel_dp_set_common_rates()
786 						     intel_dp->sink_rates,  in intel_dp_set_common_rates()
787 						     intel_dp->num_sink_rates,  in intel_dp_set_common_rates()
788 						     intel_dp->common_rates);  in intel_dp_set_common_rates()
791 	if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {  in intel_dp_set_common_rates()
792 		intel_dp->common_rates[0] = 162000;  in intel_dp_set_common_rates()
793 		intel_dp->num_common_rates = 1;  in intel_dp_set_common_rates()
805 	 * boot-up.  in intel_dp_link_params_valid()
808 	    link_rate > intel_dp->link.max_rate)  in intel_dp_link_params_valid()
828 	 * The hard-coded 1/0.972261=2.853% overhead factor  in intel_dp_bw_fec_overhead()
829 	 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +  in intel_dp_bw_fec_overhead()
833 	 * lane DP link, with 2 DSC slices and 8 bpp color depth).  in intel_dp_bw_fec_overhead()
856 		drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",  in intel_dp_dsc_nearest_valid_bpp()
861 	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */  in intel_dp_dsc_nearest_valid_bpp()
863 		bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);  in intel_dp_dsc_nearest_valid_bpp()
874 			drm_dbg_kms(display->drm,  in intel_dp_dsc_nearest_valid_bpp()
882 		for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {  in intel_dp_dsc_nearest_valid_bpp()
886 		drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",  in intel_dp_dsc_nearest_valid_bpp()
908 	max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /  in bigjoiner_bw_max_bpp()
970 	 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)  in intel_dp_dsc_get_max_compressed_bpp()
971 	 * for MST -> TimeSlots has to be calculated, based on mode requirements  in intel_dp_dsc_get_max_compressed_bpp()
999 	drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "  in intel_dp_dsc_get_max_compressed_bpp()
1014 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,  in intel_dp_dsc_get_slice_count()  argument
1018 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_get_slice_count()
1033 	if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))  in intel_dp_dsc_get_slice_count()
1036 	max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);  in intel_dp_dsc_get_slice_count()
1038 		drm_dbg_kms(display->drm,  in intel_dp_dsc_get_slice_count()
1039 			    "Unsupported slice width %d by DP DSC Sink device\n",  in intel_dp_dsc_get_slice_count()
1061 		    drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))  in intel_dp_dsc_get_slice_count()
1079 	drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",  in intel_dp_dsc_get_slice_count()
1096 		 * Also, ILK doesn't seem capable of DP YCbCr output.  in source_can_output()
1099 		return !HAS_GMCH(display) && !display->platform.ironlake;  in source_can_output()
1115 	if (!drm_dp_is_branch(intel_dp->dpcd))  in dfp_can_convert_from_rgb()
1119 		return intel_dp->dfp.rgb_to_ycbcr;  in dfp_can_convert_from_rgb()
1122 		return intel_dp->dfp.rgb_to_ycbcr &&  in dfp_can_convert_from_rgb()
1123 			intel_dp->dfp.ycbcr_444_to_420;  in dfp_can_convert_from_rgb()
1132 	if (!drm_dp_is_branch(intel_dp->dpcd))  in dfp_can_convert_from_ycbcr444()
1136 		return intel_dp->dfp.ycbcr_444_to_420;  in dfp_can_convert_from_ycbcr444()
1160 intel_dp_output_format(struct intel_connector *connector,  in intel_dp_output_format()  argument
1163 	struct intel_display *display = to_intel_display(connector);  in intel_dp_output_format()
1164 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_output_format()
1166 		intel_dp->force_dsc_output_format;  in intel_dp_output_format()
1170 		    (!drm_dp_is_branch(intel_dp->dpcd) ||  in intel_dp_output_format()
1175 		drm_dbg_kms(display->drm, "Cannot force DSC output format\n");  in intel_dp_output_format()
1189 	drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));  in intel_dp_output_format()
1216 intel_dp_sink_format(struct intel_connector *connector,  in intel_dp_sink_format()  argument
1219 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_sink_format()
1228 intel_dp_mode_min_output_bpp(struct intel_connector *connector,  in intel_dp_mode_min_output_bpp()  argument
1233 	sink_format = intel_dp_sink_format(connector, mode);  in intel_dp_mode_min_output_bpp()
1235 	output_format = intel_dp_output_format(connector, sink_format);  in intel_dp_mode_min_output_bpp()
1244 	 * Older platforms don't like hdisplay==4096 with DP.  in intel_dp_hdisplay_bad()
1261 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_max_tmds_clock()  local
1262 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_max_tmds_clock()
1263 	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;  in intel_dp_max_tmds_clock()
1266 	if (max_tmds_clock && info->max_tmds_clock)  in intel_dp_max_tmds_clock()
1267 		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);  in intel_dp_max_tmds_clock()
1285 	min_tmds_clock = intel_dp->dfp.min_tmds_clock;  in intel_dp_tmds_clock_valid()
1298 intel_dp_mode_valid_downstream(struct intel_connector *connector,  in intel_dp_mode_valid_downstream()  argument
1302 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_mode_valid_downstream()
1303 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_mode_valid_downstream()
1308 	if (intel_dp->dfp.pcon_max_frl_bw) {  in intel_dp_mode_valid_downstream()
1311 		int bpp = intel_dp_mode_min_output_bpp(connector, mode);  in intel_dp_mode_valid_downstream()
1315 		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;  in intel_dp_mode_valid_downstream()
1326 	if (intel_dp->dfp.max_dotclock &&  in intel_dp_mode_valid_downstream()
1327 	    target_clock > intel_dp->dfp.max_dotclock)  in intel_dp_mode_valid_downstream()
1330 	sink_format = intel_dp_sink_format(connector, mode);  in intel_dp_mode_valid_downstream()
1332 	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */  in intel_dp_mode_valid_downstream()
1338 		    !connector->base.ycbcr_420_allowed ||  in intel_dp_mode_valid_downstream()
1353 			   struct intel_connector *connector,  in intel_dp_needs_joiner()  argument
1367 	return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||  in intel_dp_needs_joiner()
1372 			      struct intel_connector *connector,  in intel_dp_num_joined_pipes()  argument
1377 	if (connector->force_joined_pipes)  in intel_dp_num_joined_pipes()
1378 		return connector->force_joined_pipes;  in intel_dp_num_joined_pipes()
1381 	    intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))  in intel_dp_num_joined_pipes()
1385 	    intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))  in intel_dp_num_joined_pipes()
1391 bool intel_dp_has_dsc(const struct intel_connector *connector)  in intel_dp_has_dsc()  argument
1393 	struct intel_display *display = to_intel_display(connector);  in intel_dp_has_dsc()
1398 	if (connector->mst.dp && !HAS_DSC_MST(display))  in intel_dp_has_dsc()
1401 	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&  in intel_dp_has_dsc()
1402 	    connector->panel.vbt.edp.dsc_disable)  in intel_dp_has_dsc()
1405 	if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))  in intel_dp_has_dsc()
1415 	struct intel_display *display = to_intel_display(_connector->dev);  in intel_dp_mode_valid()
1416 	struct intel_connector *connector = to_intel_connector(_connector);  in intel_dp_mode_valid()  local
1417 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_mode_valid()
1419 	int target_clock = mode->clock;  in intel_dp_mode_valid()
1421 	int max_dotclk = display->cdclk.max_dotclk_freq;  in intel_dp_mode_valid()
1432 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)  in intel_dp_mode_valid()
1435 	if (mode->clock < 10000)  in intel_dp_mode_valid()
1438 	fixed_mode = intel_panel_fixed_mode(connector, mode);  in intel_dp_mode_valid()
1440 		status = intel_panel_mode_valid(connector, mode);  in intel_dp_mode_valid()
1444 		target_clock = fixed_mode->clock;  in intel_dp_mode_valid()
1447 	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,  in intel_dp_mode_valid()
1448 						     mode->hdisplay, target_clock);  in intel_dp_mode_valid()
1454 	if (intel_dp_hdisplay_bad(display, mode->hdisplay))  in intel_dp_mode_valid()
1463 					   intel_dp_mode_min_output_bpp(connector, mode));  in intel_dp_mode_valid()
1465 	if (intel_dp_has_dsc(connector)) {  in intel_dp_mode_valid()
1469 		sink_format = intel_dp_sink_format(connector, mode);  in intel_dp_mode_valid()
1470 		output_format = intel_dp_output_format(connector, sink_format);  in intel_dp_mode_valid()
1472 		 * TBD pass the connector BPC,  in intel_dp_mode_valid()
1475 		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);  in intel_dp_mode_valid()
1483 				drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;  in intel_dp_mode_valid()
1485 				drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,  in intel_dp_mode_valid()
1487 		} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {  in intel_dp_mode_valid()
1493 								    mode->hdisplay,  in intel_dp_mode_valid()
1498 				intel_dp_dsc_get_slice_count(connector,  in intel_dp_mode_valid()
1500 							     mode->hdisplay,  in intel_dp_mode_valid()
1513 	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);  in intel_dp_mode_valid()
1523 		display->platform.broadwell || display->platform.haswell;  in intel_dp_source_supports_tps3()
1547 	seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates);  in intel_dp_print_rates()
1548 	drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));  in intel_dp_print_rates()
1551 	seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates);  in intel_dp_print_rates()
1552 	drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));  in intel_dp_print_rates()
1555 	seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates);  in intel_dp_print_rates()
1556 	drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));  in intel_dp_print_rates()
1561 	int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);  in forced_link_rate()
1566 	return intel_dp_common_rate(intel_dp, len - 1);  in forced_link_rate()
1574 	if (intel_dp->link.force_rate)  in intel_dp_max_link_rate()
1577 	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);  in intel_dp_max_link_rate()
1579 	return intel_dp_common_rate(intel_dp, len - 1);  in intel_dp_max_link_rate()
1585 	if (intel_dp->link.force_rate)  in intel_dp_min_link_rate()
1594 	int i = intel_dp_rate_index(intel_dp->sink_rates,  in intel_dp_rate_select()
1595 				    intel_dp->num_sink_rates, rate);  in intel_dp_rate_select()
1597 	if (drm_WARN_ON(display->drm, i < 0))  in intel_dp_rate_select()
1607 	if (intel_dp->use_rate_select) {  in intel_dp_compute_rate()
1619 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_has_hdmi_sink()  local
1621 	return connector->base.display_info.is_hdmi;  in intel_dp_has_hdmi_sink()
1628 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_source_supports_fec()
1633 	if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&  in intel_dp_source_supports_fec()
1641 			   const struct intel_connector *connector,  in intel_dp_supports_fec()  argument
1645 		drm_dp_sink_supports_fec(connector->dp.fec_capability);  in intel_dp_supports_fec()
1649 			   const struct intel_connector *connector,  in intel_dp_supports_dsc()  argument
1652 	if (!intel_dp_has_dsc(connector))  in intel_dp_supports_dsc()
1656 	    !intel_dp_supports_fec(intel_dp, connector, crtc_state))  in intel_dp_supports_dsc()
1666 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;  in intel_dp_hdmi_compute_bpc()
1683 	for (; bpc >= 8; bpc -= 2) {  in intel_dp_hdmi_compute_bpc()
1686 		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,  in intel_dp_hdmi_compute_bpc()
1691 	return -EINVAL;  in intel_dp_hdmi_compute_bpc()
1699 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_max_bpp()  local
1702 	bpc = crtc_state->pipe_bpp / 3;  in intel_dp_max_bpp()
1704 	if (intel_dp->dfp.max_bpc)  in intel_dp_max_bpp()
1705 		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);  in intel_dp_max_bpp()
1707 	if (intel_dp->dfp.min_tmds_clock) {  in intel_dp_max_bpp()
1721 		if (connector->base.display_info.bpc == 0 &&  in intel_dp_max_bpp()
1722 		    connector->panel.vbt.edp.bpp &&  in intel_dp_max_bpp()
1723 		    connector->panel.vbt.edp.bpp < bpp) {  in intel_dp_max_bpp()
1724 			drm_dbg_kms(display->drm,  in intel_dp_max_bpp()
1725 				    "clamping bpp for eDP panel to BIOS-provided %i\n",  in intel_dp_max_bpp()
1726 				    connector->panel.vbt.edp.bpp);  in intel_dp_max_bpp()
1727 			bpp = connector->panel.vbt.edp.bpp;  in intel_dp_max_bpp()
1734 static bool has_seamless_m_n(struct intel_connector *connector)  in has_seamless_m_n()  argument
1736 	struct intel_display *display = to_intel_display(connector);  in has_seamless_m_n()
1743 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;  in has_seamless_m_n()
1749 	struct intel_connector *connector = to_intel_connector(conn_state->connector);  in intel_dp_mode_clock()  local
1750 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_dp_mode_clock()
1753 	if (has_seamless_m_n(connector))  in intel_dp_mode_clock()
1754 		return intel_panel_highest_mode(connector, adjusted_mode)->clock;  in intel_dp_mode_clock()
1756 		return adjusted_mode->crtc_clock;  in intel_dp_mode_clock()
1769 	for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);  in intel_dp_compute_link_config_wide()
1770 	     bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);  in intel_dp_compute_link_config_wide()
1771 	     bpp -= 2 * 3) {  in intel_dp_compute_link_config_wide()
1772 		int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);  in intel_dp_compute_link_config_wide()
1776 		for (i = 0; i < intel_dp->num_common_rates; i++) {  in intel_dp_compute_link_config_wide()
1778 			if (link_rate < limits->min_rate ||  in intel_dp_compute_link_config_wide()
1779 			    link_rate > limits->max_rate)  in intel_dp_compute_link_config_wide()
1782 			for (lane_count = limits->min_lane_count;  in intel_dp_compute_link_config_wide()
1783 			     lane_count <= limits->max_lane_count;  in intel_dp_compute_link_config_wide()
1791 					pipe_config->lane_count = lane_count;  in intel_dp_compute_link_config_wide()
1792 					pipe_config->pipe_bpp = bpp;  in intel_dp_compute_link_config_wide()
1793 					pipe_config->port_clock = link_rate;  in intel_dp_compute_link_config_wide()
1801 	return -EINVAL;  in intel_dp_compute_link_config_wide()
1815 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,  in intel_dp_dsc_compute_max_bpp()  argument
1818 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_compute_max_bpp()
1830 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,  in intel_dp_dsc_compute_max_bpp()
1847 	return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>  in intel_dp_sink_dsc_version_minor()
1873 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,  in intel_dp_dsc_compute_params()  argument
1876 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_compute_params()
1877 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dp_dsc_compute_params()
1886 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;  in intel_dp_dsc_compute_params()
1887 	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;  in intel_dp_dsc_compute_params()
1889 	vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);  in intel_dp_dsc_compute_params()
1895 	vdsc_cfg->dsc_version_major =  in intel_dp_dsc_compute_params()
1896 		(connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1898 	vdsc_cfg->dsc_version_minor =  in intel_dp_dsc_compute_params()
1900 		    intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));  in intel_dp_dsc_compute_params()
1901 	if (vdsc_cfg->convert_rgb)  in intel_dp_dsc_compute_params()
1902 		vdsc_cfg->convert_rgb =  in intel_dp_dsc_compute_params()
1903 			connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1906 	vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,  in intel_dp_dsc_compute_params()
1907 				       drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));  in intel_dp_dsc_compute_params()
1908 	if (!vdsc_cfg->line_buf_depth) {  in intel_dp_dsc_compute_params()
1909 		drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_params()
1911 		return -EINVAL;  in intel_dp_dsc_compute_params()
1914 	vdsc_cfg->block_pred_enable =  in intel_dp_dsc_compute_params()
1915 		connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1921 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,  in intel_dp_dsc_supports_format()  argument
1924 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_supports_format()
1936 			intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)  in intel_dp_dsc_supports_format()
1944 	return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);  in intel_dp_dsc_supports_format()
1967 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in dsc_compute_link_config()
1971 	for (i = 0; i < intel_dp->num_common_rates; i++) {  in dsc_compute_link_config()
1973 		if (link_rate < limits->min_rate || link_rate > limits->max_rate)  in dsc_compute_link_config()
1976 		for (lane_count = limits->min_lane_count;  in dsc_compute_link_config()
1977 		     lane_count <= limits->max_lane_count;  in dsc_compute_link_config()
1982 			 * ->lane_count and ->port_clock set before we know  in dsc_compute_link_config()
1988 			pipe_config->lane_count = lane_count;  in dsc_compute_link_config()
1989 			pipe_config->port_clock = link_rate;  in dsc_compute_link_config()
2004 								     lane_count, adjusted_mode->clock,  in dsc_compute_link_config()
2005 								     pipe_config->output_format,  in dsc_compute_link_config()
2014 	return -EINVAL;  in dsc_compute_link_config()
2018 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,  in intel_dp_dsc_max_sink_compressed_bppx16()  argument
2022 	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);  in intel_dp_dsc_max_sink_compressed_bppx16()
2028 	 * values as given in spec Table 2-157 DP v2.0  in intel_dp_dsc_max_sink_compressed_bppx16()
2030 	switch (pipe_config->output_format) {  in intel_dp_dsc_max_sink_compressed_bppx16()
2037 		MISSING_CASE(pipe_config->output_format);  in intel_dp_dsc_max_sink_compressed_bppx16()
2046 	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */  in intel_dp_dsc_sink_min_compressed_bpp()
2047 	switch (pipe_config->output_format) {  in intel_dp_dsc_sink_min_compressed_bpp()
2054 		MISSING_CASE(pipe_config->output_format);  in intel_dp_dsc_sink_min_compressed_bpp()
2061 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,  in intel_dp_dsc_sink_max_compressed_bpp()  argument
2065 	return intel_dp_dsc_max_sink_compressed_bppx16(connector,  in intel_dp_dsc_sink_max_compressed_bpp()
2085 	if (intel_dp->force_dsc_en)  in dsc_src_max_compressed_bpp()
2099  * Note: for pre-13 display you still need to check the validity of each step.
2101 static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector)  in intel_dp_dsc_bpp_step_x16()  argument
2103 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_bpp_step_x16()
2104 	u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);  in intel_dp_dsc_bpp_step_x16()
2120 		if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16))  in intel_dp_dsc_valid_bpp()
2149 	const struct intel_connector *connector = to_intel_connector(conn_state->connector);  in dsc_compute_compressed_bpp()  local
2150 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in dsc_compute_compressed_bpp()
2160 	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);  in dsc_compute_compressed_bpp()
2162 	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,  in dsc_compute_compressed_bpp()
2163 								adjusted_mode->hdisplay,  in dsc_compute_compressed_bpp()
2165 	dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));  in dsc_compute_compressed_bpp()
2171 	bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector);  in dsc_compute_compressed_bpp()
2174 	output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);  in dsc_compute_compressed_bpp()
2175 	max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16);  in dsc_compute_compressed_bpp()
2177 	for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) {  in dsc_compute_compressed_bpp()
2188 			pipe_config->dsc.compressed_bpp_x16 = bpp_x16;  in dsc_compute_compressed_bpp()
2189 			if (intel_dp->force_dsc_fractional_bpp_en &&  in dsc_compute_compressed_bpp()
2191 				drm_dbg_kms(display->drm,  in dsc_compute_compressed_bpp()
2198 	return -EINVAL;  in dsc_compute_compressed_bpp()
2211 	return pipe_bpp >= limits->pipe.min_bpp &&  in is_dsc_pipe_bpp_sufficient()
2212 	       pipe_bpp <= limits->pipe.max_bpp;  in is_dsc_pipe_bpp_sufficient()
2222 	if (!intel_dp->force_dsc_bpc)  in intel_dp_force_dsc_pipe_bpp()
2225 	forced_bpp = intel_dp->force_dsc_bpc * 3;  in intel_dp_force_dsc_pipe_bpp()
2228 		drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",  in intel_dp_force_dsc_pipe_bpp()
2229 			    intel_dp->force_dsc_bpc);  in intel_dp_force_dsc_pipe_bpp()
2233 	drm_dbg_kms(display->drm,  in intel_dp_force_dsc_pipe_bpp()
2235 		    intel_dp->force_dsc_bpc);  in intel_dp_force_dsc_pipe_bpp()
2246 	const struct intel_connector *connector =  in intel_dp_dsc_compute_pipe_bpp()  local
2247 		to_intel_connector(conn_state->connector);  in intel_dp_dsc_compute_pipe_bpp()
2258 			pipe_config->pipe_bpp = forced_bpp;  in intel_dp_dsc_compute_pipe_bpp()
2267 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);  in intel_dp_dsc_compute_pipe_bpp()
2270 		if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp)  in intel_dp_dsc_compute_pipe_bpp()
2276 			pipe_config->pipe_bpp = pipe_bpp;  in intel_dp_dsc_compute_pipe_bpp()
2281 	return -EINVAL;  in intel_dp_dsc_compute_pipe_bpp()
2290 	struct intel_connector *connector =  in intel_edp_dsc_compute_pipe_bpp()  local
2291 		to_intel_connector(conn_state->connector);  in intel_edp_dsc_compute_pipe_bpp()
2301 		int max_bpc = limits->pipe.max_bpp / 3;  in intel_edp_dsc_compute_pipe_bpp()
2304 		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);  in intel_edp_dsc_compute_pipe_bpp()
2306 			drm_dbg_kms(display->drm,  in intel_edp_dsc_compute_pipe_bpp()
2308 			return -EINVAL;  in intel_edp_dsc_compute_pipe_bpp()
2311 	pipe_config->port_clock = limits->max_rate;  in intel_edp_dsc_compute_pipe_bpp()
2312 	pipe_config->lane_count = limits->max_lane_count;  in intel_edp_dsc_compute_pipe_bpp()
2314 	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);  in intel_edp_dsc_compute_pipe_bpp()
2316 	dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16);  in intel_edp_dsc_compute_pipe_bpp()
2319 	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);  in intel_edp_dsc_compute_pipe_bpp()
2321 	pipe_config->dsc.compressed_bpp_x16 =  in intel_edp_dsc_compute_pipe_bpp()
2324 	pipe_config->pipe_bpp = pipe_bpp;  in intel_edp_dsc_compute_pipe_bpp()
2332 	if (crtc_state->fec_enable)  in intel_dp_fec_compute_config()
2336 	 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.  in intel_dp_fec_compute_config()
2346 	crtc_state->fec_enable = true;  in intel_dp_fec_compute_config()
2356 	const struct intel_connector *connector =  in intel_dp_dsc_compute_config()  local
2357 		to_intel_connector(conn_state->connector);  in intel_dp_dsc_compute_config()
2359 		&pipe_config->hw.adjusted_mode;  in intel_dp_dsc_compute_config()
2366 	if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))  in intel_dp_dsc_compute_config()
2367 		return -EINVAL;  in intel_dp_dsc_compute_config()
2371 	 * figured out for DP MST DSC.  in intel_dp_dsc_compute_config()
2381 			drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_config()
2389 		pipe_config->dsc.slice_count =  in intel_dp_dsc_compute_config()
2390 			drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,  in intel_dp_dsc_compute_config()
2392 		if (!pipe_config->dsc.slice_count) {  in intel_dp_dsc_compute_config()
2393 			drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_config()
2395 				    pipe_config->dsc.slice_count);  in intel_dp_dsc_compute_config()
2396 			return -EINVAL;  in intel_dp_dsc_compute_config()
2402 			intel_dp_dsc_get_slice_count(connector,  in intel_dp_dsc_compute_config()
2403 						     adjusted_mode->crtc_clock,  in intel_dp_dsc_compute_config()
2404 						     adjusted_mode->crtc_hdisplay,  in intel_dp_dsc_compute_config()
2407 			drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_config()
2409 			return -EINVAL;  in intel_dp_dsc_compute_config()
2412 		pipe_config->dsc.slice_count = dsc_dp_slice_count;  in intel_dp_dsc_compute_config()
2421 	if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&  in intel_dp_dsc_compute_config()
2422 	    pipe_config->dsc.slice_count == 12)  in intel_dp_dsc_compute_config()
2423 		pipe_config->dsc.num_streams = 3;  in intel_dp_dsc_compute_config()
2424 	else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)  in intel_dp_dsc_compute_config()
2425 		pipe_config->dsc.num_streams = 2;  in intel_dp_dsc_compute_config()
2427 		pipe_config->dsc.num_streams = 1;  in intel_dp_dsc_compute_config()
2429 	ret = intel_dp_dsc_compute_params(connector, pipe_config);  in intel_dp_dsc_compute_config()
2431 		drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_config()
2434 			    pipe_config->pipe_bpp,  in intel_dp_dsc_compute_config()
2435 			    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));  in intel_dp_dsc_compute_config()
2439 	pipe_config->dsc.compression_enable = true;  in intel_dp_dsc_compute_config()
2440 	drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "  in intel_dp_dsc_compute_config()
2442 		    pipe_config->pipe_bpp,  in intel_dp_dsc_compute_config()
2443 		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),  in intel_dp_dsc_compute_config()
2444 		    pipe_config->dsc.slice_count);  in intel_dp_dsc_compute_config()
2455 					const struct intel_connector *connector,  in intel_dp_compute_config_link_bpp_limits()  argument
2462 		&crtc_state->hw.adjusted_mode;  in intel_dp_compute_config_link_bpp_limits()
2463 	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_dp_compute_config_link_bpp_limits()
2464 	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_compute_config_link_bpp_limits()
2467 	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,  in intel_dp_compute_config_link_bpp_limits()
2468 			       fxp_q4_from_int(limits->pipe.max_bpp));  in intel_dp_compute_config_link_bpp_limits()
2473 		if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))  in intel_dp_compute_config_link_bpp_limits()
2476 		limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);  in intel_dp_compute_config_link_bpp_limits()
2484 		limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);  in intel_dp_compute_config_link_bpp_limits()
2487 		dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,  in intel_dp_compute_config_link_bpp_limits()
2489 									limits->pipe.max_bpp / 3);  in intel_dp_compute_config_link_bpp_limits()
2496 	limits->link.max_bpp_x16 = max_link_bpp_x16;  in intel_dp_compute_config_link_bpp_limits()
2498 	drm_dbg_kms(display->drm,  in intel_dp_compute_config_link_bpp_limits()
2499 …"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d ma…  in intel_dp_compute_config_link_bpp_limits()
2500 		    encoder->base.base.id, encoder->base.name,  in intel_dp_compute_config_link_bpp_limits()
2501 		    crtc->base.base.id, crtc->base.name,  in intel_dp_compute_config_link_bpp_limits()
2502 		    adjusted_mode->crtc_clock,  in intel_dp_compute_config_link_bpp_limits()
2504 		    limits->max_lane_count,  in intel_dp_compute_config_link_bpp_limits()
2505 		    limits->max_rate,  in intel_dp_compute_config_link_bpp_limits()
2506 		    limits->pipe.max_bpp,  in intel_dp_compute_config_link_bpp_limits()
2507 		    FXP_Q4_ARGS(limits->link.max_bpp_x16));  in intel_dp_compute_config_link_bpp_limits()
2520 	limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);  in intel_dp_dsc_compute_pipe_bpp_limits()
2521 	limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);  in intel_dp_dsc_compute_pipe_bpp_limits()
2533 	limits->min_rate = intel_dp_min_link_rate(intel_dp);  in intel_dp_compute_config_limits()
2534 	limits->max_rate = intel_dp_max_link_rate(intel_dp);  in intel_dp_compute_config_limits()
2536 	limits->min_rate = min(limits->min_rate, limits->max_rate);  in intel_dp_compute_config_limits()
2538 	limits->min_lane_count = intel_dp_min_lane_count(intel_dp);  in intel_dp_compute_config_limits()
2539 	limits->max_lane_count = intel_dp_max_lane_count(intel_dp);  in intel_dp_compute_config_limits()
2541 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);  in intel_dp_compute_config_limits()
2551 		limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);  in intel_dp_compute_config_limits()
2553 		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,  in intel_dp_compute_config_limits()
2560 	if (is_mst || intel_dp->use_max_params) {  in intel_dp_compute_config_limits()
2562 		 * For MST we always configure max link bw - the spec doesn't  in intel_dp_compute_config_limits()
2572 		limits->min_lane_count = limits->max_lane_count;  in intel_dp_compute_config_limits()
2573 		limits->min_rate = limits->max_rate;  in intel_dp_compute_config_limits()
2579 						       intel_dp->attached_connector,  in intel_dp_compute_config_limits()
2588 		&crtc_state->hw.adjusted_mode;  in intel_dp_config_required_rate()
2589 	int bpp = crtc_state->dsc.compression_enable ?  in intel_dp_config_required_rate()
2590 		fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :  in intel_dp_config_required_rate()
2591 		crtc_state->pipe_bpp;  in intel_dp_config_required_rate()
2593 	return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);  in intel_dp_config_required_rate()
2616 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_dp_compute_link_config()
2617 	struct intel_connector *connector =  in intel_dp_compute_link_config()  local
2618 		to_intel_connector(conn_state->connector);  in intel_dp_compute_link_config()
2620 		&pipe_config->hw.adjusted_mode;  in intel_dp_compute_link_config()
2627 	if (pipe_config->fec_enable &&  in intel_dp_compute_link_config()
2628 	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))  in intel_dp_compute_link_config()
2629 		return -EINVAL;  in intel_dp_compute_link_config()
2631 	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,  in intel_dp_compute_link_config()
2632 						     adjusted_mode->crtc_hdisplay,  in intel_dp_compute_link_config()
2633 						     adjusted_mode->crtc_clock);  in intel_dp_compute_link_config()
2635 		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);  in intel_dp_compute_link_config()
2639 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||  in intel_dp_compute_link_config()
2656 							     fxp_q4_from_int(pipe_config->pipe_bpp),  in intel_dp_compute_link_config()
2657 							     fxp_q4_from_int(pipe_config->pipe_bpp),  in intel_dp_compute_link_config()
2663 	if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {  in intel_dp_compute_link_config()
2664 		drm_dbg_kms(display->drm, "DSC required but not available\n");  in intel_dp_compute_link_config()
2665 		return -EINVAL;  in intel_dp_compute_link_config()
2669 		drm_dbg_kms(display->drm,  in intel_dp_compute_link_config()
2672 			    str_yes_no(intel_dp->force_dsc_en));  in intel_dp_compute_link_config()
2678 			return -EINVAL;  in intel_dp_compute_link_config()
2686 	drm_dbg_kms(display->drm,  in intel_dp_compute_link_config()
2687 …"DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available …  in intel_dp_compute_link_config()
2688 		    pipe_config->lane_count, pipe_config->port_clock,  in intel_dp_compute_link_config()
2689 		    pipe_config->pipe_bpp,  in intel_dp_compute_link_config()
2690 		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),  in intel_dp_compute_link_config()
2693 						pipe_config->port_clock,  in intel_dp_compute_link_config()
2694 						pipe_config->lane_count));  in intel_dp_compute_link_config()
2705 		&crtc_state->hw.adjusted_mode;  in intel_dp_limited_color_range()
2709 	 * crtc_state->limited_color_range only applies to RGB,  in intel_dp_limited_color_range()
2714 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in intel_dp_limited_color_range()
2717 	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {  in intel_dp_limited_color_range()
2720 		 * CEA-861-E - 5.1 Default Encoding Parameters  in intel_dp_limited_color_range()
2721 		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry  in intel_dp_limited_color_range()
2723 		return crtc_state->pipe_bpp != 18 &&  in intel_dp_limited_color_range()
2727 		return intel_conn_state->broadcast_rgb ==  in intel_dp_limited_color_range()
2734 	if (display->platform.g4x)  in intel_dp_port_has_audio()
2748 	if (crtc_state->has_panel_replay) {  in intel_dp_compute_vsc_colorimetry()
2750 		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223  in intel_dp_compute_vsc_colorimetry()
2754 		vsc->revision = 0x7;  in intel_dp_compute_vsc_colorimetry()
2757 		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118  in intel_dp_compute_vsc_colorimetry()
2761 		vsc->revision = 0x5;  in intel_dp_compute_vsc_colorimetry()
2764 	vsc->length = 0x13;  in intel_dp_compute_vsc_colorimetry()
2766 	/* DP 1.4a spec, Table 2-120 */  in intel_dp_compute_vsc_colorimetry()
2767 	switch (crtc_state->output_format) {  in intel_dp_compute_vsc_colorimetry()
2769 		vsc->pixelformat = DP_PIXELFORMAT_YUV444;  in intel_dp_compute_vsc_colorimetry()
2772 		vsc->pixelformat = DP_PIXELFORMAT_YUV420;  in intel_dp_compute_vsc_colorimetry()
2776 		vsc->pixelformat = DP_PIXELFORMAT_RGB;  in intel_dp_compute_vsc_colorimetry()
2779 	switch (conn_state->colorspace) {  in intel_dp_compute_vsc_colorimetry()
2781 		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;  in intel_dp_compute_vsc_colorimetry()
2784 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;  in intel_dp_compute_vsc_colorimetry()
2787 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;  in intel_dp_compute_vsc_colorimetry()
2790 		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;  in intel_dp_compute_vsc_colorimetry()
2793 		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;  in intel_dp_compute_vsc_colorimetry()
2796 		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;  in intel_dp_compute_vsc_colorimetry()
2799 		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;  in intel_dp_compute_vsc_colorimetry()
2802 		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;  in intel_dp_compute_vsc_colorimetry()
2806 		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;  in intel_dp_compute_vsc_colorimetry()
2810 		 * RGB->YCBCR color conversion uses the BT.709  in intel_dp_compute_vsc_colorimetry()
2813 		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in intel_dp_compute_vsc_colorimetry()
2814 			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;  in intel_dp_compute_vsc_colorimetry()
2816 			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;  in intel_dp_compute_vsc_colorimetry()
2820 	vsc->bpc = crtc_state->pipe_bpp / 3;  in intel_dp_compute_vsc_colorimetry()
2823 	drm_WARN_ON(display->drm,  in intel_dp_compute_vsc_colorimetry()
2824 		    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);  in intel_dp_compute_vsc_colorimetry()
2827 	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;  in intel_dp_compute_vsc_colorimetry()
2828 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;  in intel_dp_compute_vsc_colorimetry()
2834 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;  in intel_dp_compute_as_sdp()
2836 		&crtc_state->hw.adjusted_mode;  in intel_dp_compute_as_sdp()
2838 	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)  in intel_dp_compute_as_sdp()
2841 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);  in intel_dp_compute_as_sdp()
2843 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;  in intel_dp_compute_as_sdp()
2844 	as_sdp->length = 0x9;  in intel_dp_compute_as_sdp()
2845 	as_sdp->duration_incr_ms = 0;  in intel_dp_compute_as_sdp()
2846 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);  in intel_dp_compute_as_sdp()
2848 	if (crtc_state->cmrr.enable) {  in intel_dp_compute_as_sdp()
2849 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;  in intel_dp_compute_as_sdp()
2850 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);  in intel_dp_compute_as_sdp()
2851 		as_sdp->target_rr_divider = true;  in intel_dp_compute_as_sdp()
2853 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;  in intel_dp_compute_as_sdp()
2854 		as_sdp->target_rr = 0;  in intel_dp_compute_as_sdp()
2864 	if ((!intel_dp->colorimetry_support ||  in intel_dp_compute_vsc_sdp()
2866 	    !crtc_state->has_psr)  in intel_dp_compute_vsc_sdp()
2869 	vsc = &crtc_state->infoframes.vsc;  in intel_dp_compute_vsc_sdp()
2871 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);  in intel_dp_compute_vsc_sdp()
2872 	vsc->sdp_type = DP_SDP_VSC;  in intel_dp_compute_vsc_sdp()
2878 	} else if (crtc_state->has_panel_replay) {  in intel_dp_compute_vsc_sdp()
2881 		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223  in intel_dp_compute_vsc_sdp()
2884 		vsc->revision = 0x6;  in intel_dp_compute_vsc_sdp()
2885 		vsc->length = 0x10;  in intel_dp_compute_vsc_sdp()
2886 	} else if (crtc_state->has_sel_update) {  in intel_dp_compute_vsc_sdp()
2889 		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11  in intel_dp_compute_vsc_sdp()
2890 		 * 3D stereo + PSR/PSR2 + Y-coordinate.  in intel_dp_compute_vsc_sdp()
2892 		vsc->revision = 0x4;  in intel_dp_compute_vsc_sdp()
2893 		vsc->length = 0xe;  in intel_dp_compute_vsc_sdp()
2897 		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118  in intel_dp_compute_vsc_sdp()
2901 		vsc->revision = 0x2;  in intel_dp_compute_vsc_sdp()
2902 		vsc->length = 0x8;  in intel_dp_compute_vsc_sdp()
2913 	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2915 	if (!conn_state->hdr_output_metadata)  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2921 		drm_dbg_kms(display->drm,  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2926 	crtc_state->infoframes.enable |=  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2930 static bool can_enable_drrs(struct intel_connector *connector,  in can_enable_drrs()  argument
2934 	struct intel_display *display = to_intel_display(connector);  in can_enable_drrs()
2936 	if (pipe_config->vrr.enable)  in can_enable_drrs()
2941 	 * as it allows more power-savings by complete shutting down display,  in can_enable_drrs()
2945 	if (pipe_config->has_psr)  in can_enable_drrs()
2949 	if (pipe_config->has_pch_encoder)  in can_enable_drrs()
2952 	if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder))  in can_enable_drrs()
2956 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;  in can_enable_drrs()
2960 intel_dp_drrs_compute_config(struct intel_connector *connector,  in intel_dp_drrs_compute_config()  argument
2964 	struct intel_display *display = to_intel_display(connector);  in intel_dp_drrs_compute_config()
2966 		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);  in intel_dp_drrs_compute_config()
2973 	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)  in intel_dp_drrs_compute_config()
2974 		pipe_config->update_m_n = true;  in intel_dp_drrs_compute_config()
2976 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {  in intel_dp_drrs_compute_config()
2977 		if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder))  in intel_dp_drrs_compute_config()
2978 			intel_zero_m_n(&pipe_config->dp_m2_n2);  in intel_dp_drrs_compute_config()
2982 	if (display->platform.ironlake || display->platform.sandybridge ||  in intel_dp_drrs_compute_config()
2983 	    display->platform.ivybridge)  in intel_dp_drrs_compute_config()
2984 		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;  in intel_dp_drrs_compute_config()
2986 	pipe_config->has_drrs = true;  in intel_dp_drrs_compute_config()
2988 	pixel_clock = downclock_mode->clock;  in intel_dp_drrs_compute_config()
2989 	if (pipe_config->splitter.enable)  in intel_dp_drrs_compute_config()
2990 		pixel_clock /= pipe_config->splitter.link_count;  in intel_dp_drrs_compute_config()
2992 	intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,  in intel_dp_drrs_compute_config()
2993 			       pipe_config->port_clock,  in intel_dp_drrs_compute_config()
2994 			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),  in intel_dp_drrs_compute_config()
2995 			       &pipe_config->dp_m2_n2);  in intel_dp_drrs_compute_config()
2998 	if (pipe_config->splitter.enable)  in intel_dp_drrs_compute_config()
2999 		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;  in intel_dp_drrs_compute_config()
3008 	struct intel_connector *connector =  in intel_dp_has_audio()  local
3009 		to_intel_connector(conn_state->connector);  in intel_dp_has_audio()
3011 	if (!intel_dp_port_has_audio(display, encoder->port))  in intel_dp_has_audio()
3014 	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)  in intel_dp_has_audio()
3015 		return connector->base.display_info.has_audio;  in intel_dp_has_audio()
3017 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;  in intel_dp_has_audio()
3028 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_compute_output_format()  local
3029 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_compute_output_format()
3030 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_dp_compute_output_format()
3036 	if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {  in intel_dp_compute_output_format()
3037 		drm_dbg_kms(display->drm,  in intel_dp_compute_output_format()
3039 		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;  in intel_dp_compute_output_format()
3041 		crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);  in intel_dp_compute_output_format()
3044 	crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);  in intel_dp_compute_output_format()
3049 		if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in intel_dp_compute_output_format()
3050 		    !connector->base.ycbcr_420_allowed ||  in intel_dp_compute_output_format()
3054 		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;  in intel_dp_compute_output_format()
3055 		crtc_state->output_format = intel_dp_output_format(connector,  in intel_dp_compute_output_format()
3056 								   crtc_state->sink_format);  in intel_dp_compute_output_format()
3069 	pipe_config->has_audio =  in intel_dp_audio_compute_config()
3073 	pipe_config->sdp_split_enable = pipe_config->has_audio &&  in intel_dp_audio_compute_config()
3082 	struct intel_connector *connector;  in intel_dp_queue_modeset_retry_for_link()  local
3087 	if (intel_dp->needs_modeset_retry)  in intel_dp_queue_modeset_retry_for_link()
3090 	intel_dp->needs_modeset_retry = true;  in intel_dp_queue_modeset_retry_for_link()
3093 		intel_connector_queue_modeset_retry_work(intel_dp->attached_connector);  in intel_dp_queue_modeset_retry_for_link()
3098 	for_each_new_intel_connector_in_state(state, connector, conn_state, i) {  in intel_dp_queue_modeset_retry_for_link()
3099 		if (!conn_state->base.crtc)  in intel_dp_queue_modeset_retry_for_link()
3102 		if (connector->mst.dp == intel_dp)  in intel_dp_queue_modeset_retry_for_link()
3103 			intel_connector_queue_modeset_retry_work(connector);  in intel_dp_queue_modeset_retry_for_link()
3113 	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);  in intel_dp_compute_config()
3114 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_dp_compute_config()
3117 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_compute_config()  local
3120 	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);  in intel_dp_compute_config()
3122 		ret = intel_panel_compute_config(connector, adjusted_mode);  in intel_dp_compute_config()
3127 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)  in intel_dp_compute_config()
3128 		return -EINVAL;  in intel_dp_compute_config()
3130 	if (!connector->base.interlace_allowed &&  in intel_dp_compute_config()
3131 	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)  in intel_dp_compute_config()
3132 		return -EINVAL;  in intel_dp_compute_config()
3134 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)  in intel_dp_compute_config()
3135 		return -EINVAL;  in intel_dp_compute_config()
3137 	if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))  in intel_dp_compute_config()
3138 		return -EINVAL;  in intel_dp_compute_config()
3151 	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {  in intel_dp_compute_config()
3157 	pipe_config->limited_color_range =  in intel_dp_compute_config()
3162 		pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;  in intel_dp_compute_config()
3164 		pipe_config->enhanced_framing =  in intel_dp_compute_config()
3165 			drm_dp_enhanced_frame_cap(intel_dp->dpcd);  in intel_dp_compute_config()
3168 	if (pipe_config->dsc.compression_enable)  in intel_dp_compute_config()
3169 		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;  in intel_dp_compute_config()
3171 		link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,  in intel_dp_compute_config()
3172 								   pipe_config->pipe_bpp));  in intel_dp_compute_config()
3174 	if (intel_dp->mso_link_count) {  in intel_dp_compute_config()
3175 		int n = intel_dp->mso_link_count;  in intel_dp_compute_config()
3176 		int overlap = intel_dp->mso_pixel_overlap;  in intel_dp_compute_config()
3178 		pipe_config->splitter.enable = true;  in intel_dp_compute_config()
3179 		pipe_config->splitter.link_count = n;  in intel_dp_compute_config()
3180 		pipe_config->splitter.pixel_overlap = overlap;  in intel_dp_compute_config()
3182 		drm_dbg_kms(display->drm,  in intel_dp_compute_config()
3186 		adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;  in intel_dp_compute_config()
3187 		adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;  in intel_dp_compute_config()
3188 		adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;  in intel_dp_compute_config()
3189 		adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;  in intel_dp_compute_config()
3190 		adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;  in intel_dp_compute_config()
3191 		adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;  in intel_dp_compute_config()
3192 		adjusted_mode->crtc_clock /= n;  in intel_dp_compute_config()
3199 				       pipe_config->lane_count,  in intel_dp_compute_config()
3200 				       adjusted_mode->crtc_clock,  in intel_dp_compute_config()
3201 				       pipe_config->port_clock,  in intel_dp_compute_config()
3202 				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),  in intel_dp_compute_config()
3203 				       &pipe_config->dp_m_n);  in intel_dp_compute_config()
3207 	if (pipe_config->splitter.enable)  in intel_dp_compute_config()
3208 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;  in intel_dp_compute_config()
3214 	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);  in intel_dp_compute_config()
3218 	return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,  in intel_dp_compute_config()
3225 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));  in intel_dp_set_link_params()
3226 	intel_dp->link_trained = false;  in intel_dp_set_link_params()
3227 	intel_dp->needs_modeset_retry = false;  in intel_dp_set_link_params()
3228 	intel_dp->link_rate = link_rate;  in intel_dp_set_link_params()
3229 	intel_dp->lane_count = lane_count;  in intel_dp_set_link_params()
3234 	intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);  in intel_dp_reset_link_params()
3235 	intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);  in intel_dp_reset_link_params()
3236 	intel_dp->link.mst_probed_lane_count = 0;  in intel_dp_reset_link_params()
3237 	intel_dp->link.mst_probed_rate = 0;  in intel_dp_reset_link_params()
3238 	intel_dp->link.retrain_disabled = false;  in intel_dp_reset_link_params()
3239 	intel_dp->link.seq_train_failures = 0;  in intel_dp_reset_link_params()
3247 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));  in intel_edp_backlight_on()
3252 	drm_dbg_kms(display->drm, "\n");  in intel_edp_backlight_on()
3261 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));  in intel_edp_backlight_off()
3267 	drm_dbg_kms(display->drm, "\n");  in intel_edp_backlight_off()
3283 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&  in downstream_hpd_needs_d0()
3284 		drm_dp_is_branch(intel_dp->dpcd) &&  in downstream_hpd_needs_d0()
3285 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;  in downstream_hpd_needs_d0()
3307 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,  in intel_dp_sink_set_dsc_decompression()  argument
3310 	struct intel_display *display = to_intel_display(connector);  in intel_dp_sink_set_dsc_decompression()
3312 	if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,  in intel_dp_sink_set_dsc_decompression()
3314 		drm_dbg_kms(display->drm,  in intel_dp_sink_set_dsc_decompression()
3320 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,  in intel_dp_sink_set_dsc_passthrough()  argument
3323 	struct intel_display *display = to_intel_display(connector);  in intel_dp_sink_set_dsc_passthrough()
3324 	struct drm_dp_aux *aux = connector->mst.port ?  in intel_dp_sink_set_dsc_passthrough()
3325 				 connector->mst.port->passthrough_aux : NULL;  in intel_dp_sink_set_dsc_passthrough()
3332 		drm_dbg_kms(display->drm,  in intel_dp_sink_set_dsc_passthrough()
3338 				      const struct intel_connector *connector,  in intel_dp_dsc_aux_ref_count()  argument
3349 	 * On SST the decompression AUX device won't be shared, each connector  in intel_dp_dsc_aux_ref_count()
3352 	if (!connector->mst.dp)  in intel_dp_dsc_aux_ref_count()
3353 		return connector->dp.dsc_decompression_enabled ? 1 : 0;  in intel_dp_dsc_aux_ref_count()
3355 	for_each_oldnew_connector_in_state(&state->base, _connector_iter,  in intel_dp_dsc_aux_ref_count()
3360 		if (connector_iter->mst.dp != connector->mst.dp)  in intel_dp_dsc_aux_ref_count()
3363 		if (!connector_iter->dp.dsc_decompression_enabled)  in intel_dp_dsc_aux_ref_count()
3366 		drm_WARN_ON(display->drm,  in intel_dp_dsc_aux_ref_count()
3367 			    (for_get_ref && !new_conn_state->crtc) ||  in intel_dp_dsc_aux_ref_count()
3368 			    (!for_get_ref && !old_conn_state->crtc));  in intel_dp_dsc_aux_ref_count()
3370 		if (connector_iter->dp.dsc_decompression_aux ==  in intel_dp_dsc_aux_ref_count()
3371 		    connector->dp.dsc_decompression_aux)  in intel_dp_dsc_aux_ref_count()
3379 				     struct intel_connector *connector)  in intel_dp_dsc_aux_get_ref()  argument
3381 	bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;  in intel_dp_dsc_aux_get_ref()
3383 	connector->dp.dsc_decompression_enabled = true;  in intel_dp_dsc_aux_get_ref()
3389 				     struct intel_connector *connector)  in intel_dp_dsc_aux_put_ref()  argument
3391 	connector->dp.dsc_decompression_enabled = false;  in intel_dp_dsc_aux_put_ref()
3393 	return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;  in intel_dp_dsc_aux_put_ref()
3397  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3399  * @connector: connector to enable the decompression for
3400  * @new_crtc_state: new state for the CRTC driving @connector
3410 					struct intel_connector *connector,  in intel_dp_sink_enable_decompression()  argument
3415 	if (!new_crtc_state->dsc.compression_enable)  in intel_dp_sink_enable_decompression()
3418 	if (drm_WARN_ON(display->drm,  in intel_dp_sink_enable_decompression()
3419 			!connector->dp.dsc_decompression_aux ||  in intel_dp_sink_enable_decompression()
3420 			connector->dp.dsc_decompression_enabled))  in intel_dp_sink_enable_decompression()
3423 	if (!intel_dp_dsc_aux_get_ref(state, connector))  in intel_dp_sink_enable_decompression()
3426 	intel_dp_sink_set_dsc_passthrough(connector, true);  in intel_dp_sink_enable_decompression()
3427 	intel_dp_sink_set_dsc_decompression(connector, true);  in intel_dp_sink_enable_decompression()
3431  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3433  * @connector: connector to disable the decompression for
3434  * @old_crtc_state: old state for the CRTC driving @connector
3441 					 struct intel_connector *connector,  in intel_dp_sink_disable_decompression()  argument
3446 	if (!old_crtc_state->dsc.compression_enable)  in intel_dp_sink_disable_decompression()
3449 	if (drm_WARN_ON(display->drm,  in intel_dp_sink_disable_decompression()
3450 			!connector->dp.dsc_decompression_aux ||  in intel_dp_sink_disable_decompression()
3451 			!connector->dp.dsc_decompression_enabled))  in intel_dp_sink_disable_decompression()
3454 	if (!intel_dp_dsc_aux_put_ref(state, connector))  in intel_dp_sink_disable_decompression()
3457 	intel_dp_sink_set_dsc_decompression(connector, false);  in intel_dp_sink_disable_decompression()
3458 	intel_dp_sink_set_dsc_passthrough(connector, false);  in intel_dp_sink_disable_decompression()
3468 	if (READ_ONCE(intel_dp->oui_valid))  in intel_dp_init_source_oui()
3471 	WRITE_ONCE(intel_dp->oui_valid, true);  in intel_dp_init_source_oui()
3477 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)  in intel_dp_init_source_oui()
3478 		drm_dbg_kms(display->drm, "Failed to read source OUI\n");  in intel_dp_init_source_oui()
3482 		intel_dp->last_oui_write = jiffies;  in intel_dp_init_source_oui()
3486 	if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {  in intel_dp_init_source_oui()
3487 		drm_dbg_kms(display->drm, "Failed to write source OUI\n");  in intel_dp_init_source_oui()
3488 		WRITE_ONCE(intel_dp->oui_valid, false);  in intel_dp_init_source_oui()
3491 	intel_dp->last_oui_write = jiffies;  in intel_dp_init_source_oui()
3496 	WRITE_ONCE(intel_dp->oui_valid, false);  in intel_dp_invalidate_source_oui()
3502 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_wait_source_oui()  local
3504 	drm_dbg_kms(display->drm,  in intel_dp_wait_source_oui()
3505 		    "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",  in intel_dp_wait_source_oui()
3506 		    connector->base.base.id, connector->base.name,  in intel_dp_wait_source_oui()
3507 		    connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);  in intel_dp_wait_source_oui()
3509 	wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,  in intel_dp_wait_source_oui()
3510 				       connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);  in intel_dp_wait_source_oui()
3517 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_set_power()
3521 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_set_power()
3528 		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);  in intel_dp_set_power()
3542 			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);  in intel_dp_set_power()
3553 		drm_dbg_kms(display->drm,  in intel_dp_set_power()
3555 			    encoder->base.base.id, encoder->base.name,  in intel_dp_set_power()
3563  * intel_dp_sync_state - sync the encoder state during init/resume
3580 	if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {  in intel_dp_sync_state()
3589 		intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);  in intel_dp_sync_state()
3590 		intel_dp->link_trained = true;  in intel_dp_sync_state()
3602 	 * If BIOS has set an unsupported or non-standard link rate for some  in intel_dp_initial_fastset_check()
3605 	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,  in intel_dp_initial_fastset_check()
3606 				crtc_state->port_clock) < 0) {  in intel_dp_initial_fastset_check()
3607 		drm_dbg_kms(display->drm,  in intel_dp_initial_fastset_check()
3609 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3610 		crtc_state->uapi.connectors_changed = true;  in intel_dp_initial_fastset_check()
3618 	 * of crtc_state->dsc, we have no way to ensure reliable fastset.  in intel_dp_initial_fastset_check()
3621 	if (crtc_state->dsc.compression_enable) {  in intel_dp_initial_fastset_check()
3622 		drm_dbg_kms(display->drm,  in intel_dp_initial_fastset_check()
3624 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3625 		crtc_state->uapi.mode_changed = true;  in intel_dp_initial_fastset_check()
3630 		drm_dbg_kms(display->drm,  in intel_dp_initial_fastset_check()
3632 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3633 		crtc_state->uapi.mode_changed = true;  in intel_dp_initial_fastset_check()
3646 	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));  in intel_dp_get_pcon_dsc_cap()
3648 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,  in intel_dp_get_pcon_dsc_cap()
3649 			     intel_dp->pcon_dsc_dpcd,  in intel_dp_get_pcon_dsc_cap()
3650 			     sizeof(intel_dp->pcon_dsc_dpcd)) < 0)  in intel_dp_get_pcon_dsc_cap()
3651 		drm_err(display->drm, "Failed to read DPCD register 0x%x\n",  in intel_dp_get_pcon_dsc_cap()
3654 	drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",  in intel_dp_get_pcon_dsc_cap()
3655 		    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);  in intel_dp_get_pcon_dsc_cap()
3663 	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {  in intel_dp_pcon_get_frl_mask()
3692 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_hdmi_sink_max_frl()  local
3693 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_hdmi_sink_max_frl()
3698 	max_lanes = info->hdmi.max_lanes;  in intel_dp_hdmi_sink_max_frl()
3699 	rate_per_lane = info->hdmi.max_frl_rate_per_lane;  in intel_dp_hdmi_sink_max_frl()
3702 	if (info->hdmi.dsc_cap.v_1p2) {  in intel_dp_hdmi_sink_max_frl()
3703 		max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;  in intel_dp_hdmi_sink_max_frl()
3704 		dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;  in intel_dp_hdmi_sink_max_frl()
3716 	if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&  in intel_dp_pcon_is_frl_trained()
3717 	    drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&  in intel_dp_pcon_is_frl_trained()
3733 	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;  in intel_dp_pcon_start_frl_training()
3734 	drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);  in intel_dp_pcon_start_frl_training()
3737 	drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",  in intel_dp_pcon_start_frl_training()
3743 		return -EINVAL;  in intel_dp_pcon_start_frl_training()
3746 	drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);  in intel_dp_pcon_start_frl_training()
3751 	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);  in intel_dp_pcon_start_frl_training()
3755 	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);  in intel_dp_pcon_start_frl_training()
3758 		return -ETIMEDOUT;  in intel_dp_pcon_start_frl_training()
3760 	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,  in intel_dp_pcon_start_frl_training()
3764 	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,  in intel_dp_pcon_start_frl_training()
3768 	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);  in intel_dp_pcon_start_frl_training()
3780 		return -ETIMEDOUT;  in intel_dp_pcon_start_frl_training()
3783 	drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);  in intel_dp_pcon_start_frl_training()
3784 	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);  in intel_dp_pcon_start_frl_training()
3785 	intel_dp->frl.is_trained = true;  in intel_dp_pcon_start_frl_training()
3786 	drm_dbg(display->drm, "FRL trained with : %d Gbps\n",  in intel_dp_pcon_start_frl_training()
3787 		intel_dp->frl.trained_rate_gbps);  in intel_dp_pcon_start_frl_training()
3794 	if (drm_dp_is_branch(intel_dp->dpcd) &&  in intel_dp_is_hdmi_2_1_sink()
3811 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);  in intel_dp_pcon_set_tmds_mode()
3817 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);  in intel_dp_pcon_set_tmds_mode()
3830 	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)  in intel_dp_check_frl_training()
3831 	 * -sink is HDMI2.1  in intel_dp_check_frl_training()
3833 	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||  in intel_dp_check_frl_training()
3835 	    intel_dp->frl.is_trained)  in intel_dp_check_frl_training()
3841 		drm_dbg(display->drm,  in intel_dp_check_frl_training()
3844 		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);  in intel_dp_check_frl_training()
3847 			drm_dbg(display->drm,  in intel_dp_check_frl_training()
3850 		drm_dbg(display->drm, "FRL training Completed\n");  in intel_dp_check_frl_training()
3857 	int vactive = crtc_state->hw.adjusted_mode.vdisplay;  in intel_dp_pcon_dsc_enc_slice_height()
3866 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_enc_slices()  local
3867 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_pcon_dsc_enc_slices()
3868 	int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice;  in intel_dp_pcon_dsc_enc_slices()
3869 	int hdmi_max_slices = info->hdmi.dsc_cap.max_slices;  in intel_dp_pcon_dsc_enc_slices()
3870 	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_slices()
3871 	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_slices()
3883 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_enc_bpp()  local
3884 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_pcon_dsc_enc_bpp()
3885 	int output_format = crtc_state->output_format;  in intel_dp_pcon_dsc_enc_bpp()
3886 	bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp;  in intel_dp_pcon_dsc_enc_bpp()
3887 	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_bpp()
3889 		info->hdmi.dsc_cap.total_chunk_kbytes * 1024;  in intel_dp_pcon_dsc_enc_bpp()
3901 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_configure()  local
3914 	if (!connector)  in intel_dp_pcon_dsc_configure()
3917 	info = &connector->base.display_info;  in intel_dp_pcon_dsc_configure()
3919 	hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2;  in intel_dp_pcon_dsc_configure()
3921 	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||  in intel_dp_pcon_dsc_configure()
3933 	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,  in intel_dp_pcon_dsc_configure()
3948 	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);  in intel_dp_pcon_dsc_configure()
3950 		drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");  in intel_dp_pcon_dsc_configure()
3961 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)  in intel_dp_configure_protocol_converter()
3964 	if (!drm_dp_is_branch(intel_dp->dpcd))  in intel_dp_configure_protocol_converter()
3969 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_configure_protocol_converter()
3971 		drm_dbg_kms(display->drm,  in intel_dp_configure_protocol_converter()
3975 	if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {  in intel_dp_configure_protocol_converter()
3976 		switch (crtc_state->output_format) {  in intel_dp_configure_protocol_converter()
3987 			MISSING_CASE(crtc_state->output_format);  in intel_dp_configure_protocol_converter()
3990 	} else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {  in intel_dp_configure_protocol_converter()
3991 		switch (crtc_state->output_format) {  in intel_dp_configure_protocol_converter()
3998 			MISSING_CASE(crtc_state->output_format);  in intel_dp_configure_protocol_converter()
4005 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_configure_protocol_converter()
4007 		drm_dbg_kms(display->drm,  in intel_dp_configure_protocol_converter()
4009 			    str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));  in intel_dp_configure_protocol_converter()
4013 	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)  in intel_dp_configure_protocol_converter()
4014 		drm_dbg_kms(display->drm,  in intel_dp_configure_protocol_converter()
4015 			    "Failed to %s protocol converter RGB->YCbCr conversion mode\n",  in intel_dp_configure_protocol_converter()
4023 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,  in intel_dp_get_colorimetry_status()
4034 		drm_err(aux->drm_dev,  in intel_dp_read_dsc_dpcd()
4040 	drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",  in intel_dp_read_dsc_dpcd()
4045 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)  in intel_dp_get_dsc_sink_cap()  argument
4047 	struct intel_display *display = to_intel_display(connector);  in intel_dp_get_dsc_sink_cap()
4053 	memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));  in intel_dp_get_dsc_sink_cap()
4056 	connector->dp.fec_capability = 0;  in intel_dp_get_dsc_sink_cap()
4061 	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,  in intel_dp_get_dsc_sink_cap()
4062 			       connector->dp.dsc_dpcd);  in intel_dp_get_dsc_sink_cap()
4064 	if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,  in intel_dp_get_dsc_sink_cap()
4065 			      &connector->dp.fec_capability) < 0) {  in intel_dp_get_dsc_sink_cap()
4066 		drm_err(display->drm, "Failed to read FEC DPCD register\n");  in intel_dp_get_dsc_sink_cap()
4070 	drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",  in intel_dp_get_dsc_sink_cap()
4071 		    connector->dp.fec_capability);  in intel_dp_get_dsc_sink_cap()
4074 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)  in intel_edp_get_dsc_sink_cap()  argument
4079 	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);  in intel_edp_get_dsc_sink_cap()
4083 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)  in intel_dp_detect_dsc_caps()  argument
4087 	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */  in intel_dp_detect_dsc_caps()
4092 		intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],  in intel_dp_detect_dsc_caps()
4093 					   connector);  in intel_dp_detect_dsc_caps()
4095 		intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],  in intel_dp_detect_dsc_caps()
4096 					  connector);  in intel_dp_detect_dsc_caps()
4099 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,  in intel_edp_mso_mode_fixup()  argument
4102 	struct intel_display *display = to_intel_display(connector);  in intel_edp_mso_mode_fixup()
4103 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_edp_mso_mode_fixup()
4104 	int n = intel_dp->mso_link_count;  in intel_edp_mso_mode_fixup()
4105 	int overlap = intel_dp->mso_pixel_overlap;  in intel_edp_mso_mode_fixup()
4110 	mode->hdisplay = (mode->hdisplay - overlap) * n;  in intel_edp_mso_mode_fixup()
4111 	mode->hsync_start = (mode->hsync_start - overlap) * n;  in intel_edp_mso_mode_fixup()
4112 	mode->hsync_end = (mode->hsync_end - overlap) * n;  in intel_edp_mso_mode_fixup()
4113 	mode->htotal = (mode->htotal - overlap) * n;  in intel_edp_mso_mode_fixup()
4114 	mode->clock *= n;  in intel_edp_mso_mode_fixup()
4118 	drm_dbg_kms(display->drm,  in intel_edp_mso_mode_fixup()
4119 		    "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",  in intel_edp_mso_mode_fixup()
4120 		    connector->base.base.id, connector->base.name,  in intel_edp_mso_mode_fixup()
4128 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_fixup_vbt_bpp()  local
4130 	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {  in intel_edp_fixup_vbt_bpp()
4144 		drm_dbg_kms(display->drm,  in intel_edp_fixup_vbt_bpp()
4145 			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",  in intel_edp_fixup_vbt_bpp()
4146 			    pipe_bpp, connector->panel.vbt.edp.bpp);  in intel_edp_fixup_vbt_bpp()
4147 		connector->panel.vbt.edp.bpp = pipe_bpp;  in intel_edp_fixup_vbt_bpp()
4154 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_mso_init()  local
4155 	struct drm_display_info *info = &connector->base.display_info;  in intel_edp_mso_init()
4158 	if (intel_dp->edp_dpcd[0] < DP_EDP_14)  in intel_edp_mso_init()
4161 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {  in intel_edp_mso_init()
4162 		drm_err(display->drm, "Failed to read MSO cap\n");  in intel_edp_mso_init()
4168 	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {  in intel_edp_mso_init()
4169 		drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);  in intel_edp_mso_init()
4174 		drm_dbg_kms(display->drm,  in intel_edp_mso_init()
4176 			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,  in intel_edp_mso_init()
4177 			    info->mso_pixel_overlap);  in intel_edp_mso_init()
4179 			drm_err(display->drm,  in intel_edp_mso_init()
4185 	intel_dp->mso_link_count = mso;  in intel_edp_mso_init()
4186 	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;  in intel_edp_mso_init()
4193 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_edp_set_sink_rates()
4195 	intel_dp->num_sink_rates = 0;  in intel_edp_set_sink_rates()
4197 	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {  in intel_edp_set_sink_rates()
4201 		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,  in intel_edp_set_sink_rates()
4207 			/* Value read multiplied by 200kHz gives the per-lane  in intel_edp_set_sink_rates()
4223 			if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {  in intel_edp_set_sink_rates()
4224 				drm_dbg_kms(display->drm,  in intel_edp_set_sink_rates()
4226 					    encoder->base.base.id, encoder->base.name);  in intel_edp_set_sink_rates()
4230 			intel_dp->sink_rates[i] = rate;  in intel_edp_set_sink_rates()
4232 		intel_dp->num_sink_rates = i;  in intel_edp_set_sink_rates()
4239 	if (intel_dp->num_sink_rates)  in intel_edp_set_sink_rates()
4240 		intel_dp->use_rate_select = true;  in intel_edp_set_sink_rates()
4246 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)  in intel_edp_init_dpcd()  argument
4251 	drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);  in intel_edp_init_dpcd()
4253 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)  in intel_edp_init_dpcd()
4256 	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,  in intel_edp_init_dpcd()
4257 			 drm_dp_is_branch(intel_dp->dpcd));  in intel_edp_init_dpcd()
4258 	intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);  in intel_edp_init_dpcd()
4260 	intel_dp->colorimetry_support =  in intel_edp_init_dpcd()
4272 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,  in intel_edp_init_dpcd()
4273 			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==  in intel_edp_init_dpcd()
4274 			     sizeof(intel_dp->edp_dpcd)) {  in intel_edp_init_dpcd()
4275 		drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",  in intel_edp_init_dpcd()
4276 			    (int)sizeof(intel_dp->edp_dpcd),  in intel_edp_init_dpcd()
4277 			    intel_dp->edp_dpcd);  in intel_edp_init_dpcd()
4279 		intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;  in intel_edp_init_dpcd()
4283 	 * If needed, program our source OUI so we can make various Intel-specific AUX services  in intel_edp_init_dpcd()
4289 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks  in intel_edp_init_dpcd()
4290 	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]  in intel_edp_init_dpcd()
4298 	intel_dp_detect_dsc_caps(intel_dp, connector);  in intel_edp_init_dpcd()
4306 	if (!intel_dp->attached_connector)  in intel_dp_has_sink_count()
4309 	return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,  in intel_dp_has_sink_count()
4310 					  intel_dp->dpcd,  in intel_dp_has_sink_count()
4311 					  &intel_dp->desc);  in intel_dp_has_sink_count()
4330 	 * Don't clobber cached eDP rates. Also skip re-reading  in intel_dp_get_dpcd()
4334 		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,  in intel_dp_get_dpcd()
4335 				 drm_dp_is_branch(intel_dp->dpcd));  in intel_dp_get_dpcd()
4337 		intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);  in intel_dp_get_dpcd()
4339 		intel_dp->colorimetry_support =  in intel_dp_get_dpcd()
4346 		ret = drm_dp_read_sink_count(&intel_dp->aux);  in intel_dp_get_dpcd()
4355 		intel_dp->sink_count = ret;  in intel_dp_get_dpcd()
4364 		if (!intel_dp->sink_count)  in intel_dp_get_dpcd()
4368 	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,  in intel_dp_get_dpcd()
4369 					   intel_dp->downstream_ports) == 0;  in intel_dp_get_dpcd()
4388 	if (!display->params.enable_dp_mst)  in intel_dp_mst_mode_choose()
4395 	    !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))  in intel_dp_mst_mode_choose()
4405 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_mst_detect()
4409 	sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);  in intel_dp_mst_detect()
4413 	drm_dbg_kms(display->drm,  in intel_dp_mst_detect()
4414 		    "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",  in intel_dp_mst_detect()
4415 		    encoder->base.base.id, encoder->base.name,  in intel_dp_mst_detect()
4418 		    str_yes_no(display->params.enable_dp_mst),  in intel_dp_mst_detect()
4430 	intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;  in intel_dp_mst_configure()
4432 	if (intel_dp->is_mst)  in intel_dp_mst_configure()
4435 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst);  in intel_dp_mst_configure()
4438 	intel_dp->mst_detect = DRM_DP_SST;  in intel_dp_mst_configure()
4446 	if (!intel_dp->is_mst)  in intel_dp_mst_disconnect()
4449 	drm_dbg_kms(display->drm,  in intel_dp_mst_disconnect()
4451 		    intel_dp->is_mst, intel_dp->mst.mgr.mst_state);  in intel_dp_mst_disconnect()
4452 	intel_dp->is_mst = false;  in intel_dp_mst_disconnect()
4453 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst);  in intel_dp_mst_disconnect()
4459 	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;  in intel_dp_get_sink_irq_esi()
4467 		if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,  in intel_dp_ack_sink_irq_esi()
4480 	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication  in intel_dp_needs_vsc_sdp()
4482 	 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.  in intel_dp_needs_vsc_sdp()
4484 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in intel_dp_needs_vsc_sdp()
4487 	switch (conn_state->colorspace) {  in intel_dp_needs_vsc_sdp()
4507 		return -ENOSPC;  in intel_dp_as_sdp_pack()
4512 	sdp->sdp_header.HB0 = 0;  in intel_dp_as_sdp_pack()
4513 	sdp->sdp_header.HB1 = as_sdp->sdp_type;  in intel_dp_as_sdp_pack()
4514 	sdp->sdp_header.HB2 = 0x02;  in intel_dp_as_sdp_pack()
4515 	sdp->sdp_header.HB3 = as_sdp->length;  in intel_dp_as_sdp_pack()
4518 	sdp->db[0] = as_sdp->mode;  in intel_dp_as_sdp_pack()
4519 	sdp->db[1] = as_sdp->vtotal & 0xFF;  in intel_dp_as_sdp_pack()
4520 	sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;  in intel_dp_as_sdp_pack()
4521 	sdp->db[3] = as_sdp->target_rr & 0xFF;  in intel_dp_as_sdp_pack()
4522 	sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;  in intel_dp_as_sdp_pack()
4524 	if (as_sdp->target_rr_divider)  in intel_dp_as_sdp_pack()
4525 		sdp->db[4] |= 0x20;  in intel_dp_as_sdp_pack()
4542 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4548 		drm_dbg_kms(display->drm,  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4550 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4554 		drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4555 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4560 	 * Prepare VSC Header for SU as per DP 1.4a spec,  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4561 	 * Table 2-100 and Table 2-101  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4564 	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4565 	sdp->sdp_header.HB0 = 0;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4567 	 * Packet Type 80h + Non-audio INFOFRAME Type value  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4569 	 * - 80h + Non-audio INFOFRAME Type value  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4570 	 * - InfoFrame Type: 0x07  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4571 	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4573 	sdp->sdp_header.HB1 = drm_infoframe->type;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4576 	 * infoframe_size - 1  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4578 	sdp->sdp_header.HB2 = 0x1D;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4580 	sdp->sdp_header.HB3 = (0x13 << 2);  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4582 	sdp->db[0] = drm_infoframe->version;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4584 	sdp->db[1] = drm_infoframe->length;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4589 	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4590 	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4594 	 * Size of DP infoframe sdp packet for HDR static metadata consists of  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4595 	 * - DP SDP Header(struct dp_sdp_header): 4 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4596 	 * - Two Data Blocks: 2 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4599 	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4601 	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4617 	if ((crtc_state->infoframes.enable &  in intel_write_dp_sdp()
4623 		len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);  in intel_write_dp_sdp()
4627 							       &crtc_state->infoframes.drm.drm,  in intel_write_dp_sdp()
4631 		len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,  in intel_write_dp_sdp()
4639 	if (drm_WARN_ON(display->drm, len < 0))  in intel_write_dp_sdp()
4642 	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);  in intel_write_dp_sdp()
4651 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);  in intel_dp_set_infoframes()
4669 	if (!enable || !crtc_state->has_psr)  in intel_dp_set_infoframes()
4691 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4695 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_as_sdp_unpack()
4696 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4698 	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)  in intel_dp_as_sdp_unpack()
4699 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4701 	if (sdp->sdp_header.HB2 != 0x02)  in intel_dp_as_sdp_unpack()
4702 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4704 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)  in intel_dp_as_sdp_unpack()
4705 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4707 	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;  in intel_dp_as_sdp_unpack()
4708 	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;  in intel_dp_as_sdp_unpack()
4709 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];  in intel_dp_as_sdp_unpack()
4710 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);  in intel_dp_as_sdp_unpack()
4711 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;  in intel_dp_as_sdp_unpack()
4722 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4726 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_vsc_sdp_unpack()
4727 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4729 	if (sdp->sdp_header.HB1 != DP_SDP_VSC)  in intel_dp_vsc_sdp_unpack()
4730 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4732 	vsc->sdp_type = sdp->sdp_header.HB1;  in intel_dp_vsc_sdp_unpack()
4733 	vsc->revision = sdp->sdp_header.HB2;  in intel_dp_vsc_sdp_unpack()
4734 	vsc->length = sdp->sdp_header.HB3;  in intel_dp_vsc_sdp_unpack()
4736 	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||  in intel_dp_vsc_sdp_unpack()
4737 	    (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||  in intel_dp_vsc_sdp_unpack()
4738 	    (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {  in intel_dp_vsc_sdp_unpack()
4740 		 * - HB2 = 0x2, HB3 = 0x8  in intel_dp_vsc_sdp_unpack()
4742 		 * - HB2 = 0x4, HB3 = 0xe  in intel_dp_vsc_sdp_unpack()
4743 		 *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of  in intel_dp_vsc_sdp_unpack()
4746 		 * - HB2 = 0x6, HB3 = 0x10  in intel_dp_vsc_sdp_unpack()
4750 	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {  in intel_dp_vsc_sdp_unpack()
4752 		 * - HB2 = 0x5, HB3 = 0x13  in intel_dp_vsc_sdp_unpack()
4756 		vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;  in intel_dp_vsc_sdp_unpack()
4757 		vsc->colorimetry = sdp->db[16] & 0xf;  in intel_dp_vsc_sdp_unpack()
4758 		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;  in intel_dp_vsc_sdp_unpack()
4760 		switch (sdp->db[17] & 0x7) {  in intel_dp_vsc_sdp_unpack()
4762 			vsc->bpc = 6;  in intel_dp_vsc_sdp_unpack()
4765 			vsc->bpc = 8;  in intel_dp_vsc_sdp_unpack()
4768 			vsc->bpc = 10;  in intel_dp_vsc_sdp_unpack()
4771 			vsc->bpc = 12;  in intel_dp_vsc_sdp_unpack()
4774 			vsc->bpc = 16;  in intel_dp_vsc_sdp_unpack()
4777 			MISSING_CASE(sdp->db[17] & 0x7);  in intel_dp_vsc_sdp_unpack()
4778 			return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4781 		vsc->content_type = sdp->db[18] & 0x7;  in intel_dp_vsc_sdp_unpack()
4783 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4800 	if ((crtc_state->infoframes.enable &  in intel_read_dp_as_sdp()
4804 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,  in intel_read_dp_as_sdp()
4809 		drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");  in intel_read_dp_as_sdp()
4821 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4823 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4824 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4826 	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4827 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4833 	if (sdp->sdp_header.HB2 != 0x1D)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4834 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4837 	if ((sdp->sdp_header.HB3 & 0x3) != 0)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4838 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4841 	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4842 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4845 	if (sdp->db[0] != 1)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4846 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4849 	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4850 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4852 	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4868 	if ((crtc_state->infoframes.enable &  in intel_read_dp_vsc_sdp()
4872 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));  in intel_read_dp_vsc_sdp()
4877 		drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");  in intel_read_dp_vsc_sdp()
4890 	if ((crtc_state->infoframes.enable &  in intel_read_dp_hdr_metadata_infoframe_sdp()
4894 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,  in intel_read_dp_hdr_metadata_infoframe_sdp()
4901 		drm_dbg_kms(display->drm,  in intel_read_dp_hdr_metadata_infoframe_sdp()
4902 			    "Failed to unpack DP HDR Metadata Infoframe SDP\n");  in intel_read_dp_hdr_metadata_infoframe_sdp()
4912 				      &crtc_state->infoframes.vsc);  in intel_read_dp_sdp()
4916 							 &crtc_state->infoframes.drm.drm);  in intel_read_dp_sdp()
4920 				     &crtc_state->infoframes.as_sdp);  in intel_read_dp_sdp()
4932 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_link_ok()
4933 	bool uhbr = intel_dp->link_rate >= 1000000;  in intel_dp_link_ok()
4938 							  intel_dp->lane_count);  in intel_dp_link_ok()
4940 		ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);  in intel_dp_link_ok()
4946 	drm_dbg_kms(display->drm,  in intel_dp_link_ok()
4948 		    encoder->base.base.id, encoder->base.name,  in intel_dp_link_ok()
4959 	drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled);  in intel_dp_mst_hpd_irq()
4962 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);  in intel_dp_mst_hpd_irq()
4970 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_mst_link_status()
4972 	const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;  in intel_dp_mst_link_status()
4974 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,  in intel_dp_mst_link_status()
4976 		drm_err(display->drm,  in intel_dp_mst_link_status()
4978 			encoder->base.base.id, encoder->base.name);  in intel_dp_mst_link_status()
4986  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4987  * @intel_dp: Intel DP struct
4993  * - %true if pending interrupts were serviced (or no interrupts were
4995  * - %false if an error condition - like AUX failure or a loss of link - is
4996  *   detected, or another condition - like a DP tunnel BW state change - needs
5004 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_check_mst_status()
5008 	drm_WARN_ON_ONCE(display->drm, intel_dp->mst.active_links < 0);  in intel_dp_check_mst_status()
5015 			drm_dbg_kms(display->drm,  in intel_dp_check_mst_status()
5016 				    "failed to get ESI - device may have failed\n");  in intel_dp_check_mst_status()
5022 		drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);  in intel_dp_check_mst_status()
5024 		if (intel_dp->mst.active_links > 0 && link_ok &&  in intel_dp_check_mst_status()
5034 			if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,  in intel_dp_check_mst_status()
5035 						     &intel_dp->aux))  in intel_dp_check_mst_status()
5044 			drm_dbg_kms(display->drm, "Failed to ack ESI\n");  in intel_dp_check_mst_status()
5047 			drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr);  in intel_dp_check_mst_status()
5050 	if (!link_ok || intel_dp->link.force_retrain)  in intel_dp_check_mst_status()
5062 	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);  in intel_dp_handle_hdmi_link_status_change()
5063 	if (intel_dp->frl.is_trained && !is_active) {  in intel_dp_handle_hdmi_link_status_change()
5064 		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)  in intel_dp_handle_hdmi_link_status_change()
5068 		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)  in intel_dp_handle_hdmi_link_status_change()
5071 		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);  in intel_dp_handle_hdmi_link_status_change()
5073 		intel_dp->frl.is_trained = false;  in intel_dp_handle_hdmi_link_status_change()
5085 	if (!intel_dp->link_trained)  in intel_dp_needs_link_retrain()
5089 	 * While PSR source HW is enabled, it will control main-link sending  in intel_dp_needs_link_retrain()
5099 	if (intel_dp->link.force_retrain)  in intel_dp_needs_link_retrain()
5102 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,  in intel_dp_needs_link_retrain()
5107 	 * Validate the cached values of intel_dp->link_rate and  in intel_dp_needs_link_retrain()
5108 	 * intel_dp->lane_count before attempting to retrain.  in intel_dp_needs_link_retrain()
5114 	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,  in intel_dp_needs_link_retrain()
5115 					intel_dp->lane_count))  in intel_dp_needs_link_retrain()
5118 	if (intel_dp->link.retrain_disabled)  in intel_dp_needs_link_retrain()
5121 	if (intel_dp->link.seq_train_failures)  in intel_dp_needs_link_retrain()
5136 	if (!conn_state->best_encoder)  in intel_dp_has_connector()
5140 	encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_has_connector()
5141 	if (conn_state->best_encoder == &encoder->base)  in intel_dp_has_connector()
5146 		encoder = &intel_dp->mst.stream_encoders[pipe]->base;  in intel_dp_has_connector()
5147 		if (conn_state->best_encoder == &encoder->base)  in intel_dp_has_connector()
5156 	struct intel_connector *connector = to_intel_connector(conn_state->connector);  in wait_for_connector_hw_done()  local
5157 	struct intel_display *display = to_intel_display(connector);  in wait_for_connector_hw_done()
5159 	drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);  in wait_for_connector_hw_done()
5161 	if (!conn_state->commit)  in wait_for_connector_hw_done()
5164 	drm_WARN_ON(display->drm,  in wait_for_connector_hw_done()
5165 		    !wait_for_completion_timeout(&conn_state->commit->hw_done,  in wait_for_connector_hw_done()
5175 	struct intel_connector *connector;  in intel_dp_get_active_pipes()  local
5180 	drm_connector_list_iter_begin(display->drm, &conn_iter);  in intel_dp_get_active_pipes()
5181 	for_each_intel_connector_iter(connector, &conn_iter) {  in intel_dp_get_active_pipes()
5183 			connector->base.state;  in intel_dp_get_active_pipes()
5190 		crtc = to_intel_crtc(conn_state->crtc);  in intel_dp_get_active_pipes()
5194 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);  in intel_dp_get_active_pipes()
5198 		crtc_state = to_intel_crtc_state(crtc->base.state);  in intel_dp_get_active_pipes()
5200 		drm_WARN_ON(display->drm,  in intel_dp_get_active_pipes()
5203 		if (!crtc_state->hw.active)  in intel_dp_get_active_pipes()
5208 		*pipe_mask |= BIT(crtc->pipe);  in intel_dp_get_active_pipes()
5215 void intel_dp_flush_connector_commits(struct intel_connector *connector)  in intel_dp_flush_connector_commits()  argument
5217 	wait_for_connector_hw_done(connector->base.state);  in intel_dp_flush_connector_commits()
5222 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_is_connected()  local
5224 	return connector->base.status == connector_status_connected ||  in intel_dp_is_connected()
5225 		intel_dp->is_mst;  in intel_dp_is_connected()
5239 	ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,  in intel_dp_retrain_link()
5257 	drm_dbg_kms(display->drm,  in intel_dp_retrain_link()
5259 		    encoder->base.base.id, encoder->base.name,  in intel_dp_retrain_link()
5260 		    str_yes_no(intel_dp->link.force_retrain));  in intel_dp_retrain_link()
5263 	if (ret == -EDEADLK)  in intel_dp_retrain_link()
5266 	intel_dp->link.force_retrain = false;  in intel_dp_retrain_link()
5269 		drm_dbg_kms(display->drm,  in intel_dp_retrain_link()
5271 			    encoder->base.base.id, encoder->base.name,  in intel_dp_retrain_link()
5289 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_check_link_state()
5305 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_check_device_service_irq()
5308 	if (drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_check_device_service_irq()
5312 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);  in intel_dp_check_device_service_irq()
5318 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);  in intel_dp_check_device_service_irq()
5321 		drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");  in intel_dp_check_device_service_irq()
5330 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_check_link_service_irq()
5333 	if (drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_check_link_service_irq()
5338 	    drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,  in intel_dp_check_link_service_irq()
5339 				     &intel_dp->aux))  in intel_dp_check_link_service_irq()
5342 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_check_link_service_irq()
5353  * According to DP spec
5358  *  4. Check link status on receipt of hot-plug interrupt
5360  * intel_dp_short_pulse -  handles short pulse interrupts
5368 	u8 old_sink_count = intel_dp->sink_count;  in intel_dp_short_pulse()
5382 	if ((old_sink_count != intel_dp->sink_count) || !ret) {  in intel_dp_short_pulse()
5391 	drm_dp_cec_irq(&intel_dp->aux);  in intel_dp_short_pulse()
5409 	u8 *dpcd = intel_dp->dpcd;  in intel_dp_detect_dpcd()
5412 	if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))  in intel_dp_detect_dpcd()
5420 	intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);  in intel_dp_detect_dpcd()
5426 	/* If we're HPD-aware, SINK_COUNT changes dynamically */  in intel_dp_detect_dpcd()
5428 	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {  in intel_dp_detect_dpcd()
5429 		return intel_dp->sink_count ?  in intel_dp_detect_dpcd()
5433 	if (intel_dp->mst_detect == DRM_DP_MST)  in intel_dp_detect_dpcd()
5437 	if (drm_probe_ddc(&intel_dp->aux.ddc))  in intel_dp_detect_dpcd()
5441 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {  in intel_dp_detect_dpcd()
5442 		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;  in intel_dp_detect_dpcd()
5447 		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in intel_dp_detect_dpcd()
5455 	drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");  in intel_dp_detect_dpcd()
5469 	if (dig_port->lock)  in intel_digital_port_lock()
5470 		dig_port->lock(dig_port);  in intel_digital_port_lock()
5477 	if (dig_port->unlock)  in intel_digital_port_unlock()
5478 		dig_port->unlock(dig_port);  in intel_digital_port_unlock()
5482  * intel_digital_port_connected_locked - is the specified port connected?
5485  * In cases where there's a connector physically connected but it can't be used
5487  * pretty much treat the port as disconnected. This is relevant for type-C
5507 			is_connected = dig_port->connected(encoder);  in intel_digital_port_connected_locked()
5531 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_get_edid()  local
5532 	const struct drm_edid *fixed_edid = connector->panel.fixed_edid;  in intel_dp_get_edid()
5543 	return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);  in intel_dp_get_edid()
5551 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_update_dfp()  local
5553 	intel_dp->dfp.max_bpc =  in intel_dp_update_dfp()
5554 		drm_dp_downstream_max_bpc(intel_dp->dpcd,  in intel_dp_update_dfp()
5555 					  intel_dp->downstream_ports, drm_edid);  in intel_dp_update_dfp()
5557 	intel_dp->dfp.max_dotclock =  in intel_dp_update_dfp()
5558 		drm_dp_downstream_max_dotclock(intel_dp->dpcd,  in intel_dp_update_dfp()
5559 					       intel_dp->downstream_ports);  in intel_dp_update_dfp()
5561 	intel_dp->dfp.min_tmds_clock =  in intel_dp_update_dfp()
5562 		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,  in intel_dp_update_dfp()
5563 						 intel_dp->downstream_ports,  in intel_dp_update_dfp()
5565 	intel_dp->dfp.max_tmds_clock =  in intel_dp_update_dfp()
5566 		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,  in intel_dp_update_dfp()
5567 						 intel_dp->downstream_ports,  in intel_dp_update_dfp()
5570 	intel_dp->dfp.pcon_max_frl_bw =  in intel_dp_update_dfp()
5571 		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,  in intel_dp_update_dfp()
5572 					   intel_dp->downstream_ports);  in intel_dp_update_dfp()
5574 	drm_dbg_kms(display->drm,  in intel_dp_update_dfp()
5575 …   "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",  in intel_dp_update_dfp()
5576 		    connector->base.base.id, connector->base.name,  in intel_dp_update_dfp()
5577 		    intel_dp->dfp.max_bpc,  in intel_dp_update_dfp()
5578 		    intel_dp->dfp.max_dotclock,  in intel_dp_update_dfp()
5579 		    intel_dp->dfp.min_tmds_clock,  in intel_dp_update_dfp()
5580 		    intel_dp->dfp.max_tmds_clock,  in intel_dp_update_dfp()
5581 		    intel_dp->dfp.pcon_max_frl_bw);  in intel_dp_update_dfp()
5590 	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))  in intel_dp_can_ycbcr420()
5608 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_update_420()  local
5610 	intel_dp->dfp.ycbcr420_passthrough =  in intel_dp_update_420()
5611 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,  in intel_dp_update_420()
5612 						  intel_dp->downstream_ports);  in intel_dp_update_420()
5613 	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */  in intel_dp_update_420()
5614 	intel_dp->dfp.ycbcr_444_to_420 =  in intel_dp_update_420()
5616 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,  in intel_dp_update_420()
5617 							intel_dp->downstream_ports);  in intel_dp_update_420()
5618 	intel_dp->dfp.rgb_to_ycbcr =  in intel_dp_update_420()
5619 		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,  in intel_dp_update_420()
5620 							  intel_dp->downstream_ports,  in intel_dp_update_420()
5623 	connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);  in intel_dp_update_420()
5625 	drm_dbg_kms(display->drm,  in intel_dp_update_420()
5626 …"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversi…  in intel_dp_update_420()
5627 		    connector->base.base.id, connector->base.name,  in intel_dp_update_420()
5628 		    str_yes_no(intel_dp->dfp.rgb_to_ycbcr),  in intel_dp_update_420()
5629 		    str_yes_no(connector->base.ycbcr_420_allowed),  in intel_dp_update_420()
5630 		    str_yes_no(intel_dp->dfp.ycbcr_444_to_420));  in intel_dp_update_420()
5637 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_edid()  local
5643 	connector->detect_edid = drm_edid;  in intel_dp_set_edid()
5646 	drm_edid_connector_update(&connector->base, drm_edid);  in intel_dp_set_edid()
5648 	vrr_capable = intel_vrr_is_capable(connector);  in intel_dp_set_edid()
5649 	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",  in intel_dp_set_edid()
5650 		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));  in intel_dp_set_edid()
5651 	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);  in intel_dp_set_edid()
5656 	drm_dp_cec_attach(&intel_dp->aux,  in intel_dp_set_edid()
5657 			  connector->base.display_info.source_physical_address);  in intel_dp_set_edid()
5663 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_unset_edid()  local
5665 	drm_dp_cec_unset_edid(&intel_dp->aux);  in intel_dp_unset_edid()
5666 	drm_edid_free(connector->detect_edid);  in intel_dp_unset_edid()
5667 	connector->detect_edid = NULL;  in intel_dp_unset_edid()
5669 	intel_dp->dfp.max_bpc = 0;  in intel_dp_unset_edid()
5670 	intel_dp->dfp.max_dotclock = 0;  in intel_dp_unset_edid()
5671 	intel_dp->dfp.min_tmds_clock = 0;  in intel_dp_unset_edid()
5672 	intel_dp->dfp.max_tmds_clock = 0;  in intel_dp_unset_edid()
5674 	intel_dp->dfp.pcon_max_frl_bw = 0;  in intel_dp_unset_edid()
5676 	intel_dp->dfp.ycbcr_444_to_420 = false;  in intel_dp_unset_edid()
5677 	connector->base.ycbcr_420_allowed = false;  in intel_dp_unset_edid()
5679 	drm_connector_set_vrr_capable_property(&connector->base,  in intel_dp_unset_edid()
5688 	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&  in intel_dp_detect_sdp_caps()
5689 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);  in intel_dp_detect_sdp_caps()
5697 	struct intel_display *display = to_intel_display(_connector->dev);  in intel_dp_detect()
5698 	struct intel_connector *connector = to_intel_connector(_connector);  in intel_dp_detect()  local
5699 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_detect()
5701 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_detect()
5705 	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",  in intel_dp_detect()
5706 		    connector->base.base.id, connector->base.name);  in intel_dp_detect()
5707 	drm_WARN_ON(display->drm,  in intel_dp_detect()
5708 		    !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));  in intel_dp_detect()
5714 		return connector->base.status;  in intel_dp_detect()
5716 	intel_dp_flush_connector_commits(connector);  in intel_dp_detect()
5731 		 * This requires retrying detection for instance to re-enable  in intel_dp_detect()
5734 		 * ensured by setting the connector here to SST/disconnected,  in intel_dp_detect()
5735 		 * or via a userspace connector probing in response to the  in intel_dp_detect()
5742 		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));  in intel_dp_detect()
5743 		intel_dp->psr.sink_panel_replay_support = false;  in intel_dp_detect()
5744 		intel_dp->psr.sink_panel_replay_su_support = false;  in intel_dp_detect()
5756 	if (ret == -EDEADLK) {  in intel_dp_detect()
5763 		connector->base.epoch_counter++;  in intel_dp_detect()
5768 	intel_dp_detect_dsc_caps(intel_dp, connector);  in intel_dp_detect()
5772 	if (intel_dp->reset_link_params) {  in intel_dp_detect()
5774 		intel_dp->reset_link_params = false;  in intel_dp_detect()
5781 	if (intel_dp->is_mst) {  in intel_dp_detect()
5783 		 * If we are in MST mode then this connector  in intel_dp_detect()
5807 	intel_dp->aux.i2c_nack_count = 0;  in intel_dp_detect()
5808 	intel_dp->aux.i2c_defer_count = 0;  in intel_dp_detect()
5811 	if (intel_dp_is_edp(intel_dp) || connector->detect_edid)  in intel_dp_detect()
5817 	if (status != connector_status_connected && !intel_dp->is_mst)  in intel_dp_detect()
5821 		drm_dp_set_subconnector_property(&connector->base,  in intel_dp_detect()
5823 						 intel_dp->dpcd,  in intel_dp_detect()
5824 						 intel_dp->downstream_ports);  in intel_dp_detect()
5832 intel_dp_force(struct drm_connector *connector)  in intel_dp_force()  argument
5834 	struct intel_display *display = to_intel_display(connector->dev);  in intel_dp_force()
5835 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));  in intel_dp_force()
5837 	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",  in intel_dp_force()
5838 		    connector->base.id, connector->name);  in intel_dp_force()
5845 	if (connector->status != connector_status_connected)  in intel_dp_force()
5853 	struct intel_display *display = to_intel_display(_connector->dev);  in intel_dp_get_modes()
5854 	struct intel_connector *connector = to_intel_connector(_connector);  in intel_dp_get_modes()  local
5855 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_get_modes()
5858 	/* drm_edid_connector_update() done in ->detect() or ->force() */  in intel_dp_get_modes()
5859 	num_modes = drm_edid_connector_add_modes(&connector->base);  in intel_dp_get_modes()
5863 		num_modes += intel_panel_get_modes(connector);  in intel_dp_get_modes()
5868 	if (!connector->detect_edid) {  in intel_dp_get_modes()
5871 		mode = drm_dp_downstream_mode(display->drm,  in intel_dp_get_modes()
5872 					      intel_dp->dpcd,  in intel_dp_get_modes()
5873 					      intel_dp->downstream_ports);  in intel_dp_get_modes()
5875 			drm_mode_probed_add(&connector->base, mode);  in intel_dp_get_modes()
5884 intel_dp_connector_register(struct drm_connector *connector)  in intel_dp_connector_register()  argument
5886 	struct intel_display *display = to_intel_display(connector->dev);  in intel_dp_connector_register()
5887 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));  in intel_dp_connector_register()
5891 	ret = intel_connector_register(connector);  in intel_dp_connector_register()
5895 	drm_dbg_kms(display->drm, "registering %s bus for %s\n",  in intel_dp_connector_register()
5896 		    intel_dp->aux.name, connector->kdev->kobj.name);  in intel_dp_connector_register()
5898 	intel_dp->aux.dev = connector->kdev;  in intel_dp_connector_register()
5899 	ret = drm_dp_aux_register(&intel_dp->aux);  in intel_dp_connector_register()
5901 		drm_dp_cec_register_connector(&intel_dp->aux, connector);  in intel_dp_connector_register()
5903 	if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))  in intel_dp_connector_register()
5912 			drm_connector_attach_hdr_output_metadata_property(connector);  in intel_dp_connector_register()
5919 intel_dp_connector_unregister(struct drm_connector *connector)  in intel_dp_connector_unregister()  argument
5921 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));  in intel_dp_connector_unregister()
5923 	drm_dp_cec_unregister_connector(&intel_dp->aux);  in intel_dp_connector_unregister()
5924 	drm_dp_aux_unregister(&intel_dp->aux);  in intel_dp_connector_unregister()
5925 	intel_connector_unregister(connector);  in intel_dp_connector_unregister()
5928 void intel_dp_connector_sync_state(struct intel_connector *connector,  in intel_dp_connector_sync_state()  argument
5931 	struct intel_display *display = to_intel_display(connector);  in intel_dp_connector_sync_state()
5933 	if (crtc_state && crtc_state->dsc.compression_enable) {  in intel_dp_connector_sync_state()
5934 		drm_WARN_ON(display->drm,  in intel_dp_connector_sync_state()
5935 			    !connector->dp.dsc_decompression_aux);  in intel_dp_connector_sync_state()
5936 		connector->dp.dsc_decompression_enabled = true;  in intel_dp_connector_sync_state()
5938 		connector->dp.dsc_decompression_enabled = false;  in intel_dp_connector_sync_state()
5946 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_encoder_flush_work()
5986 	struct drm_connector *connector;  in intel_modeset_tile_group()  local
5989 	drm_connector_list_iter_begin(display->drm, &conn_iter);  in intel_modeset_tile_group()
5990 	drm_for_each_connector_iter(connector, &conn_iter) {  in intel_modeset_tile_group()
5995 		if (!connector->has_tile ||  in intel_modeset_tile_group()
5996 		    connector->tile_group->id != tile_group_id)  in intel_modeset_tile_group()
5999 		conn_state = drm_atomic_get_connector_state(&state->base,  in intel_modeset_tile_group()
6000 							    connector);  in intel_modeset_tile_group()
6006 		crtc = to_intel_crtc(conn_state->crtc);  in intel_modeset_tile_group()
6012 		crtc_state->uapi.mode_changed = true;  in intel_modeset_tile_group()
6014 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);  in intel_modeset_tile_group()
6031 	for_each_intel_crtc(display->drm, crtc) {  in intel_modeset_affected_transcoders()
6035 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_affected_transcoders()
6039 		if (!crtc_state->hw.enable)  in intel_modeset_affected_transcoders()
6042 		if (!(transcoders & BIT(crtc_state->cpu_transcoder)))  in intel_modeset_affected_transcoders()
6045 		crtc_state->uapi.mode_changed = true;  in intel_modeset_affected_transcoders()
6047 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);  in intel_modeset_affected_transcoders()
6051 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);  in intel_modeset_affected_transcoders()
6055 		transcoders &= ~BIT(crtc_state->cpu_transcoder);  in intel_modeset_affected_transcoders()
6058 	drm_WARN_ON(display->drm, transcoders != 0);  in intel_modeset_affected_transcoders()
6064 				      struct drm_connector *connector)  in intel_modeset_synced_crtcs()  argument
6067 		drm_atomic_get_old_connector_state(&state->base, connector);  in intel_modeset_synced_crtcs()
6072 	crtc = to_intel_crtc(old_conn_state->crtc);  in intel_modeset_synced_crtcs()
6078 	if (!old_crtc_state->hw.active)  in intel_modeset_synced_crtcs()
6081 	transcoders = old_crtc_state->sync_mode_slaves_mask;  in intel_modeset_synced_crtcs()
6082 	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_modeset_synced_crtcs()
6083 		transcoders |= BIT(old_crtc_state->master_transcoder);  in intel_modeset_synced_crtcs()
6092 	struct intel_display *display = to_intel_display(conn->dev);  in intel_dp_connector_atomic_check()
6096 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);  in intel_dp_connector_atomic_check()
6099 	ret = intel_digital_connector_atomic_check(conn, &state->base);  in intel_dp_connector_atomic_check()
6104 		ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr);  in intel_dp_connector_atomic_check()
6125 	if (conn->has_tile) {  in intel_dp_connector_atomic_check()
6126 		ret = intel_modeset_tile_group(state, conn->tile_group->id);  in intel_dp_connector_atomic_check()
6134 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,  in intel_dp_oob_hotplug_event()  argument
6137 	struct intel_display *display = to_intel_display(connector->dev);  in intel_dp_oob_hotplug_event()
6138 	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));  in intel_dp_oob_hotplug_event()
6139 	struct drm_i915_private *i915 = to_i915(connector->dev);  in intel_dp_oob_hotplug_event()
6141 	unsigned int hpd_pin = encoder->hpd_pin;  in intel_dp_oob_hotplug_event()
6144 	spin_lock_irq(&i915->irq_lock);  in intel_dp_oob_hotplug_event()
6145 	if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {  in intel_dp_oob_hotplug_event()
6146 		display->hotplug.event_bits |= BIT(hpd_pin);  in intel_dp_oob_hotplug_event()
6149 			     &display->hotplug.oob_hotplug_last_state,  in intel_dp_oob_hotplug_event()
6153 	spin_unlock_irq(&i915->irq_lock);  in intel_dp_oob_hotplug_event()
6183 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);  in intel_dp_hpd_pulse()
6184 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_hpd_pulse()
6187 	if (dig_port->base.type == INTEL_OUTPUT_EDP &&  in intel_dp_hpd_pulse()
6189 	     intel_runtime_pm_suspended(&i915->runtime_pm) ||  in intel_dp_hpd_pulse()
6195 		 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."  in intel_dp_hpd_pulse()
6197 		drm_dbg_kms(display->drm,  in intel_dp_hpd_pulse()
6200 			    dig_port->base.base.base.id,  in intel_dp_hpd_pulse()
6201 			    dig_port->base.base.name);  in intel_dp_hpd_pulse()
6205 	drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",  in intel_dp_hpd_pulse()
6206 		    dig_port->base.base.base.id,  in intel_dp_hpd_pulse()
6207 		    dig_port->base.base.name,  in intel_dp_hpd_pulse()
6211 	 * TBT DP tunnels require the GFX driver to read out the DPRX caps in  in intel_dp_hpd_pulse()
6212 	 * response to long HPD pulses. The DP hotplug handler does that,  in intel_dp_hpd_pulse()
6214 	 * connector's/encoder's hotplug handler. Since the TBT CM may not  in intel_dp_hpd_pulse()
6215 	 * complete the DP tunnel BW request for the latter connector/encoder  in intel_dp_hpd_pulse()
6222 		intel_dp->reset_link_params = true;  in intel_dp_hpd_pulse()
6228 	if (intel_dp->is_mst) {  in intel_dp_hpd_pulse()
6267 	enum port port = encoder->port;  in intel_dp_has_gamut_metadata_dip()
6269 	if (intel_bios_encoder_is_lspcon(encoder->devdata))  in intel_dp_has_gamut_metadata_dip()
6278 	if (display->platform.haswell || display->platform.broadwell ||  in intel_dp_has_gamut_metadata_dip()
6286 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)  in intel_dp_add_properties()  argument
6289 	enum port port = dp_to_dig_port(intel_dp)->base.port;  in intel_dp_add_properties()
6292 		drm_connector_attach_dp_subconnector_property(connector);  in intel_dp_add_properties()
6294 	if (!display->platform.g4x && port != PORT_A)  in intel_dp_add_properties()
6295 		intel_attach_force_audio_property(connector);  in intel_dp_add_properties()
6297 	intel_attach_broadcast_rgb_property(connector);  in intel_dp_add_properties()
6299 		drm_connector_attach_max_bpc_property(connector, 6, 10);  in intel_dp_add_properties()
6301 		drm_connector_attach_max_bpc_property(connector, 6, 12);  in intel_dp_add_properties()
6304 	if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {  in intel_dp_add_properties()
6305 		drm_connector_attach_content_type_property(connector);  in intel_dp_add_properties()
6306 		intel_attach_hdmi_colorspace_property(connector);  in intel_dp_add_properties()
6308 		intel_attach_dp_colorspace_property(connector);  in intel_dp_add_properties()
6311 	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))  in intel_dp_add_properties()
6312 		drm_connector_attach_hdr_output_metadata_property(connector);  in intel_dp_add_properties()
6315 		drm_connector_attach_vrr_capable_property(connector);  in intel_dp_add_properties()
6322 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_add_properties()  local
6324 		intel_panel_preferred_fixed_mode(connector);  in intel_edp_add_properties()
6326 	intel_attach_scaling_mode_property(&connector->base);  in intel_edp_add_properties()
6328 	drm_connector_set_panel_orientation_with_quirk(&connector->base,  in intel_edp_add_properties()
6329 						       display->vbt.orientation,  in intel_edp_add_properties()
6330 						       fixed_mode->hdisplay,  in intel_edp_add_properties()
6331 						       fixed_mode->vdisplay);  in intel_edp_add_properties()
6335 				      struct intel_connector *connector)  in intel_edp_backlight_setup()  argument
6340 	if (display->platform.valleyview || display->platform.cherryview)  in intel_edp_backlight_setup()
6343 	intel_backlight_setup(connector, pipe);  in intel_edp_backlight_setup()
6347 				     struct intel_connector *connector)  in intel_edp_init_connector()  argument
6350 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_edp_init_connector()
6352 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_edp_init_connector()
6363 	 * with an already powered-on LVDS power sequencer.  in intel_edp_init_connector()
6366 		drm_WARN_ON(display->drm,  in intel_edp_init_connector()
6368 		drm_info(display->drm,  in intel_edp_init_connector()
6374 	intel_bios_init_panel_early(display, &connector->panel,  in intel_edp_init_connector()
6375 				    encoder->devdata);  in intel_edp_init_connector()
6378 		drm_info(display->drm,  in intel_edp_init_connector()
6380 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6401 	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);  in intel_edp_init_connector()
6405 		drm_info(display->drm,  in intel_edp_init_connector()
6407 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6419 	if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {  in intel_edp_init_connector()
6428 			drm_info(display->drm,  in intel_edp_init_connector()
6430 				 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6436 		 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall  in intel_edp_init_connector()
6440 		if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&  in intel_edp_init_connector()
6441 		    (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==  in intel_edp_init_connector()
6443 			drm_info(display->drm,  in intel_edp_init_connector()
6445 				 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6450 	mutex_lock(&display->drm->mode_config.mutex);  in intel_edp_init_connector()
6451 	drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);  in intel_edp_init_connector()
6454 		drm_edid = intel_opregion_get_edid(connector);  in intel_edp_init_connector()
6456 			drm_dbg_kms(display->drm,  in intel_edp_init_connector()
6457 				    "[CONNECTOR:%d:%s] Using OpRegion EDID\n",  in intel_edp_init_connector()
6458 				    connector->base.base.id, connector->base.name);  in intel_edp_init_connector()
6461 		if (drm_edid_connector_update(&connector->base, drm_edid) ||  in intel_edp_init_connector()
6462 		    !drm_edid_connector_add_modes(&connector->base)) {  in intel_edp_init_connector()
6463 			drm_edid_connector_update(&connector->base, NULL);  in intel_edp_init_connector()
6465 			drm_edid = ERR_PTR(-EINVAL);  in intel_edp_init_connector()
6468 		drm_edid = ERR_PTR(-ENOENT);  in intel_edp_init_connector()
6471 	intel_bios_init_panel_late(display, &connector->panel, encoder->devdata,  in intel_edp_init_connector()
6474 	intel_panel_add_edid_fixed_modes(connector, true);  in intel_edp_init_connector()
6480 	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head)  in intel_edp_init_connector()
6481 		intel_edp_mso_mode_fixup(connector, fixed_mode);  in intel_edp_init_connector()
6484 	if (!intel_panel_preferred_fixed_mode(connector))  in intel_edp_init_connector()
6485 		intel_panel_add_vbt_lfp_fixed_mode(connector);  in intel_edp_init_connector()
6487 	mutex_unlock(&display->drm->mode_config.mutex);  in intel_edp_init_connector()
6489 	if (!intel_panel_preferred_fixed_mode(connector)) {  in intel_edp_init_connector()
6490 		drm_info(display->drm,  in intel_edp_init_connector()
6492 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6496 	intel_panel_init(connector, drm_edid);  in intel_edp_init_connector()
6498 	intel_edp_backlight_setup(intel_dp, connector);  in intel_edp_init_connector()
6508 	intel_bios_fini_panel(&connector->panel);  in intel_edp_init_connector()
6515 			struct intel_connector *connector)  in intel_dp_init_connector()  argument
6518 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_init_connector()
6519 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_init_connector()
6520 	struct drm_device *dev = encoder->base.dev;  in intel_dp_init_connector()
6521 	enum port port = encoder->port;  in intel_dp_init_connector()
6524 	if (drm_WARN(dev, dig_port->max_lanes < 1,  in intel_dp_init_connector()
6525 		     "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",  in intel_dp_init_connector()
6526 		     dig_port->max_lanes, encoder->base.base.id,  in intel_dp_init_connector()
6527 		     encoder->base.name))  in intel_dp_init_connector()
6530 	intel_dp->reset_link_params = true;  in intel_dp_init_connector()
6533 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg);  in intel_dp_init_connector()
6534 	intel_dp->attached_connector = connector;  in intel_dp_init_connector()
6536 	if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {  in intel_dp_init_connector()
6544 		encoder->type = INTEL_OUTPUT_EDP;  in intel_dp_init_connector()
6547 		if (drm_WARN_ON(dev, (display->platform.valleyview ||  in intel_dp_init_connector()
6548 				      display->platform.cherryview) &&  in intel_dp_init_connector()
6558 	if (display->platform.valleyview || display->platform.cherryview)  in intel_dp_init_connector()
6562 	connector->dp.dsc_decompression_aux = &intel_dp->aux;  in intel_dp_init_connector()
6564 	drm_dbg_kms(display->drm,  in intel_dp_init_connector()
6565 		    "Adding %s connector on [ENCODER:%d:%s]\n",  in intel_dp_init_connector()
6566 		    type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",  in intel_dp_init_connector()
6567 		    encoder->base.base.id, encoder->base.name);  in intel_dp_init_connector()
6569 	drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs,  in intel_dp_init_connector()
6570 				    type, &intel_dp->aux.ddc);  in intel_dp_init_connector()
6571 	drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs);  in intel_dp_init_connector()
6574 		connector->base.interlace_allowed = true;  in intel_dp_init_connector()
6577 		connector->polled = DRM_CONNECTOR_POLL_HPD;  in intel_dp_init_connector()
6578 	connector->base.polled = connector->polled;  in intel_dp_init_connector()
6580 	intel_connector_attach_encoder(connector, encoder);  in intel_dp_init_connector()
6583 		connector->get_hw_state = intel_ddi_connector_get_hw_state;  in intel_dp_init_connector()
6585 		connector->get_hw_state = intel_connector_get_hw_state;  in intel_dp_init_connector()
6586 	connector->sync_state = intel_dp_connector_sync_state;  in intel_dp_init_connector()
6588 	if (!intel_edp_init_connector(intel_dp, connector)) {  in intel_dp_init_connector()
6598 	intel_dp_mst_encoder_init(dig_port, connector->base.base.id);  in intel_dp_init_connector()
6600 	intel_dp_add_properties(intel_dp, &connector->base);  in intel_dp_init_connector()
6603 		int ret = intel_dp_hdcp_init(dig_port, connector);  in intel_dp_init_connector()
6605 			drm_dbg_kms(display->drm,  in intel_dp_init_connector()
6609 	intel_dp->frl.is_trained = false;  in intel_dp_init_connector()
6610 	intel_dp->frl.trained_rate_gbps = 0;  in intel_dp_init_connector()
6618 	drm_connector_cleanup(&connector->base);  in intel_dp_init_connector()
6630 	for_each_intel_encoder(display->drm, encoder) {  in intel_dp_mst_suspend()
6633 		if (encoder->type != INTEL_OUTPUT_DDI)  in intel_dp_mst_suspend()
6641 		if (intel_dp->is_mst)  in intel_dp_mst_suspend()
6642 			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr);  in intel_dp_mst_suspend()
6653 	for_each_intel_encoder(display->drm, encoder) {  in intel_dp_mst_resume()
6657 		if (encoder->type != INTEL_OUTPUT_DDI)  in intel_dp_mst_resume()
6665 		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true);  in intel_dp_mst_resume()
6667 			intel_dp->is_mst = false;  in intel_dp_mst_resume()
6668 			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false);  in intel_dp_mst_resume()