Lines Matching +full:0 +full:x8f000
69 { .start = 0x44400, .end = 0x4447f }, /* PIPE interrupt registers */
70 { .start = 0x60000, .end = 0x7ffff },
75 { .start = 0x45500 }, /* DC_STATE_SEL */
76 { .start = 0x457a0, .end = 0x457b0 }, /* DC*_RESIDENCY_COUNTER */
77 { .start = 0x45504 }, /* DC_STATE_EN */
78 { .start = 0x45400, .end = 0x4540c }, /* PWR_WELL_CTL_* */
79 { .start = 0x454f0 }, /* RETENTION_CTRL */
82 { .start = 0x44300 },
83 { .start = 0x44304 },
84 { .start = 0x44f00 },
85 { .start = 0x44f04 },
86 { .start = 0x44fe8 },
87 { .start = 0x45008 },
89 { .start = 0x46070 }, /* CDCLK_PLL_ENABLE */
90 { .start = 0x46000 }, /* CDCLK_CTL */
91 { .start = 0x46008 }, /* CDCLK_SQUASH_CTL */
94 { .start = 0x6fa88 },
95 { .start = 0x6fb88 },
97 { .start = 0x46430 }, /* CHICKEN_DCPR_1 */
98 { .start = 0x46434 }, /* CHICKEN_DCPR_2 */
99 { .start = 0x454a0 }, /* CHICKEN_DCPR_4 */
100 { .start = 0x42084 }, /* CHICKEN_MISC_2 */
101 { .start = 0x42088 }, /* CHICKEN_MISC_3 */
102 { .start = 0x46160 }, /* CMTG_CLK_SEL */
103 { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */
104 { .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */
110 { .start = 0x454a0 }, /* CHICKEN_DCPR_4 */
112 { .start = 0x45504 }, /* DC_STATE_EN */
115 { .start = 0x44300 },
116 { .start = 0x44304 },
117 { .start = 0x44f00 },
118 { .start = 0x44f04 },
119 { .start = 0x44fe8 },
120 { .start = 0x45008 },
122 { .start = 0x46070 }, /* CDCLK_PLL_ENABLE */
123 { .start = 0x46000 }, /* CDCLK_CTL */
124 { .start = 0x46008 }, /* CDCLK_SQUASH_CTL */
125 { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */
128 { .start = 0x70000 },
129 { .start = 0x70004 },
130 { .start = 0x70014 },
131 { .start = 0x70018 },
132 { .start = 0x71000 },
133 { .start = 0x71004 },
134 { .start = 0x71014 },
135 { .start = 0x71018 },
136 { .start = 0x72000 },
137 { .start = 0x72004 },
138 { .start = 0x72014 },
139 { .start = 0x72018 },
140 { .start = 0x73000 },
141 { .start = 0x73004 },
142 { .start = 0x73014 },
143 { .start = 0x73018 },
144 { .start = 0x7b000 },
145 { .start = 0x7b004 },
146 { .start = 0x7b014 },
147 { .start = 0x7b018 },
148 { .start = 0x7c000 },
149 { .start = 0x7c004 },
150 { .start = 0x7c014 },
151 { .start = 0x7c018 },
184 __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0); in intel_dmc_wl_work()
187 DMC_WAKELOCK_CTL_ACK, 0, in intel_dmc_wl_work()
212 __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, 0, in __intel_dmc_wl_take()
235 for (int i = 0; ranges[i].start; i++) { in intel_dmc_wl_reg_in_range()
294 } else if (display->params.enable_dmc_wl < 0) { in intel_dmc_wl_sanitize_param()
304 display->params.enable_dmc_wl < 0 || in intel_dmc_wl_sanitize_param()
341 display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0); in intel_dmc_wl_init()
365 __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE); in intel_dmc_wl_enable()
407 __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0); in intel_dmc_wl_disable()
419 __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0); in intel_dmc_wl_disable()