44 	 * Synchronize the well's hw state to match the current sw state, for
52 	 * Enable the well and resources that depend on it (for example
53 	 * interrupts located on the well). Called after the 0->1 refcount
59 	 * Disable the well and resources that depend on it. Called after
89 	 * the first power well and hope the WARN gets reported so we can fix  in lookup_power_well()
93 		 "Power well %d not defined for this platform\n",  in lookup_power_well()
132 		 "Use count on power well %s is already zero",  in intel_power_well_put()
181  * Starting with Haswell, we have a "Power Down Well" that can be turned off
182  * when not needed anymore. We have 4 registers that can request the power well
283 		drm_dbg_kms(display->drm, "%s power well enable timeout\n",  in hsw_wait_for_power_well_enable()
318 	 * - a KVMR request on any power well via the KVMR request register  in hsw_wait_for_power_well_disable()
363 		 * before enabling the power well and PW1/PG1's own fuse  in hsw_power_well_enable()
579  * We should only use the power well if we explicitly asked the hardware to
622 		      "Power well 2 on.\n");  in assert_can_enable_dc9()
1119 			"timeout setting power well state %08x (%08x)\n",  in vlv_set_power_well()
1339 	 * reset (ie. the power well has been disabled at  in assert_chv_phy_status()
1539 	 * reset (ie. the power well has been disabled at  in assert_chv_phy_powergate()
1716 			"timeout setting power well state %08x (%08x)\n",  in chv_set_pipe_power_well()
1878 		drm_dbg_kms(display->drm, "pica power well enable timeout\n");  in xe2lpd_pica_power_well_enable()
1880 		drm_WARN(display->drm, 1, "Power well PICA timeout when enabled");  in xe2lpd_pica_power_well_enable()
1891 		drm_dbg_kms(display->drm, "pica power well disable timeout\n");  in xe2lpd_pica_power_well_disable()
1893 		drm_WARN(display->drm, 1, "Power well PICA timeout when disabled");  in xe2lpd_pica_power_well_disable()