Lines Matching +full:power +full:- +full:domains
1 /* SPDX-License-Identifier: MIT */
33 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
37 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
207 if (pm_runtime_suspended(display->drm->dev)) in __intel_display_power_is_enabled()
226 * intel_display_power_is_enabled - check for a power domain
228 * @domain: power domain to check
230 * This function can be used to check the hw power domain state. It is mostly
232 * upon explicit power domain reference counting to ensure that the hardware
236 * threads can't disable the power well while the caller tries to read a few
240 * True when the power domain is enabled, false otherwise.
245 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
248 mutex_lock(&power_domains->lock); in intel_display_power_is_enabled()
250 mutex_unlock(&power_domains->lock); in intel_display_power_is_enabled()
259 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
268 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { in sanitize_target_dc_state()
272 if (power_domains->allowed_dc_mask & target_dc_state) in sanitize_target_dc_state()
282 * intel_display_power_set_target_dc_state - Set target dc state.
286 * This function set the "DC off" power well target_dc_state,
287 * based upon this target_dc_stste, "DC off" power well will
295 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_set_target_dc_state()
297 mutex_lock(&power_domains->lock); in intel_display_power_set_target_dc_state()
300 if (drm_WARN_ON(display->drm, !power_well)) in intel_display_power_set_target_dc_state()
305 if (state == power_domains->target_dc_state) in intel_display_power_set_target_dc_state()
310 * If DC off power well is disabled, need to enable and disable the in intel_display_power_set_target_dc_state()
311 * DC off power well to effect target DC state. in intel_display_power_set_target_dc_state()
316 power_domains->target_dc_state = state; in intel_display_power_set_target_dc_state()
322 mutex_unlock(&power_domains->lock); in intel_display_power_set_target_dc_state()
328 bitmap_or(mask->bits, in __async_put_domains_mask()
329 power_domains->async_put_domains[0].bits, in __async_put_domains_mask()
330 power_domains->async_put_domains[1].bits, in __async_put_domains_mask()
341 power.domains); in assert_async_put_domain_masks_disjoint()
343 return !drm_WARN_ON(display->drm, in assert_async_put_domain_masks_disjoint()
344 bitmap_intersects(power_domains->async_put_domains[0].bits, in assert_async_put_domain_masks_disjoint()
345 power_domains->async_put_domains[1].bits, in assert_async_put_domain_masks_disjoint()
354 power.domains); in __async_put_domains_state_ok()
361 err |= drm_WARN_ON(display->drm, in __async_put_domains_state_ok()
362 !!power_domains->async_put_wakeref != in __async_put_domains_state_ok()
366 err |= drm_WARN_ON(display->drm, in __async_put_domains_state_ok()
367 power_domains->domain_use_count[domain] != 1); in __async_put_domains_state_ok()
377 power.domains); in print_power_domains()
380 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); in print_power_domains()
382 drm_dbg_kms(display->drm, "%s use_count %d\n", in print_power_domains()
384 power_domains->domain_use_count[domain]); in print_power_domains()
392 power.domains); in print_async_put_domains_state()
394 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", in print_async_put_domains_state()
395 str_yes_no(power_domains->async_put_wakeref)); in print_async_put_domains_state()
398 &power_domains->async_put_domains[0]); in print_async_put_domains_state()
400 &power_domains->async_put_domains[1]); in print_async_put_domains_state()
439 clear_bit(domain, power_domains->async_put_domains[0].bits); in async_put_domains_clear_domain()
440 clear_bit(domain, power_domains->async_put_domains[1].bits); in async_put_domains_clear_domain()
447 cancel_delayed_work_sync(&power_domains->async_put_work); in cancel_async_put_work()
449 cancel_delayed_work(&power_domains->async_put_work); in cancel_async_put_work()
451 power_domains->async_put_next_delay = 0; in cancel_async_put_work()
458 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_grab_async_put_ref()
459 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_grab_async_put_ref()
476 intel_runtime_pm_put_raw(&dev_priv->runtime_pm, in intel_display_power_grab_async_put_ref()
477 fetch_and_zero(&power_domains->async_put_wakeref)); in intel_display_power_grab_async_put_ref()
488 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_get_domain()
497 power_domains->domain_use_count[domain]++; in __intel_display_power_get_domain()
501 * intel_display_power_get - grab a power domain reference
503 * @domain: power domain to reference
505 * This function grabs a power domain reference for @domain and ensures that the
506 * power domain and all its parents are powered up. Therefore users should only
507 * grab a reference to the innermost power domain they need.
509 * Any power domain reference obtained by this function must have a symmetric
515 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_get()
516 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get()
517 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_display_power_get()
519 mutex_lock(&power_domains->lock); in intel_display_power_get()
521 mutex_unlock(&power_domains->lock); in intel_display_power_get()
527 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
529 * @domain: power domain to reference
531 * This function grabs a power domain reference for @domain and ensures that the
532 * power domain and all its parents are powered up. Therefore users should only
533 * grab a reference to the innermost power domain they need.
535 * Any power domain reference obtained by this function must have a symmetric
542 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_get_if_enabled()
543 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get_if_enabled()
547 wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm); in intel_display_power_get_if_enabled()
551 mutex_lock(&power_domains->lock); in intel_display_power_get_if_enabled()
560 mutex_unlock(&power_domains->lock); in intel_display_power_get_if_enabled()
563 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in intel_display_power_get_if_enabled()
574 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put_domain()
579 drm_WARN(display->drm, !power_domains->domain_use_count[domain], in __intel_display_power_put_domain()
583 drm_WARN(display->drm, in __intel_display_power_put_domain()
588 power_domains->domain_use_count[domain]--; in __intel_display_power_put_domain()
597 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put()
599 mutex_lock(&power_domains->lock); in __intel_display_power_put()
601 mutex_unlock(&power_domains->lock); in __intel_display_power_put()
611 power.domains); in queue_async_put_domains_work()
612 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); in queue_async_put_domains_work()
613 power_domains->async_put_wakeref = wakeref; in queue_async_put_domains_work()
614 drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq, in queue_async_put_domains_work()
615 &power_domains->async_put_work, in queue_async_put_domains_work()
625 power.domains); in release_async_put_domains()
626 struct drm_i915_private *dev_priv = to_i915(display->drm); in release_async_put_domains()
627 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; in release_async_put_domains()
646 power.domains.async_put_work.work); in intel_display_power_put_async_work()
647 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_put_async_work()
648 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_put_async_work()
649 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; in intel_display_power_put_async_work()
653 mutex_lock(&power_domains->lock); in intel_display_power_put_async_work()
659 old_work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); in intel_display_power_put_async_work()
664 &power_domains->async_put_domains[0]); in intel_display_power_put_async_work()
668 * since here we released the corresponding async-put reference. in intel_display_power_put_async_work()
672 /* Requeue the work if more domains were async put meanwhile. */ in intel_display_power_put_async_work()
673 if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { in intel_display_power_put_async_work()
674 bitmap_copy(power_domains->async_put_domains[0].bits, in intel_display_power_put_async_work()
675 power_domains->async_put_domains[1].bits, in intel_display_power_put_async_work()
677 bitmap_zero(power_domains->async_put_domains[1].bits, in intel_display_power_put_async_work()
681 power_domains->async_put_next_delay); in intel_display_power_put_async_work()
682 power_domains->async_put_next_delay = 0; in intel_display_power_put_async_work()
688 mutex_unlock(&power_domains->lock); in intel_display_power_put_async_work()
697 * __intel_display_power_put_async - release a power domain reference asynchronously
699 * @domain: power domain to reference
701 * @delay_ms: delay of powering down the power domain
703 * This function drops the power domain reference obtained by
704 * intel_display_power_get*() and schedules a work to power down the
706 * The power down is delayed by @delay_ms if this is >= 0, or by a default
714 struct drm_i915_private *i915 = to_i915(display->drm); in __intel_display_power_put_async()
715 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put_async()
716 struct intel_runtime_pm *rpm = &i915->runtime_pm; in __intel_display_power_put_async()
721 mutex_lock(&power_domains->lock); in __intel_display_power_put_async()
723 if (power_domains->domain_use_count[domain] > 1) { in __intel_display_power_put_async()
729 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); in __intel_display_power_put_async()
732 if (power_domains->async_put_wakeref) { in __intel_display_power_put_async()
733 set_bit(domain, power_domains->async_put_domains[1].bits); in __intel_display_power_put_async()
734 power_domains->async_put_next_delay = max(power_domains->async_put_next_delay, in __intel_display_power_put_async()
737 set_bit(domain, power_domains->async_put_domains[0].bits); in __intel_display_power_put_async()
746 mutex_unlock(&power_domains->lock); in __intel_display_power_put_async()
755 * intel_display_power_flush_work - flushes the async display power disabling work
760 * corresponding power domains.
768 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_flush_work()
769 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_flush_work()
773 mutex_lock(&power_domains->lock); in intel_display_power_flush_work()
775 work_wakeref = fetch_and_zero(&power_domains->async_put_wakeref); in intel_display_power_flush_work()
786 mutex_unlock(&power_domains->lock); in intel_display_power_flush_work()
789 intel_runtime_pm_put_raw(&i915->runtime_pm, work_wakeref); in intel_display_power_flush_work()
793 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
802 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_flush_work_sync()
809 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); in intel_display_power_flush_work_sync()
814 * intel_display_power_put - release a power domain reference
816 * @domain: power domain to reference
819 * This function drops the power domain reference obtained by
820 * intel_display_power_get() and might power down the corresponding hardware
827 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_put()
830 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in intel_display_power_put()
834 * intel_display_power_put_unchecked - release an unchecked power domain reference
836 * @domain: power domain to reference
838 * This function drops the power domain reference obtained by
839 * intel_display_power_get() and might power down the corresponding hardware
842 * This function is only for the power domain code's internal use to suppress wakeref
849 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_display_power_put_unchecked()
852 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); in intel_display_power_put_unchecked()
863 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); in intel_display_power_get_in_set()
867 power_domain_set->wakerefs[domain] = wf; in intel_display_power_get_in_set()
869 set_bit(domain, power_domain_set->mask.bits); in intel_display_power_get_in_set()
879 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); in intel_display_power_get_in_set_if_enabled()
886 power_domain_set->wakerefs[domain] = wf; in intel_display_power_get_in_set_if_enabled()
888 set_bit(domain, power_domain_set->mask.bits); in intel_display_power_get_in_set_if_enabled()
900 drm_WARN_ON(display->drm, in intel_display_power_put_mask_in_set()
901 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); in intel_display_power_put_mask_in_set()
907 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); in intel_display_power_put_mask_in_set()
910 clear_bit(domain, power_domain_set->mask.bits); in intel_display_power_put_mask_in_set()
934 else if (display->platform.dg2) in get_allowed_dc_mask()
936 else if (display->platform.dg1) in get_allowed_dc_mask()
940 else if (display->platform.geminilake || display->platform.broxton) in get_allowed_dc_mask()
952 mask = display->platform.geminilake || display->platform.broxton || in get_allowed_dc_mask()
955 if (!display->params.disable_power_well) in get_allowed_dc_mask()
960 } else if (enable_dc == -1) { in get_allowed_dc_mask()
963 drm_dbg_kms(display->drm, in get_allowed_dc_mask()
964 "Adjusting requested max DC state (%d->%d)\n", in get_allowed_dc_mask()
968 drm_err(display->drm, in get_allowed_dc_mask()
988 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); in get_allowed_dc_mask()
994 * intel_power_domains_init - initializes the power domain structures
997 * Initializes the power domain structures for @display depending upon the
1002 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_init()
1004 display->params.disable_power_well = in intel_power_domains_init()
1005 sanitize_disable_power_well_option(display->params.disable_power_well); in intel_power_domains_init()
1006 power_domains->allowed_dc_mask = in intel_power_domains_init()
1007 get_allowed_dc_mask(display, display->params.enable_dc); in intel_power_domains_init()
1009 power_domains->target_dc_state = in intel_power_domains_init()
1012 mutex_init(&power_domains->lock); in intel_power_domains_init()
1014 INIT_DELAYED_WORK(&power_domains->async_put_work, in intel_power_domains_init()
1021 * intel_power_domains_cleanup - clean up power domains resources
1028 intel_display_power_map_cleanup(&display->power.domains); in intel_power_domains_cleanup()
1033 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_sync_hw()
1036 mutex_lock(&power_domains->lock); in intel_power_domains_sync_hw()
1039 mutex_unlock(&power_domains->lock); in intel_power_domains_sync_hw()
1054 drm_WARN(display->drm, enable != state, in gen9_dbuf_slice_set()
1055 "DBuf slice %d power %s timeout!\n", in gen9_dbuf_slice_set()
1062 struct i915_power_domains *power_domains = &display->power.domains; in gen9_dbuf_slices_update()
1063 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; in gen9_dbuf_slices_update()
1066 drm_WARN(display->drm, req_slices & ~slice_mask, in gen9_dbuf_slices_update()
1070 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", in gen9_dbuf_slices_update()
1080 mutex_lock(&power_domains->lock); in gen9_dbuf_slices_update()
1085 display->dbuf.enabled_slices = req_slices; in gen9_dbuf_slices_update()
1087 mutex_unlock(&power_domains->lock); in gen9_dbuf_slices_update()
1094 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display); in gen9_dbuf_enable()
1096 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; in gen9_dbuf_enable()
1102 * Just power up at least 1 slice, we will in gen9_dbuf_enable()
1128 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; in icl_mbus_init()
1131 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) in icl_mbus_init()
1146 * we don't have to program other instance-0 registers like BW_BUDDY. in icl_mbus_init()
1166 drm_err(display->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1169 drm_err(display->drm, "LCPLL is disabled\n"); in hsw_assert_cdclk()
1172 drm_err(display->drm, "LCPLL not using non-SSC reference\n"); in hsw_assert_cdclk()
1177 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_can_disable_lcpll()
1180 for_each_intel_crtc(display->drm, crtc) in assert_can_disable_lcpll()
1181 INTEL_DISPLAY_STATE_WARN(display, crtc->active, in assert_can_disable_lcpll()
1183 pipe_name(crtc->pipe)); in assert_can_disable_lcpll()
1186 "Display power well on\n"); in assert_can_disable_lcpll()
1198 "Panel power on\n"); in assert_can_disable_lcpll()
1202 if (display->platform.haswell) in assert_can_disable_lcpll()
1219 * gen-specific and since we only disable LCPLL after we fully disable in assert_can_disable_lcpll()
1228 if (display->platform.haswell) in hsw_read_dcomp()
1236 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_write_dcomp()
1238 if (display->platform.haswell) { in hsw_write_dcomp()
1239 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val)) in hsw_write_dcomp()
1240 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); in hsw_write_dcomp()
1249 * - Sequence for display software to disable LCPLL
1250 * - Sequence for display software to allow package C8+
1270 drm_err(display->drm, "Switching to FCLK failed\n"); in hsw_disable_lcpll()
1280 drm_err(display->drm, "LCPLL still locked\n"); in hsw_disable_lcpll()
1289 drm_err(display->drm, "D_COMP RCOMP still in progress\n"); in hsw_disable_lcpll()
1298 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
1303 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); in hsw_restore_lcpll()
1316 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); in hsw_restore_lcpll()
1334 drm_err(display->drm, "LCPLL not locked yet\n"); in hsw_restore_lcpll()
1341 drm_err(display->drm, in hsw_restore_lcpll()
1345 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); in hsw_restore_lcpll()
1348 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
1357 * The requirements for PC8+ are that all the outputs are disabled, the power
1361 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
1376 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_enable_pc8()
1378 drm_dbg_kms(display->drm, "Enabling package C8+\n"); in hsw_enable_pc8()
1390 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_disable_pc8()
1392 drm_dbg_kms(display->drm, "Disabling package C8+\n"); in hsw_disable_pc8()
1409 if (display->platform.ivybridge) { in intel_pch_reset_handshake()
1426 struct drm_i915_private *dev_priv = to_i915(display->drm); in skl_display_core_init()
1427 struct i915_power_domains *power_domains = &display->power.domains; in skl_display_core_init()
1439 mutex_lock(&power_domains->lock); in skl_display_core_init()
1447 mutex_unlock(&power_domains->lock); in skl_display_core_init()
1459 struct i915_power_domains *power_domains = &display->power.domains; in skl_display_core_uninit()
1475 mutex_lock(&power_domains->lock); in skl_display_core_uninit()
1478 * BSpec says to keep the MISC IO power well enabled here, only in skl_display_core_uninit()
1479 * remove our request for power well 1. in skl_display_core_uninit()
1480 * Note that even though the driver's request is removed power well 1 in skl_display_core_uninit()
1486 mutex_unlock(&power_domains->lock); in skl_display_core_uninit()
1493 struct i915_power_domains *power_domains = &display->power.domains; in bxt_display_core_init()
1510 mutex_lock(&power_domains->lock); in bxt_display_core_init()
1515 mutex_unlock(&power_domains->lock); in bxt_display_core_init()
1527 struct i915_power_domains *power_domains = &display->power.domains; in bxt_display_core_uninit()
1544 * Note that even though the driver's request is removed power well 1 in bxt_display_core_uninit()
1547 mutex_lock(&power_domains->lock); in bxt_display_core_uninit()
1552 mutex_unlock(&power_domains->lock); in bxt_display_core_uninit()
1589 struct drm_i915_private *dev_priv = to_i915(display->drm); in tgl_bw_buddy_init()
1590 enum intel_dram_type type = dev_priv->dram_info.type; in tgl_bw_buddy_init()
1591 u8 num_channels = dev_priv->dram_info.num_channels; in tgl_bw_buddy_init()
1593 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; in tgl_bw_buddy_init()
1597 if (display->platform.dgfx && !display->platform.dg1) in tgl_bw_buddy_init()
1600 if (display->platform.alderlake_s || in tgl_bw_buddy_init()
1601 (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))) in tgl_bw_buddy_init()
1613 drm_dbg_kms(display->drm, in tgl_bw_buddy_init()
1623 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ in tgl_bw_buddy_init()
1635 struct drm_i915_private *dev_priv = to_i915(display->drm); in icl_display_core_init()
1636 struct i915_power_domains *power_domains = &display->power.domains; in icl_display_core_init()
1641 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ in icl_display_core_init()
1657 * 3. Enable Power Well 1 (PG1). in icl_display_core_init()
1658 * The AUX IO power wells will be enabled on demand. in icl_display_core_init()
1660 mutex_lock(&power_domains->lock); in icl_display_core_init()
1663 mutex_unlock(&power_domains->lock); in icl_display_core_init()
1672 if (DISPLAY_VER(display) == 12 || display->platform.dg2) in icl_display_core_init()
1686 if (display->platform.dg2) in icl_display_core_init()
1696 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ in icl_display_core_init()
1717 struct i915_power_domains *power_domains = &display->power.domains; in icl_display_core_uninit()
1726 /* 1. Disable all display engine functions -> already done */ in icl_display_core_uninit()
1739 * 4. Disable Power Well 1 (PG1). in icl_display_core_uninit()
1740 * The AUX IO power wells are toggled on demand, so they are already in icl_display_core_uninit()
1743 mutex_lock(&power_domains->lock); in icl_display_core_uninit()
1746 mutex_unlock(&power_domains->lock); in icl_display_core_uninit()
1763 * power well state and lane status to reconstruct the in chv_phy_control_init()
1766 display->power.chv_phy_control = in chv_phy_control_init()
1775 * with all power down bits cleared to match the state we in chv_phy_control_init()
1788 display->power.chv_phy_control |= in chv_phy_control_init()
1791 display->power.chv_phy_control |= in chv_phy_control_init()
1798 display->power.chv_phy_control |= in chv_phy_control_init()
1801 display->power.chv_phy_control |= in chv_phy_control_init()
1804 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
1806 display->power.chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
1808 display->power.chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
1820 display->power.chv_phy_control |= in chv_phy_control_init()
1823 display->power.chv_phy_control |= in chv_phy_control_init()
1826 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
1828 display->power.chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
1830 display->power.chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
1833 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", in chv_phy_control_init()
1834 display->power.chv_phy_control); in chv_phy_control_init()
1852 drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); in vlv_cmnlane_wa()
1859 * Need to assert and de-assert PHY SB reset by gating the in vlv_cmnlane_wa()
1860 * common lane power, then un-gating it. in vlv_cmnlane_wa()
1869 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_punit_is_power_gated()
1881 drm_WARN(display->drm, in assert_ved_power_gated()
1883 "VED not power gated\n"); in assert_ved_power_gated()
1894 drm_WARN(display->drm, !pci_dev_present(isp_ids) && in assert_isp_power_gated()
1896 "ISP not power gated\n"); in assert_isp_power_gated()
1902 * intel_power_domains_init_hw - initialize hardware power domain state
1906 * This function initializes the hardware power domain state and enables all
1907 * power wells belonging to the INIT power domain. Power wells in other
1908 * domains (and not in the INIT domain) are referenced or disabled by
1910 * power well must match its HW enabled state, see
1913 * It will return with power domains disabled (to be enabled later by
1919 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_init_hw()
1920 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_init_hw()
1922 power_domains->initializing = true; in intel_power_domains_init_hw()
1926 } else if (display->platform.geminilake || display->platform.broxton) { in intel_power_domains_init_hw()
1930 } else if (display->platform.cherryview) { in intel_power_domains_init_hw()
1931 mutex_lock(&power_domains->lock); in intel_power_domains_init_hw()
1933 mutex_unlock(&power_domains->lock); in intel_power_domains_init_hw()
1935 } else if (display->platform.valleyview) { in intel_power_domains_init_hw()
1936 mutex_lock(&power_domains->lock); in intel_power_domains_init_hw()
1938 mutex_unlock(&power_domains->lock); in intel_power_domains_init_hw()
1941 } else if (display->platform.broadwell || display->platform.haswell) { in intel_power_domains_init_hw()
1944 } else if (display->platform.ivybridge) { in intel_power_domains_init_hw()
1949 * Keep all power wells enabled for any dependent HW access during in intel_power_domains_init_hw()
1954 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_init_hw()
1955 power_domains->init_wakeref = in intel_power_domains_init_hw()
1958 /* Disable power support if the user asked so. */ in intel_power_domains_init_hw()
1959 if (!display->params.disable_power_well) { in intel_power_domains_init_hw()
1960 drm_WARN_ON(display->drm, power_domains->disable_wakeref); in intel_power_domains_init_hw()
1961 display->power.domains.disable_wakeref = intel_display_power_get(display, in intel_power_domains_init_hw()
1966 power_domains->initializing = false; in intel_power_domains_init_hw()
1970 * intel_power_domains_driver_remove - deinitialize hw power domain state
1973 * De-initializes the display power domain HW state. It also ensures that the
1976 * It must be called with power domains already disabled (after a call to
1982 struct drm_i915_private *i915 = to_i915(display->drm); in intel_power_domains_driver_remove()
1984 fetch_and_zero(&display->power.domains.init_wakeref); in intel_power_domains_driver_remove()
1986 /* Remove the refcount we took to keep power well support disabled. */ in intel_power_domains_driver_remove()
1987 if (!display->params.disable_power_well) in intel_power_domains_driver_remove()
1989 fetch_and_zero(&display->power.domains.disable_wakeref)); in intel_power_domains_driver_remove()
1995 /* Keep the power well enabled, but cancel its rpm wakeref. */ in intel_power_domains_driver_remove()
1996 intel_runtime_pm_put(&i915->runtime_pm, wakeref); in intel_power_domains_driver_remove()
2000 * intel_power_domains_sanitize_state - sanitize power domains state
2003 * Sanitize the power domains state during driver loading and system resume.
2004 * The function will disable all display power wells that BIOS has enabled
2005 * without a user for it (any user for a power well has taken a reference
2011 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_sanitize_state()
2014 mutex_lock(&power_domains->lock); in intel_power_domains_sanitize_state()
2017 if (power_well->desc->always_on || power_well->count || in intel_power_domains_sanitize_state()
2021 drm_dbg_kms(display->drm, in intel_power_domains_sanitize_state()
2022 "BIOS left unused %s power well enabled, disabling it\n", in intel_power_domains_sanitize_state()
2027 mutex_unlock(&power_domains->lock); in intel_power_domains_sanitize_state()
2031 * intel_power_domains_enable - enable toggling of display power wells
2034 * Enable the ondemand enabling/disabling of the display power wells. Note that
2035 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled
2038 * of these function is to keep the rest of power wells enabled until the end
2039 * of display HW readout (which will acquire the power references reflecting
2045 fetch_and_zero(&display->power.domains.init_wakeref); in intel_power_domains_enable()
2052 * intel_power_domains_disable - disable toggling of display power wells
2055 * Disable the ondemand enabling/disabling of the display power wells. See
2056 * intel_power_domains_enable() for which power wells this call controls.
2060 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_disable()
2062 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_disable()
2063 power_domains->init_wakeref = in intel_power_domains_disable()
2070 * intel_power_domains_suspend - suspend power domain state
2074 * This function prepares the hardware power domain state before entering
2077 * It must be called with power domains already disabled (after a call to
2082 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_suspend()
2084 fetch_and_zero(&power_domains->init_wakeref); in intel_power_domains_suspend()
2089 * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 in intel_power_domains_suspend()
2090 * support don't manually deinit the power domains. This also means the in intel_power_domains_suspend()
2091 * DMC firmware will stay active, it will power down any HW in intel_power_domains_suspend()
2092 * resources as required and also enable deeper system power states in intel_power_domains_suspend()
2095 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && in intel_power_domains_suspend()
2103 * Even if power well support was disabled we still want to disable in intel_power_domains_suspend()
2104 * power wells if power domains must be deinitialized for suspend. in intel_power_domains_suspend()
2106 if (!display->params.disable_power_well) in intel_power_domains_suspend()
2108 fetch_and_zero(&display->power.domains.disable_wakeref)); in intel_power_domains_suspend()
2115 else if (display->platform.geminilake || display->platform.broxton) in intel_power_domains_suspend()
2120 power_domains->display_core_suspended = true; in intel_power_domains_suspend()
2124 * intel_power_domains_resume - resume power domain state
2127 * This function resume the hardware power domain state during system resume.
2129 * It will return with power domain support disabled (to be enabled later by
2135 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_resume()
2137 if (power_domains->display_core_suspended) { in intel_power_domains_resume()
2139 power_domains->display_core_suspended = false; in intel_power_domains_resume()
2141 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_resume()
2142 power_domains->init_wakeref = in intel_power_domains_resume()
2153 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_dump_info()
2159 drm_dbg_kms(display->drm, "%-25s %d\n", in intel_power_domains_dump_info()
2163 drm_dbg_kms(display->drm, " %-23s %d\n", in intel_power_domains_dump_info()
2165 power_domains->domain_use_count[domain]); in intel_power_domains_dump_info()
2170 * intel_power_domains_verify_state - verify the HW/SW state for all power wells
2173 * Verify if the reference count of each power well matches its HW enabled
2174 * state and the total refcount of the domains it belongs to. This must be
2176 * acquiring reference counts for any power wells in use and disabling the
2181 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_verify_state()
2185 mutex_lock(&power_domains->lock); in intel_power_domains_verify_state()
2199 drm_err(display->drm, in intel_power_domains_verify_state()
2200 "power well %s state mismatch (refcount %d/enabled %d)", in intel_power_domains_verify_state()
2206 domains_count += power_domains->domain_use_count[domain]; in intel_power_domains_verify_state()
2209 drm_err(display->drm, in intel_power_domains_verify_state()
2210 "power well %s refcount/domain refcount mismatch " in intel_power_domains_verify_state()
2211 "(refcount %d/domains refcount %d)\n", in intel_power_domains_verify_state()
2228 mutex_unlock(&power_domains->lock); in intel_power_domains_verify_state()
2241 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_suspend_late()
2245 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_suspend_late()
2246 display->platform.broxton) { in intel_display_power_suspend_late()
2248 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_suspend_late()
2259 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_power_resume_early()
2261 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_resume_early()
2262 display->platform.broxton) { in intel_display_power_resume_early()
2265 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_resume_early()
2281 } else if (display->platform.geminilake || display->platform.broxton) { in intel_display_power_suspend()
2284 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_suspend()
2291 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_resume()
2297 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) in intel_display_power_resume()
2299 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) in intel_display_power_resume()
2302 } else if (display->platform.geminilake || display->platform.broxton) { in intel_display_power_resume()
2306 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) in intel_display_power_resume()
2308 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_resume()
2315 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_debug()
2318 mutex_lock(&power_domains->lock); in intel_display_power_debug()
2320 seq_printf(m, "Runtime power status: %s\n", in intel_display_power_debug()
2321 str_enabled_disabled(!power_domains->init_wakeref)); in intel_display_power_debug()
2323 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); in intel_display_power_debug()
2324 for (i = 0; i < power_domains->power_well_count; i++) { in intel_display_power_debug()
2328 power_well = &power_domains->power_wells[i]; in intel_display_power_debug()
2329 seq_printf(m, "%-25s %d\n", intel_power_well_name(power_well), in intel_display_power_debug()
2333 seq_printf(m, " %-23s %d\n", in intel_display_power_debug()
2335 power_domains->domain_use_count[power_domain]); in intel_display_power_debug()
2338 mutex_unlock(&power_domains->lock); in intel_display_power_debug()
2464 const struct intel_ddi_port_domains **domains, in intel_port_domains_for_platform() argument
2468 *domains = d13_port_domains; in intel_port_domains_for_platform()
2471 *domains = d12_port_domains; in intel_port_domains_for_platform()
2474 *domains = d11_port_domains; in intel_port_domains_for_platform()
2477 *domains = i9xx_port_domains; in intel_port_domains_for_platform()
2485 const struct intel_ddi_port_domains *domains; in intel_port_domains_for_port() local
2489 intel_port_domains_for_platform(display, &domains, &domains_size); in intel_port_domains_for_port()
2491 if (port >= domains[i].port_start && port <= domains[i].port_end) in intel_port_domains_for_port()
2492 return &domains[i]; in intel_port_domains_for_port()
2500 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); in intel_display_power_ddi_io_domain() local
2502 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) in intel_display_power_ddi_io_domain()
2505 return domains->ddi_io + (int)(port - domains->port_start); in intel_display_power_ddi_io_domain()
2511 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); in intel_display_power_ddi_lanes_domain() local
2513 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) in intel_display_power_ddi_lanes_domain()
2516 return domains->ddi_lanes + (int)(port - domains->port_start); in intel_display_power_ddi_lanes_domain()
2522 const struct intel_ddi_port_domains *domains; in intel_port_domains_for_aux_ch() local
2526 intel_port_domains_for_platform(display, &domains, &domains_size); in intel_port_domains_for_aux_ch()
2528 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) in intel_port_domains_for_aux_ch()
2529 return &domains[i]; in intel_port_domains_for_aux_ch()
2537 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_aux_io_domain() local
2539 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) in intel_display_power_aux_io_domain()
2542 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); in intel_display_power_aux_io_domain()
2548 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_legacy_aux_domain() local
2550 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) in intel_display_power_legacy_aux_domain()
2553 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); in intel_display_power_legacy_aux_domain()
2559 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_tbt_aux_domain() local
2561 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) in intel_display_power_tbt_aux_domain()
2564 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start); in intel_display_power_tbt_aux_domain()