Lines Matching full:pipe
100 enum pipe pipe, u32 fault_errors) in intel_pipe_fault_irq_handler() argument
102 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_pipe_fault_irq_handler()
118 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank() argument
121 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_handle_vblank()
196 * bdw_update_pipe_irq - update DE pipe interrupt
198 * @pipe: pipe whose interrupt to update
203 enum pipe pipe, u32 interrupt_mask, in bdw_update_pipe_irq() argument
216 new_val = dev_priv->display.irq.de_irq_mask[pipe]; in bdw_update_pipe_irq()
220 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) { in bdw_update_pipe_irq()
221 dev_priv->display.irq.de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
222 intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]); in bdw_update_pipe_irq()
223 intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
228 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq() argument
230 bdw_update_pipe_irq(i915, pipe, bits, bits); in bdw_enable_pipe_irq()
234 enum pipe pipe, u32 bits) in bdw_disable_pipe_irq() argument
236 bdw_update_pipe_irq(i915, pipe, bits, 0); in bdw_disable_pipe_irq()
277 enum pipe pipe) in i915_pipestat_enable_mask() argument
280 u32 status_mask = display->irq.pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
289 * On pipe A we don't support the PSR interrupt yet, in i915_pipestat_enable_mask()
290 * on pipe B and C the same bit MBZ. in i915_pipestat_enable_mask()
296 * On pipe B and C we don't support the PSR interrupt yet, on pipe in i915_pipestat_enable_mask()
315 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", in i915_pipestat_enable_mask()
316 pipe_name(pipe), enable_mask, status_mask); in i915_pipestat_enable_mask()
322 enum pipe pipe, u32 status_mask) in i915_enable_pipestat() argument
325 i915_reg_t reg = PIPESTAT(dev_priv, pipe); in i915_enable_pipestat()
329 "pipe %c: status_mask=0x%x\n", in i915_enable_pipestat()
330 pipe_name(pipe), status_mask); in i915_enable_pipestat()
335 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
338 dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
339 enable_mask = i915_pipestat_enable_mask(display, pipe); in i915_enable_pipestat()
346 enum pipe pipe, u32 status_mask) in i915_disable_pipestat() argument
349 i915_reg_t reg = PIPESTAT(dev_priv, pipe); in i915_disable_pipestat()
353 "pipe %c: status_mask=0x%x\n", in i915_disable_pipestat()
354 pipe_name(pipe), status_mask); in i915_disable_pipestat()
359 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
362 dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
363 enable_mask = i915_pipestat_enable_mask(display, pipe); in i915_disable_pipestat()
408 enum pipe pipe, in display_pipe_crc_irq_handler() argument
414 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in display_pipe_crc_irq_handler()
444 enum pipe pipe, in display_pipe_crc_irq_handler() argument
451 enum pipe pipe) in flip_done_handler() argument
454 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in flip_done_handler()
468 enum pipe pipe) in hsw_pipe_crc_irq_handler() argument
472 display_pipe_crc_irq_handler(dev_priv, pipe, in hsw_pipe_crc_irq_handler()
473 intel_de_read(display, PIPE_CRC_RES_HSW(pipe)), in hsw_pipe_crc_irq_handler()
478 enum pipe pipe) in ivb_pipe_crc_irq_handler() argument
482 display_pipe_crc_irq_handler(dev_priv, pipe, in ivb_pipe_crc_irq_handler()
483 intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
484 intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
485 intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
486 intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
487 intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
491 enum pipe pipe) in i9xx_pipe_crc_irq_handler() argument
497 res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); in i9xx_pipe_crc_irq_handler()
502 res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); in i9xx_pipe_crc_irq_handler()
506 display_pipe_crc_irq_handler(dev_priv, pipe, in i9xx_pipe_crc_irq_handler()
507 intel_de_read(display, PIPE_CRC_RES_RED(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
508 intel_de_read(display, PIPE_CRC_RES_GREEN(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
509 intel_de_read(display, PIPE_CRC_RES_BLUE(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
516 enum pipe pipe; in i9xx_pipestat_irq_reset() local
518 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_reset()
520 PIPESTAT(dev_priv, pipe), in i9xx_pipestat_irq_reset()
523 dev_priv->display.irq.pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
531 enum pipe pipe; in i9xx_pipestat_irq_ack() local
541 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_ack()
556 switch (pipe) { in i9xx_pipestat_irq_ack()
569 status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
574 reg = PIPESTAT(dev_priv, pipe); in i9xx_pipestat_irq_ack()
575 pipe_stats[pipe] = intel_de_read(display, reg) & status_mask; in i9xx_pipestat_irq_ack()
576 enable_mask = i915_pipestat_enable_mask(display, pipe); in i9xx_pipestat_irq_ack()
579 * Clear the PIPE*STAT regs before the IIR in i9xx_pipestat_irq_ack()
582 * edge in the ISR pipe event bit if we don't clear in i9xx_pipestat_irq_ack()
587 if (pipe_stats[pipe]) { in i9xx_pipestat_irq_ack()
588 intel_de_write(display, reg, pipe_stats[pipe]); in i9xx_pipestat_irq_ack()
600 enum pipe pipe; in i915_pipestat_irq_handler() local
602 for_each_pipe(dev_priv, pipe) { in i915_pipestat_irq_handler()
603 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) in i915_pipestat_irq_handler()
604 intel_handle_vblank(dev_priv, pipe); in i915_pipestat_irq_handler()
606 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i915_pipestat_irq_handler()
609 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i915_pipestat_irq_handler()
610 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
612 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i915_pipestat_irq_handler()
613 intel_cpu_fifo_underrun_irq_handler(display, pipe); in i915_pipestat_irq_handler()
625 enum pipe pipe; in i965_pipestat_irq_handler() local
627 for_each_pipe(dev_priv, pipe) { in i965_pipestat_irq_handler()
628 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) in i965_pipestat_irq_handler()
629 intel_handle_vblank(dev_priv, pipe); in i965_pipestat_irq_handler()
631 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i965_pipestat_irq_handler()
634 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i965_pipestat_irq_handler()
635 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
637 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i965_pipestat_irq_handler()
638 intel_cpu_fifo_underrun_irq_handler(display, pipe); in i965_pipestat_irq_handler()
652 enum pipe pipe; in valleyview_pipestat_irq_handler() local
654 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
655 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
656 intel_handle_vblank(dev_priv, pipe); in valleyview_pipestat_irq_handler()
658 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) in valleyview_pipestat_irq_handler()
659 flip_done_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
661 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
662 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
664 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in valleyview_pipestat_irq_handler()
665 intel_cpu_fifo_underrun_irq_handler(display, pipe); in valleyview_pipestat_irq_handler()
675 enum pipe pipe; in ibx_irq_handler() local
703 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
704 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in ibx_irq_handler()
705 pipe_name(pipe), in ibx_irq_handler()
706 intel_de_read(display, FDI_RX_IIR(pipe))); in ibx_irq_handler()
723 static u32 ivb_err_int_pipe_fault_mask(enum pipe pipe) in ivb_err_int_pipe_fault_mask() argument
725 switch (pipe) { in ivb_err_int_pipe_fault_mask()
760 enum pipe pipe; in ivb_err_int_handler() local
771 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
774 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) in ivb_err_int_handler()
775 intel_cpu_fifo_underrun_irq_handler(display, pipe); in ivb_err_int_handler()
777 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { in ivb_err_int_handler()
779 ivb_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
781 hsw_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
784 fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe); in ivb_err_int_handler()
787 pipe, fault_errors); in ivb_err_int_handler()
797 enum pipe pipe; in cpt_serr_int_handler() local
802 for_each_pipe(dev_priv, pipe) in cpt_serr_int_handler()
803 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) in cpt_serr_int_handler()
804 intel_pch_fifo_underrun_irq_handler(display, pipe); in cpt_serr_int_handler()
812 enum pipe pipe; in cpt_irq_handler() local
837 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
838 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in cpt_irq_handler()
839 pipe_name(pipe), in cpt_irq_handler()
840 intel_de_read(display, FDI_RX_IIR(pipe))); in cpt_irq_handler()
847 static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe) in ilk_gtt_fault_pipe_fault_mask() argument
849 switch (pipe) { in ilk_gtt_fault_pipe_fault_mask()
875 enum pipe pipe; in ilk_gtt_fault_irq_handler() local
887 for_each_pipe(display, pipe) { in ilk_gtt_fault_irq_handler()
890 fault_errors = gtt_fault & ilk_gtt_fault_pipe_fault_mask(pipe); in ilk_gtt_fault_irq_handler()
893 pipe, fault_errors); in ilk_gtt_fault_irq_handler()
900 enum pipe pipe; in ilk_display_irq_handler() local
918 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
919 if (de_iir & DE_PIPE_VBLANK(pipe)) in ilk_display_irq_handler()
920 intel_handle_vblank(dev_priv, pipe); in ilk_display_irq_handler()
922 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) in ilk_display_irq_handler()
923 flip_done_handler(dev_priv, pipe); in ilk_display_irq_handler()
925 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) in ilk_display_irq_handler()
926 intel_cpu_fifo_underrun_irq_handler(display, pipe); in ilk_display_irq_handler()
928 if (de_iir & DE_PIPE_CRC_DONE(pipe)) in ilk_display_irq_handler()
929 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
952 enum pipe pipe; in ivb_display_irq_handler() local
980 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
981 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) in ivb_display_irq_handler()
982 intel_handle_vblank(dev_priv, pipe); in ivb_display_irq_handler()
984 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) in ivb_display_irq_handler()
985 flip_done_handler(dev_priv, pipe); in ivb_display_irq_handler()
1272 enum pipe pipe = INVALID_PIPE; in gen11_dsi_te_interrupt_handler() local
1301 /* Get PIPE for handling VBLANK event */ in gen11_dsi_te_interrupt_handler()
1305 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
1308 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
1311 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
1314 drm_err(&dev_priv->drm, "Invalid PIPE\n"); in gen11_dsi_te_interrupt_handler()
1318 intel_handle_vblank(dev_priv, pipe); in gen11_dsi_te_interrupt_handler()
1366 enum pipe pipe; in gen8_de_irq_handler() local
1444 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_handler()
1447 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) in gen8_de_irq_handler()
1450 iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
1453 "The master control interrupt lied (DE PIPE)!\n"); in gen8_de_irq_handler()
1457 intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
1460 intel_handle_vblank(dev_priv, pipe); in gen8_de_irq_handler()
1463 flip_done_handler(dev_priv, pipe); in gen8_de_irq_handler()
1467 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0); in gen8_de_irq_handler()
1470 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1); in gen8_de_irq_handler()
1473 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2); in gen8_de_irq_handler()
1477 hsw_pipe_crc_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
1480 intel_cpu_fifo_underrun_irq_handler(display, pipe); in gen8_de_irq_handler()
1486 pipe, fault_errors); in gen8_de_irq_handler()
1603 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_enable_vblank() local
1607 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_enable_vblank()
1616 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_disable_vblank() local
1620 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_disable_vblank()
1645 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_enable_vblank() local
1649 i915_enable_pipestat(dev_priv, pipe, in i965_enable_vblank()
1659 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_disable_vblank() local
1663 i915_disable_pipestat(dev_priv, pipe, in i965_disable_vblank()
1671 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_enable_vblank() local
1674 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); in ilk_enable_vblank()
1692 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_disable_vblank() local
1695 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); in ilk_disable_vblank()
1746 enum pipe pipe = crtc->pipe; in bdw_enable_vblank() local
1756 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_enable_vblank()
1773 enum pipe pipe = crtc->pipe; in bdw_disable_vblank() local
1780 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_disable_vblank()
1787 static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe) in vlv_dpinvgtt_pipe_fault_mask() argument
1789 switch (pipe) { in vlv_dpinvgtt_pipe_fault_mask()
1852 enum pipe pipe; in vlv_page_table_error_irq_handler() local
1854 for_each_pipe(display, pipe) { in vlv_page_table_error_irq_handler()
1857 fault_errors = dpinvgtt & vlv_dpinvgtt_pipe_fault_mask(pipe); in vlv_page_table_error_irq_handler()
1860 pipe, fault_errors); in vlv_page_table_error_irq_handler()
1945 enum pipe pipe; in vlv_display_irq_postinstall() local
1965 for_each_pipe(dev_priv, pipe) in vlv_display_irq_postinstall()
1966 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in vlv_display_irq_postinstall()
1989 enum pipe pipe; in gen8_display_irq_reset() local
1997 for_each_pipe(dev_priv, pipe) in gen8_display_irq_reset()
1999 POWER_DOMAIN_PIPE(pipe))) in gen8_display_irq_reset()
2000 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen8_display_irq_reset()
2009 enum pipe pipe; in gen11_display_irq_reset() local
2040 for_each_pipe(dev_priv, pipe) in gen11_display_irq_reset()
2042 POWER_DOMAIN_PIPE(pipe))) in gen11_display_irq_reset()
2043 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen11_display_irq_reset()
2063 enum pipe pipe; in gen8_irq_power_well_post_enable() local
2072 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
2073 intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), in gen8_irq_power_well_post_enable()
2074 dev_priv->display.irq.de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
2075 ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
2084 enum pipe pipe; in gen8_irq_power_well_pre_disable() local
2093 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
2094 intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen8_irq_power_well_pre_disable()
2216 enum pipe pipe; in gen8_de_irq_postinstall() local
2279 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_postinstall()
2280 dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
2283 POWER_DOMAIN_PIPE(pipe))) in gen8_de_irq_postinstall()
2284 intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), in gen8_de_irq_postinstall()
2285 dev_priv->display.irq.de_irq_mask[pipe], in gen8_de_irq_postinstall()