Lines Matching +full:1 +full:- +full:bit
1 // SPDX-License-Identifier: MIT
24 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info");
43 .platforms._platform##_##_subplatform = 1, \
51 .platforms._platform##_##_subplatform = 1
62 .platforms._platform = 1, \
70 .platforms._platform = 1
89 /* ICL DSI 0 and 1 */
229 .has_overlay = 1, \
230 .cursor_needs_physical = 1, \
231 .overlay_needs_physical = 1, \
232 .has_gmch = 1, \
238 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
240 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
243 .has_overlay = 1, \
244 .overlay_needs_physical = 1, \
245 .has_gmch = 1, \
251 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
252 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
260 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
269 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
279 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
280 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
289 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
290 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
295 .has_gmch = 1, \
296 .has_overlay = 1, \
301 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
303 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
304 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
311 .cursor_needs_physical = 1,
312 .overlay_needs_physical = 1,
322 .cursor_needs_physical = 1,
323 .overlay_needs_physical = 1,
324 .supports_tv = 1,
326 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
335 .has_hotplug = 1,
336 .cursor_needs_physical = 1,
337 .overlay_needs_physical = 1,
347 .has_hotplug = 1,
348 .cursor_needs_physical = 1,
349 .overlay_needs_physical = 1,
350 .supports_tv = 1,
352 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
361 .has_hotplug = 1,
368 .has_hotplug = 1,
383 .has_hotplug = 1, \
384 .has_gmch = 1, \
390 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
392 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
398 .has_overlay = 1,
400 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
409 .has_overlay = 1,
410 .supports_tv = 1,
412 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
413 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
423 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
433 .supports_tv = 1,
435 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
436 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
441 .has_hotplug = 1, \
447 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
449 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
450 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDV…
465 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
470 .has_hotplug = 1,
476 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
478 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
479 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
480 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
495 .has_hotplug = 1,
501 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
503 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
504 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
505 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
522 .has_gmch = 1,
523 .has_hotplug = 1,
530 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
532 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
533 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
567 .has_ddi = 1,
568 .has_dp_mst = 1,
569 .has_fpga_dbg = 1,
570 .has_hotplug = 1,
571 .has_psr = 1,
572 .has_psr_hw_tracking = 1,
578 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
580 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
581 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
582 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
583 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
620 .has_ddi = 1,
621 .has_dp_mst = 1,
622 .has_fpga_dbg = 1,
623 .has_hotplug = 1,
624 .has_psr = 1,
625 .has_psr_hw_tracking = 1,
631 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
633 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
634 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
635 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
636 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
643 .has_hotplug = 1,
644 .has_gmch = 1,
651 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
653 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
654 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
659 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */
660 .dbuf.slice_mask = BIT(DBUF_S1),
661 .has_ddi = 1,
662 .has_dp_mst = 1,
663 .has_fpga_dbg = 1,
664 .has_hotplug = 1,
665 .has_ipc = 1,
666 .has_psr = 1,
667 .has_psr_hw_tracking = 1,
673 .__runtime_defaults.has_dmc = 1,
674 .__runtime_defaults.has_hdcp = 1,
675 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
677 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
678 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
679 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
680 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
735 [1] = STEP_B0,
810 .dbuf.slice_mask = BIT(DBUF_S1), \
811 .has_dp_mst = 1, \
812 .has_ddi = 1, \
813 .has_fpga_dbg = 1, \
814 .has_hotplug = 1, \
815 .has_ipc = 1, \
816 .has_psr = 1, \
817 .has_psr_hw_tracking = 1, \
822 .__runtime_defaults.has_dmc = 1, \
823 .__runtime_defaults.has_hdcp = 1, \
824 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
825 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
827 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
828 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
829 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
830 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
843 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
858 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
867 .abox_mask = BIT(0), \
869 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
870 .has_ddi = 1, \
871 .has_dp_mst = 1, \
872 .has_fpga_dbg = 1, \
873 .has_hotplug = 1, \
874 .has_ipc = 1, \
875 .has_psr = 1, \
876 .has_psr_hw_tracking = 1, \
897 .__runtime_defaults.has_dmc = 1, \
898 .__runtime_defaults.has_dsc = 1, \
899 .__runtime_defaults.has_hdcp = 1, \
900 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
902 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
903 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
904 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
905 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
928 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
936 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
941 [1] = STEP_B0,
957 .abox_mask = GENMASK(2, 1), \
959 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
960 .has_ddi = 1, \
961 .has_dp_mst = 1, \
962 .has_dsb = 1, \
963 .has_fpga_dbg = 1, \
964 .has_hotplug = 1, \
965 .has_ipc = 1, \
966 .has_psr = 1, \
967 .has_psr_hw_tracking = 1, \
988 .__runtime_defaults.has_dmc = 1, \
989 .__runtime_defaults.has_dsc = 1, \
990 .__runtime_defaults.has_hdcp = 1, \
992 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
994 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
995 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
996 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
997 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
1006 [1] = STEP_D0,
1011 [1] = STEP_C0,
1033 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1034 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
1041 [1] = STEP_B0,
1050 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1051 BIT(PORT_TC1) | BIT(PORT_TC2),
1058 [1] = STEP_B0,
1066 .abox_mask = BIT(0),
1067 .has_hti = 1,
1070 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
1072 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
1073 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1074 BIT(PORT_TC1) | BIT(PORT_TC2),
1109 .has_hti = 1,
1112 .__runtime_defaults.port_mask = BIT(PORT_A) |
1113 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1119 .abox_mask = GENMASK(1, 0), \
1126 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1127 BIT(DBUF_S4), \
1128 .has_ddi = 1, \
1129 .has_dp_mst = 1, \
1130 .has_dsb = 1, \
1131 .has_fpga_dbg = 1, \
1132 .has_hotplug = 1, \
1133 .has_ipc = 1, \
1134 .has_psr = 1, \
1154 .__runtime_defaults.has_dmc = 1, \
1155 .__runtime_defaults.has_dsc = 1, \
1156 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
1157 .__runtime_defaults.has_hdcp = 1, \
1159 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
1163 .has_cdclk_crawl = 1,
1167 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1168 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
1169 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
1170 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1171 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1230 .has_cdclk_squash = 1,
1233 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1234 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1235 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
1236 BIT(PORT_TC1),
1297 .abox_mask = GENMASK(1, 0), \
1304 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1305 BIT(DBUF_S4), \
1306 .has_cdclk_crawl = 1, \
1307 .has_cdclk_squash = 1, \
1308 .has_ddi = 1, \
1309 .has_dp_mst = 1, \
1310 .has_dsb = 1, \
1311 .has_fpga_dbg = 1, \
1312 .has_hotplug = 1, \
1313 .has_ipc = 1, \
1314 .has_psr = 1, \
1330 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
1331 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
1332 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \
1333 .__runtime_defaults.has_dmc = 1, \
1334 .__runtime_defaults.has_dsc = 1, \
1335 .__runtime_defaults.has_hdcp = 1, \
1337 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
1338 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
1339 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
1349 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
1350 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
1356 .__runtime_defaults.port_mask = BIT(PORT_A) |
1357 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1477 { 14, 1, &xe2_hpd_display },
1485 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in probe_gmdid_display()
1493 drm_err(display->drm, in probe_gmdid_display()
1502 drm_dbg_kms(display->drm, "Device doesn't have display\n"); in probe_gmdid_display()
1518 drm_err(display->drm, in probe_gmdid_display()
1529 if (intel_display_ids[i].devid == pdev->device) in find_platform_desc()
1542 for (sp = desc->subplatforms; sp && sp->pciidlist; sp++) in find_subplatform_desc()
1543 for (id = sp->pciidlist; *id; id++) in find_subplatform_desc()
1544 if (*id == pdev->device) in find_subplatform_desc()
1554 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in get_pre_gmdid_step()
1555 const enum intel_step *map = main->map; in get_pre_gmdid_step()
1556 int size = main->size; in get_pre_gmdid_step()
1557 int revision = pdev->revision; in get_pre_gmdid_step()
1561 if (sub && sub->map && sub->size) { in get_pre_gmdid_step()
1562 map = sub->map; in get_pre_gmdid_step()
1563 size = sub->size; in get_pre_gmdid_step()
1573 drm_warn(display->drm, "Unknown revision 0x%02x\n", revision); in get_pre_gmdid_step()
1587 drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n", in get_pre_gmdid_step()
1591 drm_dbg_kms(display->drm, "Using future display stepping\n"); in get_pre_gmdid_step()
1596 drm_WARN_ON(display->drm, step == STEP_NONE); in get_pre_gmdid_step()
1604 return sizeof(((struct intel_display_platforms *)0)->bitmap) * BITS_PER_BYTE; in display_platforms_num_bits()
1610 return bitmap_weight(p->bitmap, display_platforms_num_bits()); in display_platforms_weight()
1617 bitmap_or(dst->bitmap, dst->bitmap, src->bitmap, display_platforms_num_bits()); in display_platforms_or()
1630 display->drm = pci_get_drvdata(pdev); in intel_display_device_probe()
1632 intel_display_params_copy(&display->params); in intel_display_device_probe()
1635 drm_dbg_kms(display->drm, "Device doesn't have display\n"); in intel_display_device_probe()
1641 drm_dbg_kms(display->drm, in intel_display_device_probe()
1643 pdev->device); in intel_display_device_probe()
1647 info = desc->info; in intel_display_device_probe()
1656 &DISPLAY_INFO(display)->__runtime_defaults, in intel_display_device_probe()
1659 drm_WARN_ON(display->drm, !desc->name || in intel_display_device_probe()
1660 !display_platforms_weight(&desc->platforms)); in intel_display_device_probe()
1662 display->platform = desc->platforms; in intel_display_device_probe()
1666 drm_WARN_ON(display->drm, !subdesc->name || in intel_display_device_probe()
1667 !display_platforms_weight(&subdesc->platforms)); in intel_display_device_probe()
1669 display_platforms_or(&display->platform, &subdesc->platforms); in intel_display_device_probe()
1672 drm_WARN_ON(display->drm, in intel_display_device_probe()
1673 display_platforms_weight(&display->platform) != in intel_display_device_probe()
1674 display_platforms_weight(&desc->platforms) + in intel_display_device_probe()
1675 display_platforms_weight(&subdesc->platforms)); in intel_display_device_probe()
1679 DISPLAY_RUNTIME_INFO(display)->ip = ip_ver; in intel_display_device_probe()
1682 drm_dbg_kms(display->drm, "Using future display stepping\n"); in intel_display_device_probe()
1686 step = get_pre_gmdid_step(display, &desc->step_info, in intel_display_device_probe()
1687 subdesc ? &subdesc->step_info : NULL); in intel_display_device_probe()
1690 DISPLAY_RUNTIME_INFO(display)->step = step; in intel_display_device_probe()
1692 drm_info(display->drm, "Found %s%s%s (device ID %04x) %s display version %u.%02u stepping %s\n", in intel_display_device_probe()
1693 desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", in intel_display_device_probe()
1694 pdev->device, display->platform.dgfx ? "discrete" : "integrated", in intel_display_device_probe()
1695 DISPLAY_RUNTIME_INFO(display)->ip.ver, in intel_display_device_probe()
1696 DISPLAY_RUNTIME_INFO(display)->ip.rel, in intel_display_device_probe()
1709 intel_display_params_free(&display->params); in intel_display_device_remove()
1714 struct drm_i915_private *i915 = to_i915(display->drm); in __intel_display_device_info_runtime_init()
1718 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); in __intel_display_device_info_runtime_init()
1719 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); in __intel_display_device_info_runtime_init()
1720 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); in __intel_display_device_info_runtime_init()
1723 if (display->platform.haswell_ult || display->platform.broadwell_ult) in __intel_display_device_info_runtime_init()
1724 display_runtime->port_mask &= ~BIT(PORT_D); in __intel_display_device_info_runtime_init()
1726 if (display->platform.icelake_port_f) in __intel_display_device_info_runtime_init()
1727 display_runtime->port_mask |= BIT(PORT_F); in __intel_display_device_info_runtime_init()
1729 /* Wa_14011765242: adl-s A0,A1 */ in __intel_display_device_info_runtime_init()
1730 if (display->platform.alderlake_s && IS_DISPLAY_STEP(display, STEP_A0, STEP_A2)) in __intel_display_device_info_runtime_init()
1732 display_runtime->num_scalers[pipe] = 0; in __intel_display_device_info_runtime_init()
1735 display_runtime->num_scalers[pipe] = 2; in __intel_display_device_info_runtime_init()
1737 display_runtime->num_scalers[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
1738 display_runtime->num_scalers[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
1739 display_runtime->num_scalers[PIPE_C] = 1; in __intel_display_device_info_runtime_init()
1744 display_runtime->num_sprites[pipe] = 4; in __intel_display_device_info_runtime_init()
1747 display_runtime->num_sprites[pipe] = 6; in __intel_display_device_info_runtime_init()
1750 display_runtime->num_sprites[pipe] = 3; in __intel_display_device_info_runtime_init()
1751 else if (display->platform.broxton) { in __intel_display_device_info_runtime_init()
1761 display_runtime->num_sprites[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
1762 display_runtime->num_sprites[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
1763 display_runtime->num_sprites[PIPE_C] = 1; in __intel_display_device_info_runtime_init()
1764 } else if (display->platform.valleyview || display->platform.cherryview) { in __intel_display_device_info_runtime_init()
1766 display_runtime->num_sprites[pipe] = 2; in __intel_display_device_info_runtime_init()
1767 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { in __intel_display_device_info_runtime_init()
1769 display_runtime->num_sprites[pipe] = 1; in __intel_display_device_info_runtime_init()
1772 if ((display->platform.dgfx || DISPLAY_VER(display) >= 14) && in __intel_display_device_info_runtime_init()
1774 drm_info(display->drm, "Display not present, disabling\n"); in __intel_display_device_info_runtime_init()
1783 * SFUSE_STRAP is supposed to have a bit signalling the display in __intel_display_device_info_runtime_init()
1795 drm_info(display->drm, in __intel_display_device_info_runtime_init()
1799 drm_info(display->drm, "PipeC fused off\n"); in __intel_display_device_info_runtime_init()
1800 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
1801 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); in __intel_display_device_info_runtime_init()
1807 display_runtime->pipe_mask &= ~BIT(PIPE_A); in __intel_display_device_info_runtime_init()
1808 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); in __intel_display_device_info_runtime_init()
1809 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); in __intel_display_device_info_runtime_init()
1812 display_runtime->pipe_mask &= ~BIT(PIPE_B); in __intel_display_device_info_runtime_init()
1813 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); in __intel_display_device_info_runtime_init()
1814 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B); in __intel_display_device_info_runtime_init()
1817 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
1818 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); in __intel_display_device_info_runtime_init()
1819 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C); in __intel_display_device_info_runtime_init()
1824 display_runtime->pipe_mask &= ~BIT(PIPE_D); in __intel_display_device_info_runtime_init()
1825 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); in __intel_display_device_info_runtime_init()
1826 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D); in __intel_display_device_info_runtime_init()
1829 if (!display_runtime->pipe_mask) in __intel_display_device_info_runtime_init()
1833 display_runtime->has_hdcp = 0; in __intel_display_device_info_runtime_init()
1835 if (display->platform.dg2 || DISPLAY_VER(display) < 13) { in __intel_display_device_info_runtime_init()
1837 display_runtime->fbc_mask = 0; in __intel_display_device_info_runtime_init()
1841 display_runtime->has_dmc = 0; in __intel_display_device_info_runtime_init()
1845 display_runtime->has_dsc = 0; in __intel_display_device_info_runtime_init()
1849 display_runtime->has_dbuf_overlap_detection = false; in __intel_display_device_info_runtime_init()
1857 display_runtime->has_dsc = 0; in __intel_display_device_info_runtime_init()
1862 if (display_runtime->num_scalers[pipe]) in __intel_display_device_info_runtime_init()
1863 display_runtime->num_scalers[pipe] = 1; in __intel_display_device_info_runtime_init()
1868 display_runtime->edp_typec_support = in __intel_display_device_info_runtime_init()
1871 display_runtime->rawclk_freq = intel_read_rawclk(display); in __intel_display_device_info_runtime_init()
1872 drm_dbg_kms(display->drm, "rawclk rate: %d kHz\n", in __intel_display_device_info_runtime_init()
1873 display_runtime->rawclk_freq); in __intel_display_device_info_runtime_init()
1888 display->drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); in intel_display_device_info_runtime_init()
1889 display->info.__device_info = &no_display; in intel_display_device_info_runtime_init()
1892 /* Disable nuclear pageflip by default on pre-g4x */ in intel_display_device_info_runtime_init()
1893 if (!display->params.nuclear_pageflip && in intel_display_device_info_runtime_init()
1894 DISPLAY_VER(display) < 5 && !display->platform.g4x) in intel_display_device_info_runtime_init()
1895 display->drm->driver_features &= ~DRIVER_ATOMIC; in intel_display_device_info_runtime_init()
1902 if (runtime->ip.rel) in intel_display_device_info_print()
1904 runtime->ip.ver, in intel_display_device_info_print()
1905 runtime->ip.rel); in intel_display_device_info_print()
1908 runtime->ip.ver); in intel_display_device_info_print()
1910 drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step)); in intel_display_device_info_print()
1912 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) in intel_display_device_info_print()
1916 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); in intel_display_device_info_print()
1917 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); in intel_display_device_info_print()
1918 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); in intel_display_device_info_print()
1920 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); in intel_display_device_info_print()
1935 drm_WARN_ON(display->drm, !HAS_DISPLAY(display)); in intel_display_device_enabled()
1937 return !display->params.disable_display && in intel_display_device_enabled()