2  * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
161 	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=  in vlv_get_cck_clock()
175 	if (dev_priv->hpll_freq == 0)  in vlv_get_cck_clock_hpll()
176 		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);  in vlv_get_cck_clock_hpll()
178 	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);  in vlv_get_cck_clock_hpll()
187 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_update_czclk()
189 	if (!display->platform.valleyview && !display->platform.cherryview)  in intel_update_czclk()
192 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",  in intel_update_czclk()
195 	drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq);  in intel_update_czclk()
200 	return (crtc_state->active_planes &  in is_hdr_mode()
236 	return crtc_state->master_transcoder != INVALID_TRANSCODER;  in is_trans_port_sync_slave()
242 	return crtc_state->sync_mode_slaves_mask != 0;  in is_trans_port_sync_master()
254 	return ffs(crtc_state->joiner_pipes) - 1;  in joiner_primary_pipe()
263 	return hweight8(crtc_state->joiner_pipes) >= 2;  in is_bigjoiner()
271 	return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));  in bigjoiner_primary_pipes()
279 	return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));  in bigjoiner_secondary_pipes()
284 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_bigjoiner_primary()
289 	return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);  in intel_crtc_is_bigjoiner_primary()
294 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_bigjoiner_secondary()
299 	return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);  in intel_crtc_is_bigjoiner_secondary()
304 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in _intel_modeset_primary_pipes()
307 		return BIT(crtc->pipe);  in _intel_modeset_primary_pipes()
327 	return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));  in ultrajoiner_primary_pipes()
332 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_ultrajoiner_primary()
335 	       BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);  in intel_crtc_is_ultrajoiner_primary()
348 	return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));  in ultrajoiner_enable_pipes()
353 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_ultrajoiner_enable_needed()
356 	       BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);  in intel_crtc_ultrajoiner_enable_needed()
361 	if (crtc_state->joiner_pipes)  in intel_crtc_joiner_secondary_pipes()
362 		return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));  in intel_crtc_joiner_secondary_pipes()
369 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_joiner_secondary()
371 	return crtc_state->joiner_pipes &&  in intel_crtc_is_joiner_secondary()
372 		crtc->pipe != joiner_primary_pipe(crtc_state);  in intel_crtc_is_joiner_secondary()
377 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_joiner_primary()
379 	return crtc_state->joiner_pipes &&  in intel_crtc_is_joiner_primary()
380 		crtc->pipe == joiner_primary_pipe(crtc_state);  in intel_crtc_is_joiner_primary()
390 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_joined_pipe_mask()
392 	return BIT(crtc->pipe) | crtc_state->joiner_pipes;  in intel_crtc_joined_pipe_mask()
402 		return to_intel_crtc(crtc_state->uapi.crtc);  in intel_primary_crtc()
409 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_wait_for_pipe_off()
412 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_wait_for_pipe_off()
417 			drm_WARN(display->drm, 1, "pipe_off wait timed out\n");  in intel_wait_for_pipe_off()
431 	if (display->platform.i830)  in assert_transcoder()
454 	struct intel_display *display = to_intel_display(plane->base.dev);  in assert_plane()
458 	cur_state = plane->get_hw_state(plane, &pipe);  in assert_plane()
462 				 plane->base.name, str_on_off(state),  in assert_plane()
474 	for_each_intel_plane_on_crtc(display->drm, crtc, plane)  in assert_planes_disabled()
481 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_enable_transcoder()
482 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in intel_enable_transcoder()
483 	enum pipe pipe = crtc->pipe;  in intel_enable_transcoder()
486 	drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));  in intel_enable_transcoder()
501 		if (new_crtc_state->has_pch_encoder) {  in intel_enable_transcoder()
511 	/* Wa_22012358565:adl-p */  in intel_enable_transcoder()
530 		drm_WARN_ON(display->drm, !display->platform.i830);  in intel_enable_transcoder()
536 	    new_crtc_state->dsc.compression_enable) {  in intel_enable_transcoder()
560 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_disable_transcoder()
561 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_disable_transcoder()
562 	enum pipe pipe = crtc->pipe;  in intel_disable_transcoder()
565 	drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));  in intel_disable_transcoder()
581 	if (old_crtc_state->double_wide)  in intel_disable_transcoder()
585 	if (!display->platform.i830)  in intel_disable_transcoder()
590 	    old_crtc_state->dsc.compression_enable)  in intel_disable_transcoder()
622 	plane = to_intel_plane(crtc->base.primary);  in intel_plane_fb_max_stride()
624 	return plane->max_stride(plane, pixel_format, modifier,  in intel_plane_fb_max_stride()
632 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_set_plane_visible()
634 	plane_state->uapi.visible = visible;  in intel_set_plane_visible()
637 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);  in intel_set_plane_visible()
639 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);  in intel_set_plane_visible()
652 	crtc_state->enabled_planes = 0;  in intel_plane_fixup_bitmasks()
653 	crtc_state->active_planes = 0;  in intel_plane_fixup_bitmasks()
655 	drm_for_each_plane_mask(plane, display->drm,  in intel_plane_fixup_bitmasks()
656 				crtc_state->uapi.plane_mask) {  in intel_plane_fixup_bitmasks()
657 		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
658 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
666 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_plane_disable_noatomic()
668 		to_intel_crtc_state(crtc->base.state);  in intel_plane_disable_noatomic()
670 		to_intel_plane_state(plane->base.state);  in intel_plane_disable_noatomic()
672 	drm_dbg_kms(display->drm,  in intel_plane_disable_noatomic()
674 		    plane->base.base.id, plane->base.name,  in intel_plane_disable_noatomic()
675 		    crtc->base.base.id, crtc->base.name);  in intel_plane_disable_noatomic()
683 	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&  in intel_plane_disable_noatomic()
685 		crtc_state->ips_enabled = false;  in intel_plane_disable_noatomic()
691 	 * are blocked if the memory self-refresh mode is active at that  in intel_plane_disable_noatomic()
693 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_plane_disable_noatomic()
696 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_plane_disable_noatomic()
706 	if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)  in intel_plane_disable_noatomic()
707 		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);  in intel_plane_disable_noatomic()
719 					  plane_state->view.color_plane[0].offset, 0);  in intel_plane_fence_y_offset()
727 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in icl_set_pipe_chicken()
728 	enum pipe pipe = crtc->pipe;  in icl_set_pipe_chicken()
736 	 * and rounding for per-pixel values 00 and 0xff  in icl_set_pipe_chicken()
751 	if (display->platform.dg2)  in icl_set_pipe_chicken()
757 	if (display->platform.dg2)  in icl_set_pipe_chicken()
768 	drm_for_each_crtc(crtc, display->drm) {  in intel_has_pending_fb_unpin()
770 		spin_lock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
771 		commit = list_first_entry_or_null(&crtc->commit_list,  in intel_has_pending_fb_unpin()
774 			try_wait_for_completion(&commit->cleanup_done) : true;  in intel_has_pending_fb_unpin()
775 		spin_unlock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
805 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_get_crtc_new_encoder()
806 		if (connector_state->crtc != &primary_crtc->base)  in intel_get_crtc_new_encoder()
809 		encoder = to_intel_encoder(connector_state->best_encoder);  in intel_get_crtc_new_encoder()
813 	drm_WARN(state->base.dev, num_encoders != 1,  in intel_get_crtc_new_encoder()
815 		 num_encoders, pipe_name(primary_crtc->pipe));  in intel_get_crtc_new_encoder()
822 	if (crtc->overlay)  in intel_crtc_dpms_overlay_disable()
823 		(void) intel_overlay_switch_off(crtc->overlay);  in intel_crtc_dpms_overlay_disable()
834 	if (!crtc_state->nv12_planes)  in needs_nv12_wa()
849 	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)  in needs_scalerclk_wa()
861 	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&  in needs_cursorclk_wa()
890 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in needs_async_flip_vtd_wa()
892 	return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&  in needs_async_flip_vtd_wa()
893 		(DISPLAY_VER(display) == 9 || display->platform.broadwell ||  in needs_async_flip_vtd_wa()
894 		 display->platform.haswell);  in needs_async_flip_vtd_wa()
906 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_audio_enable()
908 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_audio_enable()
910 		if (conn_state->crtc != &crtc->base)  in intel_encoders_audio_enable()
913 		if (encoder->audio_enable)  in intel_encoders_audio_enable()
914 			encoder->audio_enable(encoder, crtc_state, conn_state);  in intel_encoders_audio_enable()
927 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_audio_disable()
929 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_audio_disable()
931 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_audio_disable()
934 		if (encoder->audio_disable)  in intel_encoders_audio_disable()
935 			encoder->audio_disable(encoder, old_crtc_state, old_conn_state);  in intel_encoders_audio_disable()
940 	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
941 	 (new_crtc_state)->feature)
943 	((old_crtc_state)->feature && \
944 	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
949 	if (!new_crtc_state->hw.active)  in planes_enabling()
958 	if (!old_crtc_state->hw.active)  in planes_disabling()
967 	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||  in vrr_params_changed()
968 		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||  in vrr_params_changed()
969 		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||  in vrr_params_changed()
970 		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||  in vrr_params_changed()
971 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||  in vrr_params_changed()
972 		old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||  in vrr_params_changed()
973 		old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;  in vrr_params_changed()
979 	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||  in cmrr_params_changed()
980 		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;  in cmrr_params_changed()
991 	if (!new_crtc_state->hw.active)  in intel_crtc_vrr_enabling()
995 		(new_crtc_state->vrr.enable &&  in intel_crtc_vrr_enabling()
996 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in intel_crtc_vrr_enabling()
1008 	if (!old_crtc_state->hw.active)  in intel_crtc_vrr_disabling()
1012 		(old_crtc_state->vrr.enable &&  in intel_crtc_vrr_disabling()
1013 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in intel_crtc_vrr_disabling()
1020 	if (!new_crtc_state->hw.active)  in audio_enabling()
1024 		(new_crtc_state->has_audio &&  in audio_enabling()
1025 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_enabling()
1031 	if (!old_crtc_state->hw.active)  in audio_disabling()
1035 		(old_crtc_state->has_audio &&  in audio_disabling()
1036 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_disabling()
1046 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_post_plane_update()
1051 	enum pipe pipe = crtc->pipe;  in intel_post_plane_update()
1055 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);  in intel_post_plane_update()
1057 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)  in intel_post_plane_update()
1106 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_enable_flip_done()
1112 		if (plane->pipe == crtc->pipe &&  in intel_crtc_enable_flip_done()
1113 		    update_planes & BIT(plane->id))  in intel_crtc_enable_flip_done()
1114 			plane->enable_flip_done(plane);  in intel_crtc_enable_flip_done()
1123 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_disable_flip_done()
1129 		if (plane->pipe == crtc->pipe &&  in intel_crtc_disable_flip_done()
1130 		    update_planes & BIT(plane->id))  in intel_crtc_disable_flip_done()
1131 			plane->disable_flip_done(plane);  in intel_crtc_disable_flip_done()
1142 	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &  in intel_crtc_async_flip_disable_wa()
1143 				       ~new_crtc_state->async_flip_planes;  in intel_crtc_async_flip_disable_wa()
1150 		if (plane->need_async_flip_toggle_wa &&  in intel_crtc_async_flip_disable_wa()
1151 		    plane->pipe == crtc->pipe &&  in intel_crtc_async_flip_disable_wa()
1152 		    disable_async_flip_planes & BIT(plane->id)) {  in intel_crtc_async_flip_disable_wa()
1171 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_pre_plane_update()
1176 	enum pipe pipe = crtc->pipe;  in intel_pre_plane_update()
1217 	 * are blocked if the memory self-refresh mode is active at that  in intel_pre_plane_update()
1219 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_pre_plane_update()
1222 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_pre_plane_update()
1224 	if (HAS_GMCH(display) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
1225 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))  in intel_pre_plane_update()
1230 	 * one frame before enabling scaling.  LP watermarks can be re-enabled  in intel_pre_plane_update()
1235 	if (!HAS_GMCH(display) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
1236 	    new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))  in intel_pre_plane_update()
1241 	 * pre-vblank watermark programming here.  in intel_pre_plane_update()
1246 		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these  in intel_pre_plane_update()
1247 		 * will be the intermediate values that are safe for both pre- and  in intel_pre_plane_update()
1248 		 * post- vblank; when vblank happens, the 'active' values will be set  in intel_pre_plane_update()
1259 			if (new_crtc_state->update_wm_pre)  in intel_pre_plane_update()
1278 	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)  in intel_pre_plane_update()
1285 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_disable_planes()
1288 	unsigned int update_mask = new_crtc_state->update_planes;  in intel_crtc_disable_planes()
1297 		if (crtc->pipe != plane->pipe ||  in intel_crtc_disable_planes()
1298 		    !(update_mask & BIT(plane->id)))  in intel_crtc_disable_planes()
1303 		if (old_plane_state->uapi.visible)  in intel_crtc_disable_planes()
1304 			fb_bits |= plane->frontbuffer_bit;  in intel_crtc_disable_planes()
1318 	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.  in intel_encoders_update_prepare()
1319 	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.  in intel_encoders_update_prepare()
1321 	if (display->dpll.mgr) {  in intel_encoders_update_prepare()
1326 			new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;  in intel_encoders_update_prepare()
1327 			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;  in intel_encoders_update_prepare()
1341 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_pll_enable()
1343 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_pll_enable()
1345 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_pll_enable()
1348 		if (encoder->pre_pll_enable)  in intel_encoders_pre_pll_enable()
1349 			encoder->pre_pll_enable(state, encoder,  in intel_encoders_pre_pll_enable()
1363 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_enable()
1365 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_enable()
1367 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_enable()
1370 		if (encoder->pre_enable)  in intel_encoders_pre_enable()
1371 			encoder->pre_enable(state, encoder,  in intel_encoders_pre_enable()
1385 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_enable()
1387 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_enable()
1389 		if (conn_state->crtc != &crtc->base)  in intel_encoders_enable()
1392 		if (encoder->enable)  in intel_encoders_enable()
1393 			encoder->enable(state, encoder,  in intel_encoders_enable()
1408 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_disable()
1410 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_disable()
1412 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_disable()
1416 		if (encoder->disable)  in intel_encoders_disable()
1417 			encoder->disable(state, encoder,  in intel_encoders_disable()
1431 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_disable()
1433 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_disable()
1435 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_disable()
1438 		if (encoder->post_disable)  in intel_encoders_post_disable()
1439 			encoder->post_disable(state, encoder,  in intel_encoders_post_disable()
1453 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_pll_disable()
1455 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_pll_disable()
1457 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_pll_disable()
1460 		if (encoder->post_pll_disable)  in intel_encoders_post_pll_disable()
1461 			encoder->post_pll_disable(state, encoder,  in intel_encoders_post_pll_disable()
1475 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_update_pipe()
1477 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_update_pipe()
1479 		if (conn_state->crtc != &crtc->base)  in intel_encoders_update_pipe()
1482 		if (encoder->update_pipe)  in intel_encoders_update_pipe()
1483 			encoder->update_pipe(state, encoder,  in intel_encoders_update_pipe()
1490 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_configure_cpu_transcoder()
1491 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_configure_cpu_transcoder()
1493 	if (crtc_state->has_pch_encoder) {  in ilk_configure_cpu_transcoder()
1495 					       &crtc_state->fdi_m_n);  in ilk_configure_cpu_transcoder()
1498 					       &crtc_state->dp_m_n);  in ilk_configure_cpu_transcoder()
1500 					       &crtc_state->dp_m2_n2);  in ilk_configure_cpu_transcoder()
1514 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_enable()
1515 	enum pipe pipe = crtc->pipe;  in ilk_crtc_enable()
1517 	if (drm_WARN_ON(display->drm, crtc->active))  in ilk_crtc_enable()
1537 	crtc->active = true;  in ilk_crtc_enable()
1541 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1559 	if (new_crtc_state->has_pch_encoder)  in ilk_crtc_enable()
1575 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1588 	return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;  in glk_need_scaler_clock_gating_wa()
1596 	intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),  in glk_pipe_scaler_clock_gating_wa()
1603 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_linetime_wm()
1605 	intel_de_write(display, WM_LINETIME(crtc->pipe),  in hsw_set_linetime_wm()
1606 		       HSW_LINETIME(crtc_state->linetime) |  in hsw_set_linetime_wm()
1607 		       HSW_IPS_LINETIME(crtc_state->ips_linetime));  in hsw_set_linetime_wm()
1614 	intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),  in hsw_set_frame_start_delay()
1616 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));  in hsw_set_frame_start_delay()
1622 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_configure_cpu_transcoder()
1623 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_configure_cpu_transcoder()
1625 	if (crtc_state->has_pch_encoder) {  in hsw_configure_cpu_transcoder()
1627 					       &crtc_state->fdi_m_n);  in hsw_configure_cpu_transcoder()
1630 					       &crtc_state->dp_m_n);  in hsw_configure_cpu_transcoder()
1632 					       &crtc_state->dp_m2_n2);  in hsw_configure_cpu_transcoder()
1641 			       crtc_state->pixel_multiplier - 1);  in hsw_configure_cpu_transcoder()
1654 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in hsw_crtc_enable()
1658 	if (drm_WARN_ON(display->drm, crtc->active))  in hsw_crtc_enable()
1661 		intel_dmc_enable_pipe(display, pipe_crtc->pipe);  in hsw_crtc_enable()
1669 		if (pipe_crtc_state->shared_dpll)  in hsw_crtc_enable()
1686 		if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)  in hsw_crtc_enable()
1697 		pipe_crtc->active = true;  in hsw_crtc_enable()
1737 		hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;  in hsw_crtc_enable()
1738 		if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {  in hsw_crtc_enable()
1754 	enum pipe pipe = crtc->pipe;  in ilk_crtc_disable()
1772 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1777 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1797 	 * Need care with mst->ddi interactions.  in hsw_crtc_disable()
1812 		intel_dmc_disable_pipe(display, pipe_crtc->pipe);  in hsw_crtc_disable()
1820 	else if (display->platform.alderlake_s)  in intel_phy_is_combo()
1822 	else if (display->platform.dg1 || display->platform.rocketlake)  in intel_phy_is_combo()
1824 	else if (display->platform.jasperlake || display->platform.elkhartlake)  in intel_phy_is_combo()
1826 	else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))  in intel_phy_is_combo()
1842 	 * subsystem Legacy or non-legacy, and only support native DP/HDMI  in intel_phy_is_tc()
1844 	if (display->platform.dgfx)  in intel_phy_is_tc()
1849 	else if (display->platform.tigerlake)  in intel_phy_is_tc()
1851 	else if (display->platform.icelake)  in intel_phy_is_tc()
1864 	return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;  in intel_phy_is_snps()
1871 		return PHY_D + port - PORT_D_XELPD;  in intel_port_to_phy()
1873 		return PHY_F + port - PORT_TC1;  in intel_port_to_phy()
1874 	else if (display->platform.alderlake_s && port >= PORT_TC1)  in intel_port_to_phy()
1875 		return PHY_B + port - PORT_TC1;  in intel_port_to_phy()
1876 	else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)  in intel_port_to_phy()
1877 		return PHY_C + port - PORT_TC1;  in intel_port_to_phy()
1878 	else if ((display->platform.jasperlake || display->platform.elkhartlake) &&  in intel_port_to_phy()
1882 	return PHY_A + port - PORT_A;  in intel_port_to_phy()
1892 		return TC_PORT_1 + port - PORT_TC1;  in intel_port_to_tc()
1894 		return TC_PORT_1 + port - PORT_C;  in intel_port_to_tc()
1901 	return intel_port_to_phy(display, encoder->port);  in intel_encoder_to_phy()
1929 	return intel_port_to_tc(display, encoder->port);  in intel_encoder_to_tc()
1938 		return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch);  in intel_aux_power_domain()
1940 	return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);  in intel_aux_power_domain()
1947 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in get_crtc_power_domains()
1948 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in get_crtc_power_domains()
1950 	enum pipe pipe = crtc->pipe;  in get_crtc_power_domains()
1952 	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);  in get_crtc_power_domains()
1954 	if (!crtc_state->hw.active)  in get_crtc_power_domains()
1957 	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);  in get_crtc_power_domains()
1958 	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);  in get_crtc_power_domains()
1959 	if (crtc_state->pch_pfit.enabled ||  in get_crtc_power_domains()
1960 	    crtc_state->pch_pfit.force_thru)  in get_crtc_power_domains()
1961 		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);  in get_crtc_power_domains()
1963 	drm_for_each_encoder_mask(encoder, display->drm,  in get_crtc_power_domains()
1964 				  crtc_state->uapi.encoder_mask) {  in get_crtc_power_domains()
1967 		set_bit(intel_encoder->power_domain, mask->bits);  in get_crtc_power_domains()
1970 	if (HAS_DDI(display) && crtc_state->has_audio)  in get_crtc_power_domains()
1971 		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);  in get_crtc_power_domains()
1973 	if (crtc_state->shared_dpll)  in get_crtc_power_domains()
1974 		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);  in get_crtc_power_domains()
1976 	if (crtc_state->dsc.compression_enable)  in get_crtc_power_domains()
1977 		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);  in get_crtc_power_domains()
1984 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_get_crtc_power_domains()
1992 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
1994 	bitmap_andnot(old_domains->bits,  in intel_modeset_get_crtc_power_domains()
1995 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
2001 					       &crtc->enabled_power_domains,  in intel_modeset_get_crtc_power_domains()
2011 					    &crtc->enabled_power_domains,  in intel_modeset_put_crtc_power_domains()
2017 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_configure_cpu_transcoder()
2018 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_configure_cpu_transcoder()
2022 					       &crtc_state->dp_m_n);  in i9xx_configure_cpu_transcoder()
2024 					       &crtc_state->dp_m2_n2);  in i9xx_configure_cpu_transcoder()
2038 	enum pipe pipe = crtc->pipe;  in valleyview_crtc_enable()
2040 	if (drm_WARN_ON(display->drm, crtc->active))  in valleyview_crtc_enable()
2049 	if (display->platform.cherryview && pipe == PIPE_B) {  in valleyview_crtc_enable()
2055 	crtc->active = true;  in valleyview_crtc_enable()
2061 	if (display->platform.cherryview)  in valleyview_crtc_enable()
2086 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_crtc_enable()
2087 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_enable()
2089 	if (drm_WARN_ON(display->drm, crtc->active))  in i9xx_crtc_enable()
2096 	crtc->active = true;  in i9xx_crtc_enable()
2126 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in i9xx_crtc_disable()
2129 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_disable()
2149 		if (display->platform.cherryview)  in i9xx_crtc_disable()
2151 		else if (display->platform.valleyview)  in i9xx_crtc_disable()
2162 	if (!display->funcs.wm->initial_watermarks)  in i9xx_crtc_disable()
2166 	if (display->platform.i830)  in i9xx_crtc_disable()
2184 		(crtc->pipe == PIPE_A || display->platform.i915g);  in intel_crtc_supports_double_wide()
2189 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;  in ilk_pipe_pixel_rate()
2193 	 * We only use IF-ID interlacing. If we ever use  in ilk_pipe_pixel_rate()
2194 	 * PF-ID we'll need to adjust the pixel_rate here.  in ilk_pipe_pixel_rate()
2197 	if (!crtc_state->pch_pfit.enabled)  in ilk_pipe_pixel_rate()
2201 		      drm_rect_width(&crtc_state->pipe_src) << 16,  in ilk_pipe_pixel_rate()
2202 		      drm_rect_height(&crtc_state->pipe_src) << 16);  in ilk_pipe_pixel_rate()
2204 	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,  in ilk_pipe_pixel_rate()
2211 	mode->hdisplay = timings->crtc_hdisplay;  in intel_mode_from_crtc_timings()
2212 	mode->htotal = timings->crtc_htotal;  in intel_mode_from_crtc_timings()
2213 	mode->hsync_start = timings->crtc_hsync_start;  in intel_mode_from_crtc_timings()
2214 	mode->hsync_end = timings->crtc_hsync_end;  in intel_mode_from_crtc_timings()
2216 	mode->vdisplay = timings->crtc_vdisplay;  in intel_mode_from_crtc_timings()
2217 	mode->vtotal = timings->crtc_vtotal;  in intel_mode_from_crtc_timings()
2218 	mode->vsync_start = timings->crtc_vsync_start;  in intel_mode_from_crtc_timings()
2219 	mode->vsync_end = timings->crtc_vsync_end;  in intel_mode_from_crtc_timings()
2221 	mode->flags = timings->flags;  in intel_mode_from_crtc_timings()
2222 	mode->type = DRM_MODE_TYPE_DRIVER;  in intel_mode_from_crtc_timings()
2224 	mode->clock = timings->crtc_clock;  in intel_mode_from_crtc_timings()
2235 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2236 			crtc_state->hw.pipe_mode.crtc_clock;  in intel_crtc_compute_pixel_rate()
2238 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2250 	mode->crtc_clock /= num_pipes;  in intel_joiner_adjust_timings()
2251 	mode->crtc_hdisplay /= num_pipes;  in intel_joiner_adjust_timings()
2252 	mode->crtc_hblank_start /= num_pipes;  in intel_joiner_adjust_timings()
2253 	mode->crtc_hblank_end /= num_pipes;  in intel_joiner_adjust_timings()
2254 	mode->crtc_hsync_start /= num_pipes;  in intel_joiner_adjust_timings()
2255 	mode->crtc_hsync_end /= num_pipes;  in intel_joiner_adjust_timings()
2256 	mode->crtc_htotal /= num_pipes;  in intel_joiner_adjust_timings()
2262 	int overlap = crtc_state->splitter.pixel_overlap;  in intel_splitter_adjust_timings()
2263 	int n = crtc_state->splitter.link_count;  in intel_splitter_adjust_timings()
2265 	if (!crtc_state->splitter.enable)  in intel_splitter_adjust_timings()
2272 	 * h_full = (h_segment - pixel_overlap) * link_count  in intel_splitter_adjust_timings()
2274 	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;  in intel_splitter_adjust_timings()
2275 	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;  in intel_splitter_adjust_timings()
2276 	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;  in intel_splitter_adjust_timings()
2277 	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;  in intel_splitter_adjust_timings()
2278 	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;  in intel_splitter_adjust_timings()
2279 	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;  in intel_splitter_adjust_timings()
2280 	mode->crtc_clock *= n;  in intel_splitter_adjust_timings()
2285 	struct drm_display_mode *mode = &crtc_state->hw.mode;  in intel_crtc_readout_derived_state()
2286 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_readout_derived_state()
2287 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_readout_derived_state()
2295 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_readout_derived_state()
2308 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *  in intel_crtc_readout_derived_state()
2310 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);  in intel_crtc_readout_derived_state()
2312 	/* Derive per-pipe timings in case joiner is used */  in intel_crtc_readout_derived_state()
2322 	encoder->get_config(encoder, crtc_state);  in intel_encoder_get_config()
2335 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_joiner_compute_pipe_src()
2336 	height = drm_rect_height(&crtc_state->pipe_src);  in intel_joiner_compute_pipe_src()
2338 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_joiner_compute_pipe_src()
2345 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_src()
2346 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_compute_pipe_src()
2352 	 * - DVO ganged mode  in intel_crtc_compute_pipe_src()
2353 	 * - LVDS dual channel mode  in intel_crtc_compute_pipe_src()
2354 	 * - Double wide pipe  in intel_crtc_compute_pipe_src()
2356 	if (drm_rect_width(&crtc_state->pipe_src) & 1) {  in intel_crtc_compute_pipe_src()
2357 		if (crtc_state->double_wide) {  in intel_crtc_compute_pipe_src()
2358 			drm_dbg_kms(display->drm,  in intel_crtc_compute_pipe_src()
2360 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2361 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2366 			drm_dbg_kms(display->drm,  in intel_crtc_compute_pipe_src()
2367 				    "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",  in intel_crtc_compute_pipe_src()
2368 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2369 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2379 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_mode()
2380 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_compute_pipe_mode()
2381 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_compute_pipe_mode()
2382 	int clock_limit = display->cdclk.max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2390 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_compute_pipe_mode()
2393 	/* Derive per-pipe timings in case joiner is used */  in intel_crtc_compute_pipe_mode()
2398 		clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;  in intel_crtc_compute_pipe_mode()
2405 		    pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2406 			clock_limit = display->cdclk.max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2407 			crtc_state->double_wide = true;  in intel_crtc_compute_pipe_mode()
2411 	if (pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2412 		drm_dbg_kms(display->drm,  in intel_crtc_compute_pipe_mode()
2414 			    crtc->base.base.id, crtc->base.name,  in intel_crtc_compute_pipe_mode()
2415 			    pipe_mode->crtc_clock, clock_limit,  in intel_crtc_compute_pipe_mode()
2416 			    str_yes_no(crtc_state->double_wide));  in intel_crtc_compute_pipe_mode()
2417 		return -EINVAL;  in intel_crtc_compute_pipe_mode()
2427 	return intel_vrr_possible(crtc_state) && crtc_state->has_psr &&  in intel_crtc_needs_wa_14015401596()
2453 		&crtc_state->hw.adjusted_mode;  in intel_crtc_compute_vblank_delay()
2457 	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;  in intel_crtc_compute_vblank_delay()
2460 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] vblank delay (%d) exceeds max (%d)\n",  in intel_crtc_compute_vblank_delay()
2461 			    crtc->base.base.id, crtc->base.name, vblank_delay, max_vblank_delay);  in intel_crtc_compute_vblank_delay()
2462 		return -EINVAL;  in intel_crtc_compute_vblank_delay()
2465 	adjusted_mode->crtc_vblank_start += vblank_delay;  in intel_crtc_compute_vblank_delay()
2495 	if (crtc_state->has_pch_encoder)  in intel_crtc_compute_config()
2541 	m_n->tu = 64;  in intel_link_compute_m_n()
2542 	compute_m_n(&m_n->data_m, &m_n->data_n,  in intel_link_compute_m_n()
2546 	compute_m_n(&m_n->link_m, &m_n->link_n,  in intel_link_compute_m_n()
2553 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_panel_sanitize_ssc()
2566 		if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {  in intel_panel_sanitize_ssc()
2567 			drm_dbg_kms(display->drm,  in intel_panel_sanitize_ssc()
2570 				    str_enabled_disabled(display->vbt.lvds_use_ssc));  in intel_panel_sanitize_ssc()
2571 			display->vbt.lvds_use_ssc = bios_lvds_use_ssc;  in intel_panel_sanitize_ssc()
2580 	m_n->tu = 1;  in intel_zero_m_n()
2588 	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);  in intel_set_m_n()
2589 	intel_de_write(display, data_n_reg, m_n->data_n);  in intel_set_m_n()
2590 	intel_de_write(display, link_m_reg, m_n->link_m);  in intel_set_m_n()
2595 	intel_de_write(display, link_n_reg, m_n->link_n);  in intel_set_m_n()
2601 	if (display->platform.haswell)  in intel_cpu_transcoder_has_m2_n2()
2604 	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;  in intel_cpu_transcoder_has_m2_n2()
2612 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_set_m1_n1()
2645 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings()
2646 	enum pipe pipe = crtc->pipe;  in intel_set_transcoder_timings()
2647 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings()
2648 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings()
2652 	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));  in intel_set_transcoder_timings()
2656 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings()
2657 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings()
2658 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings()
2659 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings()
2661 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {  in intel_set_transcoder_timings()
2663 		crtc_vtotal -= 1;  in intel_set_transcoder_timings()
2664 		crtc_vblank_end -= 1;  in intel_set_transcoder_timings()
2667 			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;  in intel_set_transcoder_timings()
2669 			vsyncshift = adjusted_mode->crtc_hsync_start -  in intel_set_transcoder_timings()
2670 				adjusted_mode->crtc_htotal / 2;  in intel_set_transcoder_timings()
2672 			vsyncshift += adjusted_mode->crtc_htotal;  in intel_set_transcoder_timings()
2682 			       crtc_vblank_start - crtc_vdisplay);  in intel_set_transcoder_timings()
2697 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |  in intel_set_transcoder_timings()
2698 		       HTOTAL(adjusted_mode->crtc_htotal - 1));  in intel_set_transcoder_timings()
2700 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |  in intel_set_transcoder_timings()
2701 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));  in intel_set_transcoder_timings()
2703 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |  in intel_set_transcoder_timings()
2704 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));  in intel_set_transcoder_timings()
2707 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2708 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2710 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings()
2711 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings()
2713 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |  in intel_set_transcoder_timings()
2714 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));  in intel_set_transcoder_timings()
2720 	if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&  in intel_set_transcoder_timings()
2723 			       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2724 			       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2730 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings_lrr()
2731 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings_lrr()
2734 	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));  in intel_set_transcoder_timings_lrr()
2736 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings_lrr()
2737 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings_lrr()
2738 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings_lrr()
2739 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings_lrr()
2741 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {  in intel_set_transcoder_timings_lrr()
2743 		crtc_vtotal -= 1;  in intel_set_transcoder_timings_lrr()
2744 		crtc_vblank_end -= 1;  in intel_set_transcoder_timings_lrr()
2750 			       crtc_vblank_start - crtc_vdisplay);  in intel_set_transcoder_timings_lrr()
2764 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings_lrr()
2765 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings_lrr()
2771 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings_lrr()
2772 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings_lrr()
2778 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_pipe_src_size()
2779 	int width = drm_rect_width(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2780 	int height = drm_rect_height(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2781 	enum pipe pipe = crtc->pipe;  in intel_set_pipe_src_size()
2787 		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));  in intel_set_pipe_src_size()
2793 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_pipe_is_interlaced()
2799 	    display->platform.broadwell || display->platform.haswell)  in intel_pipe_is_interlaced()
2811 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_get_transcoder_timings()
2812 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_get_transcoder_timings()
2816 	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2817 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2822 		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2823 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2827 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2828 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2831 	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2832 	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2834 	/* FIXME TGL+ DSI transcoders have this! */  in intel_get_transcoder_timings()
2838 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2839 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2842 	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2843 	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2846 		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;  in intel_get_transcoder_timings()
2847 		adjusted_mode->crtc_vtotal += 1;  in intel_get_transcoder_timings()
2848 		adjusted_mode->crtc_vblank_end += 1;  in intel_get_transcoder_timings()
2852 		adjusted_mode->crtc_vblank_start =  in intel_get_transcoder_timings()
2853 			adjusted_mode->crtc_vdisplay +  in intel_get_transcoder_timings()
2860 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_joiner_adjust_pipe_src()
2862 	enum pipe primary_pipe, pipe = crtc->pipe;  in intel_joiner_adjust_pipe_src()
2869 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_joiner_adjust_pipe_src()
2871 	drm_rect_translate_to(&crtc_state->pipe_src,  in intel_joiner_adjust_pipe_src()
2872 			      (pipe - primary_pipe) * width, 0);  in intel_joiner_adjust_pipe_src()
2881 	tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));  in intel_get_pipe_src_size()
2883 	drm_rect_init(&pipe_config->pipe_src, 0, 0,  in intel_get_pipe_src_size()
2893 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_set_pipeconf()
2897 	 * - We keep both pipes enabled on 830  in i9xx_set_pipeconf()
2898 	 * - During modeset the pipe is still disabled and must remain so  in i9xx_set_pipeconf()
2899 	 * - During fastset the pipe is already enabled and must remain so  in i9xx_set_pipeconf()
2901 	if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))  in i9xx_set_pipeconf()
2904 	if (crtc_state->double_wide)  in i9xx_set_pipeconf()
2908 	if (display->platform.g4x || display->platform.valleyview ||  in i9xx_set_pipeconf()
2909 	    display->platform.cherryview) {  in i9xx_set_pipeconf()
2911 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
2915 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
2918 			MISSING_CASE(crtc_state->pipe_bpp);  in i9xx_set_pipeconf()
2932 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {  in i9xx_set_pipeconf()
2942 	if ((display->platform.valleyview || display->platform.cherryview) &&  in i9xx_set_pipeconf()
2943 	    crtc_state->limited_color_range)  in i9xx_set_pipeconf()
2946 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in i9xx_set_pipeconf()
2948 	if (crtc_state->wgc_enable)  in i9xx_set_pipeconf()
2951 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in i9xx_set_pipeconf()
2963 	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_output_format()
2972 			drm_WARN_ON(display->drm,  in bdw_get_pipe_misc_output_format()
2988 	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;  in i9xx_get_pipe_config()
2993 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in i9xx_get_pipe_config()
3002 	pipe_config->cpu_transcoder = cpu_transcoder;  in i9xx_get_pipe_config()
3004 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in i9xx_get_pipe_config()
3005 	pipe_config->sink_format = pipe_config->output_format;  in i9xx_get_pipe_config()
3007 	if (display->platform.g4x || display->platform.valleyview ||  in i9xx_get_pipe_config()
3008 	    display->platform.cherryview) {  in i9xx_get_pipe_config()
3011 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
3014 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
3017 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
3025 	if ((display->platform.valleyview || display->platform.cherryview) &&  in i9xx_get_pipe_config()
3027 		pipe_config->limited_color_range = true;  in i9xx_get_pipe_config()
3029 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);  in i9xx_get_pipe_config()
3031 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in i9xx_get_pipe_config()
3033 	if ((display->platform.valleyview || display->platform.cherryview) &&  in i9xx_get_pipe_config()
3035 		pipe_config->wgc_enable = true;  in i9xx_get_pipe_config()
3040 		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;  in i9xx_get_pipe_config()
3047 	i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);  in i9xx_get_pipe_config()
3050 		tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;  in i9xx_get_pipe_config()
3051 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3054 	} else if (display->platform.i945g || display->platform.i945gm ||  in i9xx_get_pipe_config()
3055 		   display->platform.g33 || display->platform.pineview) {  in i9xx_get_pipe_config()
3056 		tmp = pipe_config->dpll_hw_state.i9xx.dpll;  in i9xx_get_pipe_config()
3057 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3062 		 * port and will be fixed up in the encoder->get_config  in i9xx_get_pipe_config()
3064 		pipe_config->pixel_multiplier = 1;  in i9xx_get_pipe_config()
3067 	if (display->platform.cherryview)  in i9xx_get_pipe_config()
3069 	else if (display->platform.valleyview)  in i9xx_get_pipe_config()
3079 	pipe_config->hw.adjusted_mode.crtc_clock =  in i9xx_get_pipe_config()
3080 		pipe_config->port_clock / pipe_config->pixel_multiplier;  in i9xx_get_pipe_config()
3093 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_set_pipeconf()
3097 	 * - During modeset the pipe is still disabled and must remain so  in ilk_set_pipeconf()
3098 	 * - During fastset the pipe is already enabled and must remain so  in ilk_set_pipeconf()
3103 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
3106 		MISSING_CASE(crtc_state->pipe_bpp);  in ilk_set_pipeconf()
3122 	if (crtc_state->dither)  in ilk_set_pipeconf()
3125 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in ilk_set_pipeconf()
3134 	drm_WARN_ON(display->drm, crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3135 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);  in ilk_set_pipeconf()
3137 	if (crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3141 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in ilk_set_pipeconf()
3144 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in ilk_set_pipeconf()
3146 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in ilk_set_pipeconf()
3147 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);  in ilk_set_pipeconf()
3156 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_set_transconf()
3160 	 * - During modeset the pipe is still disabled and must remain so  in hsw_set_transconf()
3161 	 * - During fastset the pipe is already enabled and must remain so  in hsw_set_transconf()
3166 	if (display->platform.haswell && crtc_state->dither)  in hsw_set_transconf()
3169 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in hsw_set_transconf()
3174 	if (display->platform.haswell &&  in hsw_set_transconf()
3175 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in hsw_set_transconf()
3186 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in bdw_set_pipe_misc()
3189 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipe_misc()
3205 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipe_misc()
3209 	if (crtc_state->dither)  in bdw_set_pipe_misc()
3212 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in bdw_set_pipe_misc()
3213 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)  in bdw_set_pipe_misc()
3216 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in bdw_set_pipe_misc()
3227 	if (display->platform.broadwell)  in bdw_set_pipe_misc()
3230 	intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);  in bdw_set_pipe_misc()
3238 	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_bpp()
3251 	 * For previous platforms with DSI interface, bits 5:7  in bdw_get_pipe_misc_bpp()
3255 	 * MIPI DSI HW readout.  in bdw_get_pipe_misc_bpp()
3283 	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3284 	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3285 	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3286 	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3287 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;  in intel_get_m_n()
3295 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_get_m1_n1()
3330 	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;  in ilk_get_pipe_config()
3335 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in ilk_get_pipe_config()
3344 	pipe_config->cpu_transcoder = cpu_transcoder;  in ilk_get_pipe_config()
3348 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
3351 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
3354 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
3357 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
3364 		pipe_config->limited_color_range = true;  in ilk_get_pipe_config()
3369 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in ilk_get_pipe_config()
3372 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in ilk_get_pipe_config()
3376 	pipe_config->sink_format = pipe_config->output_format;  in ilk_get_pipe_config()
3378 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);  in ilk_get_pipe_config()
3380 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in ilk_get_pipe_config()
3382 	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);  in ilk_get_pipe_config()
3386 	pipe_config->pixel_multiplier = 1;  in ilk_get_pipe_config()
3414 	return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;  in joiner_pipes()
3444 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,  in enabled_uncompressed_joiner_pipes()
3447 		enum pipe pipe = crtc->pipe;  in enabled_uncompressed_joiner_pipes()
3473 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,  in enabled_bigjoiner_pipes()
3476 		enum pipe pipe = crtc->pipe;  in enabled_bigjoiner_pipes()
3518 	return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;  in get_joiner_primary_pipe()
3543 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,  in enabled_ultrajoiner_pipes()
3546 		enum pipe pipe = crtc->pipe;  in enabled_ultrajoiner_pipes()
3582 	drm_WARN_ON(display->drm,  in enabled_joiner_pipes()
3589 	drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);  in enabled_joiner_pipes()
3594 	drm_WARN_ON(display->drm,  in enabled_joiner_pipes()
3600 	drm_WARN_ON(display->drm,  in enabled_joiner_pipes()
3608 	drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,  in enabled_joiner_pipes()
3612 	drm_WARN(display->drm, secondary_ultrajoiner_pipes !=  in enabled_joiner_pipes()
3618 	drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,  in enabled_joiner_pipes()
3622 	drm_WARN(display->drm, secondary_bigjoiner_pipes !=  in enabled_joiner_pipes()
3628 	drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=  in enabled_joiner_pipes()
3642 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3657 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3672 		drm_WARN(display->drm,  in enabled_joiner_pipes()
3722 			drm_WARN(display->drm, 1,  in hsw_enabled_transcoders()
3741 		if (trans_pipe == crtc->pipe)  in hsw_enabled_transcoders()
3746 	cpu_transcoder = (enum transcoder) crtc->pipe;  in hsw_enabled_transcoders()
3750 	/* joiner secondary -> consider the primary pipe's transcoder as well */  in hsw_enabled_transcoders()
3751 	enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes);  in hsw_enabled_transcoders()
3752 	if (secondary_pipes & BIT(crtc->pipe)) {  in hsw_enabled_transcoders()
3753 		cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1;  in hsw_enabled_transcoders()
3783 	drm_WARN_ON(display->drm,  in assert_enabled_transcoders()
3788 	/* Only DSI transcoders can be ganged */  in assert_enabled_transcoders()
3789 	drm_WARN_ON(display->drm,  in assert_enabled_transcoders()
3809 	 * With the exception of DSI we should only ever have  in hsw_get_transcoder_state()
3810 	 * a single enabled transcoder. With DSI let's just  in hsw_get_transcoder_state()
3813 	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;  in hsw_get_transcoder_state()
3816 						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))  in hsw_get_transcoder_state()
3819 	if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {  in hsw_get_transcoder_state()
3821 				    TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
3824 			pipe_config->pch_pfit.force_thru = true;  in hsw_get_transcoder_state()
3828 			    TRANSCONF(display, pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
3838 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bxt_get_dsi_transcoder_state()
3855 		 * configuration, otherwise accessing DSI registers will hang  in bxt_get_dsi_transcoder_state()
3858 		 * need the same DSI PLL to be enabled for both DSI ports.  in bxt_get_dsi_transcoder_state()
3869 		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))  in bxt_get_dsi_transcoder_state()
3872 		pipe_config->cpu_transcoder = cpu_transcoder;  in bxt_get_dsi_transcoder_state()
3876 	return transcoder_is_dsi(pipe_config->cpu_transcoder);  in bxt_get_dsi_transcoder_state()
3882 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_joiner_get_config()
3884 	enum pipe pipe = crtc->pipe;  in intel_joiner_get_config()
3891 	crtc_state->joiner_pipes = primary_pipe | secondary_pipes;  in intel_joiner_get_config()
3901 	if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
3902 						       POWER_DOMAIN_PIPE(crtc->pipe)))  in hsw_get_pipe_config()
3905 	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
3907 	if ((display->platform.geminilake || display->platform.broxton) &&  in hsw_get_pipe_config()
3908 	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {  in hsw_get_pipe_config()
3909 		drm_WARN_ON(display->drm, active);  in hsw_get_pipe_config()
3919 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||  in hsw_get_pipe_config()
3923 	if (HAS_VRR(display) && !transcoder_is_dsi(pipe_config->cpu_transcoder))  in hsw_get_pipe_config()
3928 	if (display->platform.haswell) {  in hsw_get_pipe_config()
3930 					TRANSCONF(display, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
3933 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in hsw_get_pipe_config()
3935 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in hsw_get_pipe_config()
3937 		pipe_config->output_format =  in hsw_get_pipe_config()
3941 	pipe_config->sink_format = pipe_config->output_format;  in hsw_get_pipe_config()
3945 	tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));  in hsw_get_pipe_config()
3946 	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);  in hsw_get_pipe_config()
3947 	if (display->platform.broadwell || display->platform.haswell)  in hsw_get_pipe_config()
3948 		pipe_config->ips_linetime =  in hsw_get_pipe_config()
3951 	if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
3952 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {  in hsw_get_pipe_config()
3961 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&  in hsw_get_pipe_config()
3962 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
3963 		pipe_config->pixel_multiplier =  in hsw_get_pipe_config()
3965 				      TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;  in hsw_get_pipe_config()
3967 		pipe_config->pixel_multiplier = 1;  in hsw_get_pipe_config()
3970 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
3971 		tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
3973 		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;  in hsw_get_pipe_config()
3976 		pipe_config->framestart_delay = 1;  in hsw_get_pipe_config()
3980 	intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
3988 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_get_pipe_config()
3990 	if (!display->funcs.display->get_pipe_config(crtc, crtc_state))  in intel_crtc_get_pipe_config()
3993 	crtc_state->hw.active = true;  in intel_crtc_get_pipe_config()
4004 	 * The calculation for the data clock -> pixel clock is:  in intel_dotclock_calculate()
4009 	 * and for link freq (10kbs units) -> pixel clock it is:  in intel_dotclock_calculate()
4016 	if (!m_n->link_n)  in intel_dotclock_calculate()
4019 	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),  in intel_dotclock_calculate()
4020 				m_n->link_n * intel_dp_link_symbol_size(link_freq));  in intel_dotclock_calculate()
4028 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in intel_crtc_dotclock()
4029 						    &pipe_config->dp_m_n);  in intel_crtc_dotclock()
4030 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)  in intel_crtc_dotclock()
4031 		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,  in intel_crtc_dotclock()
4032 					     pipe_config->pipe_bpp);  in intel_crtc_dotclock()
4034 		dotclock = pipe_config->port_clock;  in intel_crtc_dotclock()
4036 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&  in intel_crtc_dotclock()
4040 	if (pipe_config->pixel_multiplier)  in intel_crtc_dotclock()
4041 		dotclock /= pipe_config->pixel_multiplier;  in intel_crtc_dotclock()
4056 	if (!encoder->get_hw_state(encoder, &pipe))  in intel_encoder_current_mode()
4072 		intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
4079 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);  in intel_encoder_current_mode()
4081 	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
4090 	return a == b || (a->cloneable & BIT(b->type) &&  in encoders_cloneable()
4091 			  b->cloneable & BIT(a->type));  in encoders_cloneable()
4103 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in check_single_encoder_cloning()
4104 		if (connector_state->crtc != &crtc->base)  in check_single_encoder_cloning()
4108 			to_intel_encoder(connector_state->best_encoder);  in check_single_encoder_cloning()
4119 		&crtc_state->hw.pipe_mode;  in hsw_linetime_wm()
4122 	if (!crtc_state->hw.enable)  in hsw_linetime_wm()
4125 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_linetime_wm()
4126 					pipe_mode->crtc_clock);  in hsw_linetime_wm()
4135 		&crtc_state->hw.pipe_mode;  in hsw_ips_linetime_wm()
4138 	if (!crtc_state->hw.enable)  in hsw_ips_linetime_wm()
4141 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_ips_linetime_wm()
4142 					cdclk_state->logical.cdclk);  in hsw_ips_linetime_wm()
4150 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in skl_linetime_wm()
4151 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in skl_linetime_wm()
4153 		&crtc_state->hw.pipe_mode;  in skl_linetime_wm()
4156 	if (!crtc_state->hw.enable)  in skl_linetime_wm()
4159 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,  in skl_linetime_wm()
4160 				   crtc_state->pixel_rate);  in skl_linetime_wm()
4163 	if ((display->platform.geminilake || display->platform.broxton) &&  in skl_linetime_wm()
4179 		crtc_state->linetime = skl_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4181 		crtc_state->linetime = hsw_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4190 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,  in hsw_compute_linetime_wm()
4204 	if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&  in intel_crtc_atomic_check()
4206 	    !crtc_state->hw.active)  in intel_crtc_atomic_check()
4207 		crtc_state->update_wm_post = true;  in intel_crtc_atomic_check()
4221 		drm_dbg_kms(display->drm,  in intel_crtc_atomic_check()
4223 			    crtc->base.base.id, crtc->base.name);  in intel_crtc_atomic_check()
4247 	    display->platform.broadwell || display->platform.haswell) {  in intel_crtc_atomic_check()
4266 	struct drm_connector *connector = conn_state->connector;  in compute_sink_pipe_bpp()
4267 	const struct drm_display_info *info = &connector->display_info;  in compute_sink_pipe_bpp()
4270 	switch (conn_state->max_bpc) {  in compute_sink_pipe_bpp()
4284 		MISSING_CASE(conn_state->max_bpc);  in compute_sink_pipe_bpp()
4285 		return -EINVAL;  in compute_sink_pipe_bpp()
4288 	if (bpp < crtc_state->pipe_bpp) {  in compute_sink_pipe_bpp()
4289 		drm_dbg_kms(display->drm,  in compute_sink_pipe_bpp()
4292 			    connector->base.id, connector->name,  in compute_sink_pipe_bpp()
4293 			    bpp, 3 * info->bpc,  in compute_sink_pipe_bpp()
4294 			    3 * conn_state->max_requested_bpc,  in compute_sink_pipe_bpp()
4295 			    crtc_state->pipe_bpp);  in compute_sink_pipe_bpp()
4297 		crtc_state->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
4314 	if (display->platform.g4x || display->platform.valleyview ||  in compute_baseline_pipe_bpp()
4315 	    display->platform.cherryview)  in compute_baseline_pipe_bpp()
4322 	crtc_state->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
4325 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in compute_baseline_pipe_bpp()
4328 		if (connector_state->crtc != &crtc->base)  in compute_baseline_pipe_bpp()
4349 	 * We're going to peek into connector->state,  in check_digital_port_conflicts()
4352 	drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);  in check_digital_port_conflicts()
4359 	drm_connector_list_iter_begin(display->drm, &conn_iter);  in check_digital_port_conflicts()
4365 			drm_atomic_get_new_connector_state(&state->base,  in check_digital_port_conflicts()
4368 			connector_state = connector->state;  in check_digital_port_conflicts()
4370 		if (!connector_state->best_encoder)  in check_digital_port_conflicts()
4373 		encoder = to_intel_encoder(connector_state->best_encoder);  in check_digital_port_conflicts()
4375 		drm_WARN_ON(display->drm, !connector_state->crtc);  in check_digital_port_conflicts()
4377 		switch (encoder->type) {  in check_digital_port_conflicts()
4379 			if (drm_WARN_ON(display->drm, !HAS_DDI(display)))  in check_digital_port_conflicts()
4386 			if (used_ports & BIT(encoder->port))  in check_digital_port_conflicts()
4389 			used_ports |= BIT(encoder->port);  in check_digital_port_conflicts()
4393 				1 << encoder->port;  in check_digital_port_conflicts()
4417 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4418 				  crtc_state->uapi.degamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4419 	drm_property_replace_blob(&crtc_state->hw.gamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4420 				  crtc_state->uapi.gamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4421 	drm_property_replace_blob(&crtc_state->hw.ctm,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4422 				  crtc_state->uapi.ctm);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4434 	crtc_state->hw.enable = crtc_state->uapi.enable;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4435 	crtc_state->hw.active = crtc_state->uapi.active;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4436 	drm_mode_copy(&crtc_state->hw.mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4437 		      &crtc_state->uapi.mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4438 	drm_mode_copy(&crtc_state->hw.adjusted_mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4439 		      &crtc_state->uapi.adjusted_mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4440 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4455 	drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,  in copy_joiner_crtc_state_nomodeset()
4456 				  primary_crtc_state->hw.degamma_lut);  in copy_joiner_crtc_state_nomodeset()
4457 	drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,  in copy_joiner_crtc_state_nomodeset()
4458 				  primary_crtc_state->hw.gamma_lut);  in copy_joiner_crtc_state_nomodeset()
4459 	drm_property_replace_blob(&secondary_crtc_state->hw.ctm,  in copy_joiner_crtc_state_nomodeset()
4460 				  primary_crtc_state->hw.ctm);  in copy_joiner_crtc_state_nomodeset()
4462 	secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;  in copy_joiner_crtc_state_nomodeset()
4476 	WARN_ON(primary_crtc_state->joiner_pipes !=  in copy_joiner_crtc_state_modeset()
4477 		secondary_crtc_state->joiner_pipes);  in copy_joiner_crtc_state_modeset()
4481 		return -ENOMEM;  in copy_joiner_crtc_state_modeset()
4484 	saved_state->uapi = secondary_crtc_state->uapi;  in copy_joiner_crtc_state_modeset()
4485 	saved_state->scaler_state = secondary_crtc_state->scaler_state;  in copy_joiner_crtc_state_modeset()
4486 	saved_state->shared_dpll = secondary_crtc_state->shared_dpll;  in copy_joiner_crtc_state_modeset()
4487 	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;  in copy_joiner_crtc_state_modeset()
4490 	if (secondary_crtc_state->dp_tunnel_ref.tunnel)  in copy_joiner_crtc_state_modeset()
4491 		drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);  in copy_joiner_crtc_state_modeset()
4495 	/* Re-init hw state */  in copy_joiner_crtc_state_modeset()
4496 	memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));  in copy_joiner_crtc_state_modeset()
4497 	secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;  in copy_joiner_crtc_state_modeset()
4498 	secondary_crtc_state->hw.active = primary_crtc_state->hw.active;  in copy_joiner_crtc_state_modeset()
4499 	drm_mode_copy(&secondary_crtc_state->hw.mode,  in copy_joiner_crtc_state_modeset()
4500 		      &primary_crtc_state->hw.mode);  in copy_joiner_crtc_state_modeset()
4501 	drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,  in copy_joiner_crtc_state_modeset()
4502 		      &primary_crtc_state->hw.pipe_mode);  in copy_joiner_crtc_state_modeset()
4503 	drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,  in copy_joiner_crtc_state_modeset()
4504 		      &primary_crtc_state->hw.adjusted_mode);  in copy_joiner_crtc_state_modeset()
4505 	secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;  in copy_joiner_crtc_state_modeset()
4507 	if (primary_crtc_state->dp_tunnel_ref.tunnel)  in copy_joiner_crtc_state_modeset()
4508 		drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,  in copy_joiner_crtc_state_modeset()
4509 				      &secondary_crtc_state->dp_tunnel_ref);  in copy_joiner_crtc_state_modeset()
4513 	secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;  in copy_joiner_crtc_state_modeset()
4514 	secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;  in copy_joiner_crtc_state_modeset()
4515 	secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;  in copy_joiner_crtc_state_modeset()
4517 	WARN_ON(primary_crtc_state->joiner_pipes !=  in copy_joiner_crtc_state_modeset()
4518 		secondary_crtc_state->joiner_pipes);  in copy_joiner_crtc_state_modeset()
4534 		return -ENOMEM;  in intel_crtc_prepare_cleared_state()
4536 	/* free the old crtc_state->hw members */  in intel_crtc_prepare_cleared_state()
4546 	saved_state->uapi = crtc_state->uapi;  in intel_crtc_prepare_cleared_state()
4547 	saved_state->inherited = crtc_state->inherited;  in intel_crtc_prepare_cleared_state()
4548 	saved_state->scaler_state = crtc_state->scaler_state;  in intel_crtc_prepare_cleared_state()
4549 	saved_state->shared_dpll = crtc_state->shared_dpll;  in intel_crtc_prepare_cleared_state()
4550 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;  in intel_crtc_prepare_cleared_state()
4551 	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,  in intel_crtc_prepare_cleared_state()
4552 	       sizeof(saved_state->icl_port_dplls));  in intel_crtc_prepare_cleared_state()
4553 	saved_state->crc_enabled = crtc_state->crc_enabled;  in intel_crtc_prepare_cleared_state()
4554 	if (display->platform.g4x ||  in intel_crtc_prepare_cleared_state()
4555 	    display->platform.valleyview || display->platform.cherryview)  in intel_crtc_prepare_cleared_state()
4556 		saved_state->wm = crtc_state->wm;  in intel_crtc_prepare_cleared_state()
4579 	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;  in intel_modeset_pipe_config()
4581 	crtc_state->framestart_delay = 1;  in intel_modeset_pipe_config()
4584 	 * Sanitize sync polarity flags based on requested ones. If neither  in intel_modeset_pipe_config()
4588 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4590 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;  in intel_modeset_pipe_config()
4592 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4594 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;  in intel_modeset_pipe_config()
4600 	crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);  in intel_modeset_pipe_config()
4601 	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];  in intel_modeset_pipe_config()
4603 	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {  in intel_modeset_pipe_config()
4604 		drm_dbg_kms(display->drm,  in intel_modeset_pipe_config()
4606 			    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4607 			    FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));  in intel_modeset_pipe_config()
4608 		crtc_state->bw_constrained = true;  in intel_modeset_pipe_config()
4611 	base_bpp = crtc_state->pipe_bpp;  in intel_modeset_pipe_config()
4621 	drm_mode_get_hv_timing(&crtc_state->hw.mode,  in intel_modeset_pipe_config()
4623 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_modeset_pipe_config()
4626 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4628 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4630 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4634 			drm_dbg_kms(display->drm,  in intel_modeset_pipe_config()
4636 				    encoder->base.base.id, encoder->base.name);  in intel_modeset_pipe_config()
4637 			return -EINVAL;  in intel_modeset_pipe_config()
4644 		if (encoder->compute_output_type)  in intel_modeset_pipe_config()
4645 			crtc_state->output_types |=  in intel_modeset_pipe_config()
4646 				BIT(encoder->compute_output_type(encoder, crtc_state,  in intel_modeset_pipe_config()
4649 			crtc_state->output_types |= BIT(encoder->type);  in intel_modeset_pipe_config()
4653 	crtc_state->port_clock = 0;  in intel_modeset_pipe_config()
4654 	crtc_state->pixel_multiplier = 1;  in intel_modeset_pipe_config()
4657 	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,  in intel_modeset_pipe_config()
4664 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4666 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4668 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4671 		ret = encoder->compute_config(encoder, crtc_state,  in intel_modeset_pipe_config()
4673 		if (ret == -EDEADLK)  in intel_modeset_pipe_config()
4676 			drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
4677 				    encoder->base.base.id, encoder->base.name, ret);  in intel_modeset_pipe_config()
4684 	if (!crtc_state->port_clock)  in intel_modeset_pipe_config()
4685 		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock  in intel_modeset_pipe_config()
4686 			* crtc_state->pixel_multiplier;  in intel_modeset_pipe_config()
4689 	if (ret == -EDEADLK)  in intel_modeset_pipe_config()
4692 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
4693 			    crtc->base.base.id, crtc->base.name, ret);  in intel_modeset_pipe_config()
4697 	/* Dithering seems to not pass-through bits correctly when it should, so  in intel_modeset_pipe_config()
4701 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
4702 		!crtc_state->dither_force_disable;  in intel_modeset_pipe_config()
4703 	drm_dbg_kms(display->drm,  in intel_modeset_pipe_config()
4705 		    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4706 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);  in intel_modeset_pipe_config()
4723 	for_each_new_connector_in_state(&state->base, connector,  in intel_modeset_pipe_config_late()
4726 			to_intel_encoder(conn_state->best_encoder);  in intel_modeset_pipe_config_late()
4729 		if (conn_state->crtc != &crtc->base ||  in intel_modeset_pipe_config_late()
4730 		    !encoder->compute_config_late)  in intel_modeset_pipe_config_late()
4733 		ret = encoder->compute_config_late(encoder, crtc_state,  in intel_modeset_pipe_config_late()
4752 	diff = abs(clock1 - clock2);  in intel_fuzzy_clock_check()
4764 	return m_n->tu == m2_n2->tu &&  in intel_compare_link_m_n()
4765 		m_n->data_m == m2_n2->data_m &&  in intel_compare_link_m_n()
4766 		m_n->data_n == m2_n2->data_n &&  in intel_compare_link_m_n()
4767 		m_n->link_m == m2_n2->link_m &&  in intel_compare_link_m_n()
4768 		m_n->link_n == m2_n2->link_n;  in intel_compare_link_m_n()
4782 	return a->pixelformat == b->pixelformat &&  in intel_compare_dp_vsc_sdp()
4783 		a->colorimetry == b->colorimetry &&  in intel_compare_dp_vsc_sdp()
4784 		a->bpc == b->bpc &&  in intel_compare_dp_vsc_sdp()
4785 		a->dynamic_range == b->dynamic_range &&  in intel_compare_dp_vsc_sdp()
4786 		a->content_type == b->content_type;  in intel_compare_dp_vsc_sdp()
4793 	return a->vtotal == b->vtotal &&  in intel_compare_dp_as_sdp()
4794 		a->target_rr == b->target_rr &&  in intel_compare_dp_as_sdp()
4795 		a->duration_incr_ms == b->duration_incr_ms &&  in intel_compare_dp_as_sdp()
4796 		a->duration_decr_ms == b->duration_decr_ms &&  in intel_compare_dp_as_sdp()
4797 		a->mode == b->mode;  in intel_compare_dp_as_sdp()
4820 			   crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
4823 			   crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
4850 	hdmi_infoframe_log(loglevel, display->drm->dev, a);  in pipe_config_infoframe_mismatch()
4852 	hdmi_infoframe_log(loglevel, display->drm->dev, b);  in pipe_config_infoframe_mismatch()
4891 	for (i = len - 1; i >= 0; i--) {  in memcmp_diff_len()
4923 	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */  in pipe_config_pll_mismatch()
4939 	char *chipname = a->use_c10 ? "C10" : "C20";  in pipe_config_cx0pll_mismatch()
4958 	return HAS_LRR(display) && old_crtc_state->inherited &&  in allow_vblank_delay_fastset()
4968 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_pipe_config_compare()
4974 		p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);  in intel_pipe_config_compare()
4976 		p = drm_err_printer(display->drm, NULL);  in intel_pipe_config_compare()
4979 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
4980 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
4984 				     current_config->name, \  in intel_pipe_config_compare()
4985 				     pipe_config->name); \  in intel_pipe_config_compare()
4991 	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \  in intel_pipe_config_compare()
4992 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
4996 				     current_config->name & (mask), \  in intel_pipe_config_compare()
4997 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5003 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5004 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5008 				     current_config->name, \  in intel_pipe_config_compare()
5009 				     pipe_config->name); \  in intel_pipe_config_compare()
5015 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5018 				     current_config->name, \  in intel_pipe_config_compare()
5019 				     pipe_config->name); \  in intel_pipe_config_compare()
5025 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5026 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5030 				     str_yes_no(current_config->name), \  in intel_pipe_config_compare()
5031 				     str_yes_no(pipe_config->name)); \  in intel_pipe_config_compare()
5037 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5040 				     current_config->name, \  in intel_pipe_config_compare()
5041 				     pipe_config->name); \  in intel_pipe_config_compare()
5047 	if (!intel_compare_link_m_n(&current_config->name, \  in intel_pipe_config_compare()
5048 				    &pipe_config->name)) { \  in intel_pipe_config_compare()
5052 				     current_config->name.tu, \  in intel_pipe_config_compare()
5053 				     current_config->name.data_m, \  in intel_pipe_config_compare()
5054 				     current_config->name.data_n, \  in intel_pipe_config_compare()
5055 				     current_config->name.link_m, \  in intel_pipe_config_compare()
5056 				     current_config->name.link_n, \  in intel_pipe_config_compare()
5057 				     pipe_config->name.tu, \  in intel_pipe_config_compare()
5058 				     pipe_config->name.data_m, \  in intel_pipe_config_compare()
5059 				     pipe_config->name.data_n, \  in intel_pipe_config_compare()
5060 				     pipe_config->name.link_m, \  in intel_pipe_config_compare()
5061 				     pipe_config->name.link_n); \  in intel_pipe_config_compare()
5067 	if (!intel_dpll_compare_hw_state(display, &current_config->name, \  in intel_pipe_config_compare()
5068 					 &pipe_config->name)) { \  in intel_pipe_config_compare()
5070 					 &current_config->name, \  in intel_pipe_config_compare()
5071 					 &pipe_config->name); \  in intel_pipe_config_compare()
5077 	if (!intel_cx0pll_compare_hw_state(&current_config->name, \  in intel_pipe_config_compare()
5078 					   &pipe_config->name)) { \  in intel_pipe_config_compare()
5080 					    &current_config->name, \  in intel_pipe_config_compare()
5081 					    &pipe_config->name); \  in intel_pipe_config_compare()
5098 	if (!fastset || !pipe_config->update_lrr) { \  in intel_pipe_config_compare()
5112 	if ((current_config->name ^ pipe_config->name) & (mask)) { \  in intel_pipe_config_compare()
5116 				     current_config->name & (mask), \  in intel_pipe_config_compare()
5117 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5123 	if (!intel_compare_infoframe(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5124 				     &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5126 					       &current_config->infoframes.name, \  in intel_pipe_config_compare()
5127 					       &pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5133 	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5134 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5136 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5137 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5143 	if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5144 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5146 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5147 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5153 	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \  in intel_pipe_config_compare()
5154 	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \  in intel_pipe_config_compare()
5155 	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \  in intel_pipe_config_compare()
5157 					    current_config->name, \  in intel_pipe_config_compare()
5158 					    pipe_config->name, \  in intel_pipe_config_compare()
5165 	if (current_config->gamma_mode == pipe_config->gamma_mode && \  in intel_pipe_config_compare()
5167 				   current_config->lut, pipe_config->lut, \  in intel_pipe_config_compare()
5194 	((current_config->quirks | pipe_config->quirks) & (quirk))  in intel_pipe_config_compare()
5210 		if (!fastset || !pipe_config->update_m_n)  in intel_pipe_config_compare()
5243 	if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||  in intel_pipe_config_compare()
5244 	    display->platform.valleyview || display->platform.cherryview)  in intel_pipe_config_compare()
5280 		if (display->platform.cherryview)  in intel_pipe_config_compare()
5300 	if (display->dpll.mgr)  in intel_pipe_config_compare()
5304 	if (display->dpll.mgr || HAS_GMCH(display))  in intel_pipe_config_compare()
5314 	if (display->platform.g4x || DISPLAY_VER(display) >= 5)  in intel_pipe_config_compare()
5317 	if (!fastset || !pipe_config->update_m_n) {  in intel_pipe_config_compare()
5325 	if (current_config->has_psr || pipe_config->has_psr)  in intel_pipe_config_compare()
5328 	if (current_config->vrr.enable || pipe_config->vrr.enable)  in intel_pipe_config_compare()
5422 		assert_plane(plane, plane_state->is_y_plane ||  in intel_verify_planes()
5423 			     plane_state->uapi.visible);  in intel_verify_planes()
5431 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_pipe()
5434 	drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",  in intel_modeset_pipe()
5435 		    crtc->base.base.id, crtc->base.name, reason);  in intel_modeset_pipe()
5437 	ret = drm_atomic_add_affected_connectors(&state->base,  in intel_modeset_pipe()
5438 						 &crtc->base);  in intel_modeset_pipe()
5454 	crtc_state->uapi.mode_changed = true;  in intel_modeset_pipe()
5460  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5477 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {  in intel_modeset_pipes_in_mask_early()
5481 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_pipes_in_mask_early()
5485 		if (!crtc_state->hw.enable ||  in intel_modeset_pipes_in_mask_early()
5500 	crtc_state->uapi.mode_changed = true;  in intel_crtc_flag_modeset()
5502 	crtc_state->update_pipe = false;  in intel_crtc_flag_modeset()
5503 	crtc_state->update_m_n = false;  in intel_crtc_flag_modeset()
5504 	crtc_state->update_lrr = false;  in intel_crtc_flag_modeset()
5508  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5524 	for_each_intel_crtc(display->drm, crtc) {  in intel_modeset_all_pipes_late()
5528 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_all_pipes_late()
5532 		if (!crtc_state->hw.active ||  in intel_modeset_all_pipes_late()
5542 		crtc_state->update_planes |= crtc_state->active_planes;  in intel_modeset_all_pipes_late()
5543 		crtc_state->async_flip_planes = 0;  in intel_modeset_all_pipes_late()
5544 		crtc_state->do_async_flip = false;  in intel_modeset_all_pipes_late()
5558 	state = drm_atomic_state_alloc(display->drm);  in intel_modeset_commit_pipes()
5560 		return -ENOMEM;  in intel_modeset_commit_pipes()
5562 	state->acquire_ctx = ctx;  in intel_modeset_commit_pipes()
5563 	to_intel_atomic_state(state)->internal = true;  in intel_modeset_commit_pipes()
5565 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {  in intel_modeset_commit_pipes()
5574 		crtc_state->uapi.connectors_changed = true;  in intel_modeset_commit_pipes()
5601 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5610 			first_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5619 	for_each_intel_crtc(state->base.dev, crtc) {  in hsw_mode_set_planes_workaround()
5620 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in hsw_mode_set_planes_workaround()
5624 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;  in hsw_mode_set_planes_workaround()
5626 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5634 		enabled_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5638 		first_crtc_state->hsw_workaround_pipe = enabled_pipe;  in hsw_mode_set_planes_workaround()
5640 		other_crtc_state->hsw_workaround_pipe = first_pipe;  in hsw_mode_set_planes_workaround()
5653 		if (crtc_state->hw.active)  in intel_calc_active_pipes()
5654 			active_pipes |= BIT(crtc->pipe);  in intel_calc_active_pipes()
5656 			active_pipes &= ~BIT(crtc->pipe);  in intel_calc_active_pipes()
5666 	state->modeset = true;  in intel_modeset_checks()
5668 	if (display->platform.haswell)  in intel_modeset_checks()
5677 	return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||  in lrr_params_changed()
5678 		old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||  in lrr_params_changed()
5679 		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal;  in lrr_params_changed()
5686 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_crtc_check_fastset()
5689 	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)  in intel_crtc_check_fastset()
5690 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
5693 		drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",  in intel_crtc_check_fastset()
5694 			    crtc->base.base.id, crtc->base.name);  in intel_crtc_check_fastset()
5697 			new_crtc_state->update_lrr = true;  in intel_crtc_check_fastset()
5698 		new_crtc_state->uapi.mode_changed = false;  in intel_crtc_check_fastset()
5701 	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,  in intel_crtc_check_fastset()
5702 				   &new_crtc_state->dp_m_n))  in intel_crtc_check_fastset()
5703 		new_crtc_state->update_m_n = false;  in intel_crtc_check_fastset()
5705 	if (!lrr_params_changed(&old_crtc_state->hw.adjusted_mode,  in intel_crtc_check_fastset()
5706 				&new_crtc_state->hw.adjusted_mode))  in intel_crtc_check_fastset()
5707 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
5712 		new_crtc_state->update_pipe = true;  in intel_crtc_check_fastset()
5727 			drm_dbg_atomic(display->drm,  in intel_atomic_check_crtcs()
5729 				       crtc->base.base.id, crtc->base.name);  in intel_atomic_check_crtcs()
5745 		if (new_crtc_state->hw.enable &&  in intel_cpu_transcoders_need_modeset()
5746 		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&  in intel_cpu_transcoders_need_modeset()
5762 		if (new_crtc_state->hw.enable &&  in intel_pipes_need_modeset()
5763 		    pipes & BIT(crtc->pipe) &&  in intel_pipes_need_modeset()
5779 	if (!primary_crtc_state->joiner_pipes)  in intel_atomic_check_joiner()
5783 	if (drm_WARN_ON(display->drm,  in intel_atomic_check_joiner()
5784 			primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))  in intel_atomic_check_joiner()
5785 		return -EINVAL;  in intel_atomic_check_joiner()
5787 	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {  in intel_atomic_check_joiner()
5788 		drm_dbg_kms(display->drm,  in intel_atomic_check_joiner()
5791 			    primary_crtc->base.base.id, primary_crtc->base.name,  in intel_atomic_check_joiner()
5792 			    primary_crtc_state->joiner_pipes, joiner_pipes(display));  in intel_atomic_check_joiner()
5793 		return -EINVAL;  in intel_atomic_check_joiner()
5796 	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,  in intel_atomic_check_joiner()
5801 		secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);  in intel_atomic_check_joiner()
5806 		if (secondary_crtc_state->uapi.enable) {  in intel_atomic_check_joiner()
5807 			drm_dbg_kms(display->drm,  in intel_atomic_check_joiner()
5810 				    secondary_crtc->base.base.id, secondary_crtc->base.name,  in intel_atomic_check_joiner()
5811 				    primary_crtc->base.base.id, primary_crtc->base.name);  in intel_atomic_check_joiner()
5812 			return -EINVAL;  in intel_atomic_check_joiner()
5822 		if (WARN_ON(drm_crtc_index(&primary_crtc->base) >  in intel_atomic_check_joiner()
5823 			    drm_crtc_index(&secondary_crtc->base)))  in intel_atomic_check_joiner()
5824 			return -EINVAL;  in intel_atomic_check_joiner()
5826 		drm_dbg_kms(display->drm,  in intel_atomic_check_joiner()
5828 			    secondary_crtc->base.base.id, secondary_crtc->base.name,  in intel_atomic_check_joiner()
5829 			    primary_crtc->base.base.id, primary_crtc->base.name);  in intel_atomic_check_joiner()
5831 		secondary_crtc_state->joiner_pipes =  in intel_atomic_check_joiner()
5832 			primary_crtc_state->joiner_pipes;  in intel_atomic_check_joiner()
5850 	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,  in kill_joiner_secondaries()
5855 		secondary_crtc_state->joiner_pipes = 0;  in kill_joiner_secondaries()
5860 	primary_crtc_state->joiner_pipes = 0;  in kill_joiner_secondaries()
5892 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_uapi()
5895 	if (!new_crtc_state->uapi.active) {  in intel_async_flip_check_uapi()
5896 		drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
5898 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
5899 		return -EINVAL;  in intel_async_flip_check_uapi()
5903 		drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
5905 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
5906 		return -EINVAL;  in intel_async_flip_check_uapi()
5913 	if (new_crtc_state->joiner_pipes) {  in intel_async_flip_check_uapi()
5914 		drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
5916 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
5917 		return -EINVAL;  in intel_async_flip_check_uapi()
5922 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_uapi()
5932 		if (!plane->async_flip) {  in intel_async_flip_check_uapi()
5933 			drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
5935 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
5936 			return -EINVAL;  in intel_async_flip_check_uapi()
5939 		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {  in intel_async_flip_check_uapi()
5940 			drm_dbg_kms(display->drm,  in intel_async_flip_check_uapi()
5942 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
5943 			return -EINVAL;  in intel_async_flip_check_uapi()
5961 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_hw()
5964 	if (!new_crtc_state->hw.active) {  in intel_async_flip_check_hw()
5965 		drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
5967 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
5968 		return -EINVAL;  in intel_async_flip_check_hw()
5972 		drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
5974 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
5975 		return -EINVAL;  in intel_async_flip_check_hw()
5978 	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {  in intel_async_flip_check_hw()
5979 		drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
5981 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
5982 		return -EINVAL;  in intel_async_flip_check_hw()
5987 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_hw()
5995 		if (drm_WARN_ON(display->drm,  in intel_async_flip_check_hw()
5996 				new_crtc_state->do_async_flip && !plane->async_flip))  in intel_async_flip_check_hw()
5997 			return -EINVAL;  in intel_async_flip_check_hw()
6007 		if (!plane->async_flip)  in intel_async_flip_check_hw()
6010 		if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) {  in intel_async_flip_check_hw()
6011 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6013 				    plane->base.base.id, plane->base.name,  in intel_async_flip_check_hw()
6014 				    new_plane_state->hw.fb->modifier);  in intel_async_flip_check_hw()
6015 			return -EINVAL;  in intel_async_flip_check_hw()
6018 		if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format,  in intel_async_flip_check_hw()
6019 							new_plane_state->hw.fb->modifier)) {  in intel_async_flip_check_hw()
6020 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6022 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6023 			return -EINVAL;  in intel_async_flip_check_hw()
6027 		 * We turn the first async flip request into a sync flip  in intel_async_flip_check_hw()
6030 		if (!new_crtc_state->do_async_flip)  in intel_async_flip_check_hw()
6033 		if (old_plane_state->view.color_plane[0].mapping_stride !=  in intel_async_flip_check_hw()
6034 		    new_plane_state->view.color_plane[0].mapping_stride) {  in intel_async_flip_check_hw()
6035 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6037 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6038 			return -EINVAL;  in intel_async_flip_check_hw()
6041 		if (old_plane_state->hw.fb->modifier !=  in intel_async_flip_check_hw()
6042 		    new_plane_state->hw.fb->modifier) {  in intel_async_flip_check_hw()
6043 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6045 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6046 			return -EINVAL;  in intel_async_flip_check_hw()
6049 		if (old_plane_state->hw.fb->format !=  in intel_async_flip_check_hw()
6050 		    new_plane_state->hw.fb->format) {  in intel_async_flip_check_hw()
6051 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6053 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6054 			return -EINVAL;  in intel_async_flip_check_hw()
6057 		if (old_plane_state->hw.rotation !=  in intel_async_flip_check_hw()
6058 		    new_plane_state->hw.rotation) {  in intel_async_flip_check_hw()
6059 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6061 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6062 			return -EINVAL;  in intel_async_flip_check_hw()
6067 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6069 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6070 			return -EINVAL;  in intel_async_flip_check_hw()
6073 		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||  in intel_async_flip_check_hw()
6074 		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {  in intel_async_flip_check_hw()
6075 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6076 				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",  in intel_async_flip_check_hw()
6077 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6078 			return -EINVAL;  in intel_async_flip_check_hw()
6081 		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {  in intel_async_flip_check_hw()
6082 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6084 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6085 			return -EINVAL;  in intel_async_flip_check_hw()
6088 		if (old_plane_state->hw.pixel_blend_mode !=  in intel_async_flip_check_hw()
6089 		    new_plane_state->hw.pixel_blend_mode) {  in intel_async_flip_check_hw()
6090 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6092 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6093 			return -EINVAL;  in intel_async_flip_check_hw()
6096 		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {  in intel_async_flip_check_hw()
6097 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6099 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6100 			return -EINVAL;  in intel_async_flip_check_hw()
6103 		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {  in intel_async_flip_check_hw()
6104 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6106 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6107 			return -EINVAL;  in intel_async_flip_check_hw()
6111 		if (old_plane_state->decrypt != new_plane_state->decrypt) {  in intel_async_flip_check_hw()
6112 			drm_dbg_kms(display->drm,  in intel_async_flip_check_hw()
6114 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6115 			return -EINVAL;  in intel_async_flip_check_hw()
6139 		crtc = to_intel_crtc(plane_state->hw.crtc);  in intel_joiner_add_affected_crtcs()
6143 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_joiner_add_affected_crtcs()
6150 		affected_pipes |= crtc_state->joiner_pipes;  in intel_joiner_add_affected_crtcs()
6152 			modeset_pipes |= crtc_state->joiner_pipes;  in intel_joiner_add_affected_crtcs()
6155 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {  in intel_joiner_add_affected_crtcs()
6156 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_joiner_add_affected_crtcs()
6161 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {  in intel_joiner_add_affected_crtcs()
6166 		crtc_state->uapi.mode_changed = true;  in intel_joiner_add_affected_crtcs()
6168 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);  in intel_joiner_add_affected_crtcs()
6178 		/* Kill old joiner link, we may re-establish afterwards */  in intel_joiner_add_affected_crtcs()
6216 		if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))  in intel_atomic_check_config()
6223 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6235 		if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))  in intel_atomic_check_config()
6238 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6248 		*failed_pipe = crtc->pipe;  in intel_atomic_check_config()
6272 			if (ret == -EINVAL &&  in intel_atomic_check_config_and_link()
6285 		if (ret != -EAGAIN)  in intel_atomic_check_config_and_link()
6292  * intel_atomic_check - validate state object
6307 		return -ENODEV;  in intel_atomic_check()
6315 		if (!state->internal)  in intel_atomic_check()
6316 			new_crtc_state->inherited = false;  in intel_atomic_check()
6318 		if (new_crtc_state->inherited != old_crtc_state->inherited)  in intel_atomic_check()
6319 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6321 		if (new_crtc_state->uapi.scaling_filter !=  in intel_atomic_check()
6322 		    old_crtc_state->uapi.scaling_filter)  in intel_atomic_check()
6323 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6328 	ret = drm_atomic_helper_check_modeset(dev, &state->base);  in intel_atomic_check()
6347 			drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);  in intel_atomic_check()
6378 		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))  in intel_atomic_check()
6385 			enum transcoder master = new_crtc_state->mst_master_transcoder;  in intel_atomic_check()
6392 			u8 trans = new_crtc_state->sync_mode_slaves_mask;  in intel_atomic_check()
6394 			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_atomic_check()
6395 				trans |= BIT(new_crtc_state->master_transcoder);  in intel_atomic_check()
6401 		if (new_crtc_state->joiner_pipes) {  in intel_atomic_check()
6402 			if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))  in intel_atomic_check()
6418 		drm_dbg_kms(display->drm,  in intel_atomic_check()
6420 		ret = -EINVAL;  in intel_atomic_check()
6474 		drm_WARN_ON(display->drm,  in intel_atomic_check()
6490 	if (ret == -EDEADLK)  in intel_atomic_check()
6508 	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);  in intel_atomic_prepare_commit()
6520 	if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)  in intel_crtc_arm_fifo_underrun()
6521 		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);  in intel_crtc_arm_fifo_underrun()
6523 	if (crtc_state->has_pch_encoder) {  in intel_crtc_arm_fifo_underrun()
6535 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_pipe_fastset()
6536 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_pipe_fastset()
6550 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6553 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6555 		else if (old_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6568 	    display->platform.broadwell || display->platform.haswell)  in intel_pipe_fastset()
6571 	if (new_crtc_state->update_m_n)  in intel_pipe_fastset()
6572 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,  in intel_pipe_fastset()
6573 					       &new_crtc_state->dp_m_n);  in intel_pipe_fastset()
6575 	if (new_crtc_state->update_lrr)  in intel_pipe_fastset()
6589 	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);  in commit_pipe_pre_planes()
6599 		if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)  in commit_pipe_pre_planes()
6618 	drm_WARN_ON(display->drm, new_crtc_state->use_dsb);  in commit_pipe_post_planes()
6644 	for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc,  in intel_enable_crtc()
6653 	display->funcs.display->crtc_enable(state, crtc);  in intel_enable_crtc()
6655 	/* vblanks work again, re-enable pipe CRC. */  in intel_enable_crtc()
6669 	if (old_crtc_state->inherited ||  in intel_pre_update_crtc()
6676 		if (new_crtc_state->preload_luts &&  in intel_pre_update_crtc()
6696 	drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));  in intel_pre_update_crtc()
6700 	    !new_crtc_state->use_dsb)  in intel_pre_update_crtc()
6703 	if (!new_crtc_state->use_dsb)  in intel_pre_update_crtc()
6715 	if (new_crtc_state->use_dsb) {  in intel_update_crtc()
6716 		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);  in intel_update_crtc()
6718 		intel_dsb_commit(new_crtc_state->dsb_commit, false);  in intel_update_crtc()
6723 		if (new_crtc_state->dsb_commit)  in intel_update_crtc()
6724 			intel_dsb_commit(new_crtc_state->dsb_commit, false);  in intel_update_crtc()
6741 	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)  in intel_update_crtc()
6743 						 new_crtc_state->vrr.enable);  in intel_update_crtc()
6752 	    old_crtc_state->inherited)  in intel_update_crtc()
6768 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,  in intel_old_crtc_state_disables()
6772 	display->funcs.display->crtc_disable(state, crtc);  in intel_old_crtc_state_disables()
6774 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,  in intel_old_crtc_state_disables()
6779 		pipe_crtc->active = false;  in intel_old_crtc_state_disables()
6782 		if (!new_pipe_crtc_state->hw.active)  in intel_old_crtc_state_disables()
6806 		if (!old_crtc_state->hw.active)  in intel_commit_modeset_disables()
6809 		disable_pipes |= BIT(crtc->pipe);  in intel_commit_modeset_disables()
6813 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
6818 		drm_vblank_work_flush_all(&crtc->base);  in intel_commit_modeset_disables()
6821 	/* Only disable port sync and MST slaves */  in intel_commit_modeset_disables()
6823 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
6829 		/* In case of Transcoder port Sync master slave CRTCs can be  in intel_commit_modeset_disables()
6845 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
6856 	drm_WARN_ON(display->drm, disable_pipes);  in intel_commit_modeset_disables()
6866 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
6874 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
6891 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6893 		if (!new_crtc_state->hw.active)  in skl_commit_modeset_enables()
6898 			entries[pipe] = old_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
6915 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6932 			enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6937 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
6941 			entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
6952 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
6953 						 &old_crtc_state->wm.skl.ddb) &&  in skl_commit_modeset_enables()
6968 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
6987 	 * pipes: MST slaves and port sync masters  in skl_commit_modeset_enables()
6990 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7007 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7020 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7025 		drm_WARN_ON(display->drm,  in skl_commit_modeset_enables()
7026 			    skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7029 		entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7035 	drm_WARN_ON(display->drm, modeset_pipes);  in skl_commit_modeset_enables()
7036 	drm_WARN_ON(display->drm, update_pipes);  in skl_commit_modeset_enables()
7041 	struct drm_i915_private *i915 = to_i915(intel_state->base.dev);  in intel_atomic_commit_fence_wait()
7046 	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {  in intel_atomic_commit_fence_wait()
7047 		if (new_plane_state->fence) {  in intel_atomic_commit_fence_wait()
7048 			ret = dma_fence_wait_timeout(new_plane_state->fence, false,  in intel_atomic_commit_fence_wait()
7053 			dma_fence_put(new_plane_state->fence);  in intel_atomic_commit_fence_wait()
7054 			new_plane_state->fence = NULL;  in intel_atomic_commit_fence_wait()
7061 	if (crtc_state->dsb_commit)  in intel_atomic_dsb_wait_commit()
7062 		intel_dsb_wait(crtc_state->dsb_commit);  in intel_atomic_dsb_wait_commit()
7069 	if (crtc_state->dsb_commit) {  in intel_atomic_dsb_cleanup()
7070 		intel_dsb_cleanup(crtc_state->dsb_commit);  in intel_atomic_dsb_cleanup()
7071 		crtc_state->dsb_commit = NULL;  in intel_atomic_dsb_cleanup()
7089 	drm_atomic_helper_cleanup_planes(display->drm, &state->base);  in intel_atomic_cleanup_work()
7090 	drm_atomic_helper_commit_cleanup_done(&state->base);  in intel_atomic_cleanup_work()
7091 	drm_atomic_state_put(&state->base);  in intel_atomic_cleanup_work()
7102 		struct drm_framebuffer *fb = plane_state->hw.fb;  in intel_atomic_prepare_plane_clear_colors()
7118 		 * - 4 x 4 bytes per-channel value  in intel_atomic_prepare_plane_clear_colors()
7120 		 * - 8 bytes native color value used by the display  in intel_atomic_prepare_plane_clear_colors()
7122 		 *    above per-channel values)  in intel_atomic_prepare_plane_clear_colors()
7129 					      fb->offsets[cc_plane] + 16,  in intel_atomic_prepare_plane_clear_colors()
7130 					      &plane_state->ccval,  in intel_atomic_prepare_plane_clear_colors()
7131 					      sizeof(plane_state->ccval));  in intel_atomic_prepare_plane_clear_colors()
7133 		drm_WARN_ON(display->drm, ret);  in intel_atomic_prepare_plane_clear_colors()
7144 	if (!new_crtc_state->hw.active)  in intel_atomic_dsb_prepare()
7147 	if (state->base.legacy_cursor_update)  in intel_atomic_dsb_prepare()
7151 	new_crtc_state->use_dsb =  in intel_atomic_dsb_prepare()
7152 		!new_crtc_state->do_async_flip &&  in intel_atomic_dsb_prepare()
7153 		(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&  in intel_atomic_dsb_prepare()
7167 	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)  in intel_atomic_dsb_finish()
7175 	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,  in intel_atomic_dsb_finish()
7176 						       new_crtc_state->use_dsb ? 1024 : 16);  in intel_atomic_dsb_finish()
7177 	if (!new_crtc_state->dsb_commit) {  in intel_atomic_dsb_finish()
7178 		new_crtc_state->use_dsb = false;  in intel_atomic_dsb_finish()
7183 	if (new_crtc_state->use_dsb) {  in intel_atomic_dsb_finish()
7185 			intel_color_commit_noarm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7187 		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7195 		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7198 		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7201 			intel_color_commit_arm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7203 		bdw_set_pipe_misc(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7205 		intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7207 		intel_crtc_planes_update_arm(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7211 			skl_detach_scalers(new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7214 		if (!new_crtc_state->dsb_color_vblank) {  in intel_atomic_dsb_finish()
7215 			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);  in intel_atomic_dsb_finish()
7217 			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);  in intel_atomic_dsb_finish()
7218 			intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7219 			intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);  in intel_atomic_dsb_finish()
7220 			intel_dsb_interrupt(new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7224 	if (new_crtc_state->dsb_color_vblank)  in intel_atomic_dsb_finish()
7225 		intel_dsb_chain(state, new_crtc_state->dsb_commit,  in intel_atomic_dsb_finish()
7226 				new_crtc_state->dsb_color_vblank, true);  in intel_atomic_dsb_finish()
7228 	intel_dsb_finish(new_crtc_state->dsb_commit);  in intel_atomic_dsb_finish()
7234 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_atomic_commit_tail()
7256 	drm_atomic_helper_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7257 	drm_dp_mst_atomic_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7269 	 * 3. Due to some long delay PSR is re-entered  in intel_atomic_commit_tail()
7270 	 * 4. DC5 entry -> DMC saves the already written new  in intel_atomic_commit_tail()
7273 	 * 5. DC5 exit -> DMC restores a mixture of old and  in intel_atomic_commit_tail()
7275 	 * 6. PSR exit -> hardware latches a mixture of old and  in intel_atomic_commit_tail()
7276 	 *    new register values -> corrupted frame, or worse  in intel_atomic_commit_tail()
7293 			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7300 	/* FIXME: Eventually get rid of our crtc->config pointer */  in intel_atomic_commit_tail()
7302 		crtc->config = new_crtc_state;  in intel_atomic_commit_tail()
7312 	if (state->modeset) {  in intel_atomic_commit_tail()
7313 		drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base);  in intel_atomic_commit_tail()
7327 		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {  in intel_atomic_commit_tail()
7328 			spin_lock_irq(&display->drm->event_lock);  in intel_atomic_commit_tail()
7329 			drm_crtc_send_vblank_event(&crtc->base,  in intel_atomic_commit_tail()
7330 						   new_crtc_state->uapi.event);  in intel_atomic_commit_tail()
7331 			spin_unlock_irq(&display->drm->event_lock);  in intel_atomic_commit_tail()
7333 			new_crtc_state->uapi.event = NULL;  in intel_atomic_commit_tail()
7342 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7347 	display->funcs.display->commit_modeset_enables(state);  in intel_atomic_commit_tail()
7356 	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.  in intel_atomic_commit_tail()
7357 	 * - schedule that vblank worker _before_ calling hw_done  in intel_atomic_commit_tail()
7358 	 * - at the start of commit_tail, cancel it _synchrously  in intel_atomic_commit_tail()
7359 	 * - switch over to the vblank wait helper in the core after that since  in intel_atomic_commit_tail()
7362 	drm_atomic_helper_wait_for_flip_done(display->drm, &state->base);  in intel_atomic_commit_tail()
7365 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7370 		if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb)  in intel_atomic_commit_tail()
7376 	 * optimal watermarks on platforms that need two-step watermark  in intel_atomic_commit_tail()
7385 		 * So re-enable underrun reporting after some planes get enabled.  in intel_atomic_commit_tail()
7392 			intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);  in intel_atomic_commit_tail()
7402 		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7410 		 * cleanup. So copy and reset the dsb structure to sync with  in intel_atomic_commit_tail()
7413 		 * FIXME get rid of this funny new->old swapping  in intel_atomic_commit_tail()
7415 		old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);  in intel_atomic_commit_tail()
7416 		old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);  in intel_atomic_commit_tail()
7423 	if (state->modeset)  in intel_atomic_commit_tail()
7427 	if (state->modeset)  in intel_atomic_commit_tail()
7431 	drm_atomic_helper_commit_hw_done(&state->base);  in intel_atomic_commit_tail()
7434 	if (state->modeset) {  in intel_atomic_commit_tail()
7438 		 * so enable debugging for the next modeset - and hope we catch  in intel_atomic_commit_tail()
7441 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);  in intel_atomic_commit_tail()
7444 	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off  in intel_atomic_commit_tail()
7448 	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit_tail()
7453 	 * are executed inline. For out-of-line asynchronous modesets/flips,  in intel_atomic_commit_tail()
7458 	INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work);  in intel_atomic_commit_tail()
7459 	queue_work(display->wq.cleanup, &state->cleanup_work);  in intel_atomic_commit_tail()
7478 		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),  in intel_atomic_track_fbs()
7479 					to_intel_frontbuffer(new_plane_state->hw.fb),  in intel_atomic_track_fbs()
7480 					plane->frontbuffer_bit);  in intel_atomic_track_fbs()
7487 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);  in intel_atomic_setup_commit()
7502 	ret = drm_atomic_helper_swap_state(&state->base, true);  in intel_atomic_swap_state()
7523 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);  in intel_atomic_commit()
7533 	 * Unset state->legacy_cursor_update before the call to  in intel_atomic_commit()
7542 	if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {  in intel_atomic_commit()
7548 			if (new_crtc_state->wm.need_postvbl_update ||  in intel_atomic_commit()
7549 			    new_crtc_state->update_wm_post)  in intel_atomic_commit()
7550 				state->base.legacy_cursor_update = false;  in intel_atomic_commit()
7555 		drm_dbg_atomic(display->drm,  in intel_atomic_commit()
7557 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
7566 		drm_atomic_helper_unprepare_planes(dev, &state->base);  in intel_atomic_commit()
7567 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
7571 	drm_atomic_state_get(&state->base);  in intel_atomic_commit()
7572 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);  in intel_atomic_commit()
7574 	if (nonblock && state->modeset) {  in intel_atomic_commit()
7575 		queue_work(display->wq.modeset, &state->base.commit_work);  in intel_atomic_commit()
7577 		queue_work(display->wq.flip, &state->base.commit_work);  in intel_atomic_commit()
7579 		if (state->modeset)  in intel_atomic_commit()
7580 			flush_workqueue(display->wq.modeset);  in intel_atomic_commit()
7593 	for_each_intel_encoder(display->drm, source_encoder) {  in intel_encoder_possible_clones()
7595 			possible_clones |= drm_encoder_mask(&source_encoder->base);  in intel_encoder_possible_clones()
7607 	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)  in intel_encoder_possible_crtcs()
7608 		possible_crtcs |= drm_crtc_mask(&crtc->base);  in intel_encoder_possible_crtcs()
7615 	if (!display->platform.mobile)  in ilk_has_edp_a()
7621 	if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))  in ilk_has_edp_a()
7629 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_ddi_crt_present()
7634 	if (display->platform.haswell_ult || display->platform.broadwell_ult)  in intel_ddi_crt_present()
7645 	if (!display->vbt.int_crt_support)  in intel_ddi_crt_present()
7653 	return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),  in assert_port_valid()
7659 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_setup_outputs()
7674 		if (display->platform.geminilake || display->platform.broxton)  in intel_setup_outputs()
7712 	} else if (display->platform.valleyview || display->platform.cherryview) {  in intel_setup_outputs()
7715 		if (display->platform.valleyview && display->vbt.int_crt_support)  in intel_setup_outputs()
7721 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for  in intel_setup_outputs()
7728 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap  in intel_setup_outputs()
7747 		if (display->platform.cherryview) {  in intel_setup_outputs()
7760 	} else if (display->platform.pineview) {  in intel_setup_outputs()
7766 		if (display->platform.mobile)  in intel_setup_outputs()
7772 			drm_dbg_kms(display->drm, "probing SDVOB\n");  in intel_setup_outputs()
7774 			if (!found && display->platform.g4x) {  in intel_setup_outputs()
7775 				drm_dbg_kms(display->drm,  in intel_setup_outputs()
7780 			if (!found && display->platform.g4x)  in intel_setup_outputs()
7787 			drm_dbg_kms(display->drm, "probing SDVOC\n");  in intel_setup_outputs()
7793 			if (display->platform.g4x) {  in intel_setup_outputs()
7794 				drm_dbg_kms(display->drm,  in intel_setup_outputs()
7798 			if (display->platform.g4x)  in intel_setup_outputs()
7802 		if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))  in intel_setup_outputs()
7808 		if (display->platform.i85x)  in intel_setup_outputs()
7815 	for_each_intel_encoder(display->drm, encoder) {  in intel_setup_outputs()
7816 		encoder->base.possible_crtcs =  in intel_setup_outputs()
7818 		encoder->base.possible_clones =  in intel_setup_outputs()
7824 	drm_helper_move_panel_connectors_to_head(display->drm);  in intel_setup_outputs()
7829 	int max_dotclock = display->cdclk.max_dotclk_freq;  in max_dotclock()
7854 	 * reject modes with the DBLSCAN flag in encoder->compute_config().  in intel_mode_valid()
7855 	 * And we always reject DBLSCAN modes in connector->mode_valid()  in intel_mode_valid()
7859 	if (mode->vscan > 1)  in intel_mode_valid()
7862 	if (mode->flags & DRM_MODE_FLAG_HSKEW)  in intel_mode_valid()
7865 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |  in intel_mode_valid()
7870 	if (mode->flags & (DRM_MODE_FLAG_BCAST |  in intel_mode_valid()
7879 	if (mode->clock > max_dotclock(display))  in intel_mode_valid()
7889 		   display->platform.broadwell || display->platform.haswell) {  in intel_mode_valid()
7906 	if (mode->hdisplay > hdisplay_max ||  in intel_mode_valid()
7907 	    mode->hsync_start > htotal_max ||  in intel_mode_valid()
7908 	    mode->hsync_end > htotal_max ||  in intel_mode_valid()
7909 	    mode->htotal > htotal_max)  in intel_mode_valid()
7912 	if (mode->vdisplay > vdisplay_max ||  in intel_mode_valid()
7913 	    mode->vsync_start > vtotal_max ||  in intel_mode_valid()
7914 	    mode->vsync_end > vtotal_max ||  in intel_mode_valid()
7915 	    mode->vtotal > vtotal_max)  in intel_mode_valid()
7926 	 * excluding BXT/GLK DSI transcoders.  in intel_cpu_transcoder_mode_valid()
7929 		if (mode->hdisplay < 64 ||  in intel_cpu_transcoder_mode_valid()
7930 		    mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
7933 		if (mode->vtotal - mode->vdisplay < 5)  in intel_cpu_transcoder_mode_valid()
7936 		if (mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
7939 		if (mode->vtotal - mode->vdisplay < 3)  in intel_cpu_transcoder_mode_valid()
7947 	if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&  in intel_cpu_transcoder_mode_valid()
7948 	    mode->hsync_start == mode->hdisplay)  in intel_cpu_transcoder_mode_valid()
7984 	if (mode->hdisplay > plane_width_max)  in intel_mode_valid_max_plane_size()
7987 	if (mode->vdisplay > plane_height_max)  in intel_mode_valid_max_plane_size()
8039  * intel_init_display_hooks - initialize the display modesetting hooks
8044 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_init_display_hooks()
8047 		display->funcs.display = &skl_display_funcs;  in intel_init_display_hooks()
8049 		display->funcs.display = &ddi_display_funcs;  in intel_init_display_hooks()
8051 		display->funcs.display = &pch_split_display_funcs;  in intel_init_display_hooks()
8052 	} else if (display->platform.cherryview ||  in intel_init_display_hooks()
8053 		   display->platform.valleyview) {  in intel_init_display_hooks()
8054 		display->funcs.display = &vlv_display_funcs;  in intel_init_display_hooks()
8056 		display->funcs.display = &i9xx_display_funcs;  in intel_init_display_hooks()
8067 	state = drm_atomic_state_alloc(display->drm);  in intel_initial_commit()
8069 		return -ENOMEM;  in intel_initial_commit()
8073 	state->acquire_ctx = &ctx;  in intel_initial_commit()
8074 	to_intel_atomic_state(state)->internal = true;  in intel_initial_commit()
8077 	for_each_intel_crtc(display->drm, crtc) {  in intel_initial_commit()
8086 		if (crtc_state->hw.active) {  in intel_initial_commit()
8089 			ret = drm_atomic_add_affected_planes(state, &crtc->base);  in intel_initial_commit()
8099 			crtc_state->uapi.color_mgmt_changed = true;  in intel_initial_commit()
8101 			for_each_intel_encoder_mask(display->drm, encoder,  in intel_initial_commit()
8102 						    crtc_state->uapi.encoder_mask) {  in intel_initial_commit()
8103 				if (encoder->initial_fastset_check &&  in intel_initial_commit()
8104 				    !encoder->initial_fastset_check(encoder, crtc_state)) {  in intel_initial_commit()
8106 										 &crtc->base);  in intel_initial_commit()
8117 	if (ret == -EDEADLK) {  in intel_initial_commit()
8146 	drm_WARN_ON(display->drm,  in i830_enable_pipe()
8149 	drm_dbg_kms(display->drm,  in i830_enable_pipe()
8156 		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |  in i830_enable_pipe()
8162 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));  in i830_enable_pipe()
8164 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));  in i830_enable_pipe()
8166 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));  in i830_enable_pipe()
8168 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));  in i830_enable_pipe()
8170 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));  in i830_enable_pipe()
8172 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));  in i830_enable_pipe()
8174 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));  in i830_enable_pipe()
8216 	drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",  in i830_disable_pipe()
8219 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8221 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8223 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8225 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8227 	drm_WARN_ON(display->drm,  in i830_disable_pipe()
8241 	struct drm_i915_private *i915 = to_i915(display->drm);  in intel_scanout_needs_vtd_wa()