56  * are two main clocks involved that aren't directly related to the actual
57  * pixel clock or any symbol/bit clock of the actual output port. These
559 		 * Specs are full of misinformation, but testing on actual  in vlv_calc_voltage_level()
2578 	if (!intel_cdclk_changed(&old_cdclk_state->actual,  in intel_cdclk_pcode_pre_notify()
2579 				 &new_cdclk_state->actual) &&  in intel_cdclk_pcode_pre_notify()
2587 	change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;  in intel_cdclk_pcode_pre_notify()
2598 		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);  in intel_cdclk_pcode_pre_notify()
2624 	voltage_level = new_cdclk_state->actual.voltage_level;  in intel_cdclk_pcode_post_notify()
2626 	update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;  in intel_cdclk_pcode_post_notify()
2635 		cdclk = new_cdclk_state->actual.cdclk;  in intel_cdclk_pcode_post_notify()
2658 		new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;  in intel_cdclk_is_decreasing_later()
2679 	if (!intel_cdclk_changed(&old_cdclk_state->actual,  in intel_set_cdclk_pre_plane_update()
2680 				 &new_cdclk_state->actual))  in intel_set_cdclk_pre_plane_update()
2687 		cdclk_config = new_cdclk_state->actual;  in intel_set_cdclk_pre_plane_update()
2690 		if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {  in intel_set_cdclk_pre_plane_update()
2691 			cdclk_config = new_cdclk_state->actual;  in intel_set_cdclk_pre_plane_update()
2694 			cdclk_config = old_cdclk_state->actual;  in intel_set_cdclk_pre_plane_update()
2698 		cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,  in intel_set_cdclk_pre_plane_update()
2699 						 old_cdclk_state->actual.voltage_level);  in intel_set_cdclk_pre_plane_update()
2706 	cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;  in intel_set_cdclk_pre_plane_update()
2731 	if (!intel_cdclk_changed(&old_cdclk_state->actual,  in intel_set_cdclk_post_plane_update()
2732 				 &new_cdclk_state->actual))  in intel_set_cdclk_post_plane_update()
2739 	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)  in intel_set_cdclk_post_plane_update()
2746 	intel_set_cdclk(display, &new_cdclk_state->actual, pipe,  in intel_set_cdclk_post_plane_update()
2949 		cdclk_state->actual.cdclk = cdclk;  in vlv_modeset_calc_cdclk()
2950 		cdclk_state->actual.voltage_level =  in vlv_modeset_calc_cdclk()
2953 		cdclk_state->actual = cdclk_state->logical;  in vlv_modeset_calc_cdclk()
2978 		cdclk_state->actual.cdclk = cdclk;  in bdw_modeset_calc_cdclk()
2979 		cdclk_state->actual.voltage_level =  in bdw_modeset_calc_cdclk()
2982 		cdclk_state->actual = cdclk_state->logical;  in bdw_modeset_calc_cdclk()
3048 		cdclk_state->actual.vco = vco;  in skl_modeset_calc_cdclk()
3049 		cdclk_state->actual.cdclk = cdclk;  in skl_modeset_calc_cdclk()
3050 		cdclk_state->actual.voltage_level =  in skl_modeset_calc_cdclk()
3053 		cdclk_state->actual = cdclk_state->logical;  in skl_modeset_calc_cdclk()
3087 		cdclk_state->actual.vco = vco;  in bxt_modeset_calc_cdclk()
3088 		cdclk_state->actual.cdclk = cdclk;  in bxt_modeset_calc_cdclk()
3089 		cdclk_state->actual.voltage_level =  in bxt_modeset_calc_cdclk()
3092 		cdclk_state->actual = cdclk_state->logical;  in bxt_modeset_calc_cdclk()
3105 	 * the actual cdclk frequency.  in fixed_modeset_calc_cdclk()
3195 	cdclk_state->actual.joined_mbus = joined_mbus;  in intel_cdclk_state_set_joined_mbus()
3221 	bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,  in intel_cdclk_need_serialize()
3222 						 &new_cdclk_state->actual);  in intel_cdclk_need_serialize()
3254 		 * if the actual hw needs to be poked.  in intel_modeset_calc_cdclk()
3272 					&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3273 					&new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3289 					     &old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3290 					     &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3294 					&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3295 					&new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3299 					 &old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3300 					 &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3309 	} else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
3310 					     &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3322 	if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) !=  in intel_modeset_calc_cdclk()
3323 	    intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
3324 		int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual);  in intel_modeset_calc_cdclk()
3332 		    "New cdclk calculated to be logical %u kHz, actual %u kHz\n",  in intel_modeset_calc_cdclk()
3334 		    new_cdclk_state->actual.cdclk);  in intel_modeset_calc_cdclk()
3336 		    "New voltage level calculated to be logical %u, actual %u\n",  in intel_modeset_calc_cdclk()
3338 		    new_cdclk_state->actual.voltage_level);  in intel_modeset_calc_cdclk()