Lines Matching +full:dual +full:- +full:dsi +full:- +full:mode
75 drm_err(display->drm, "DSI header credits not released\n"); in wait_for_header_credits()
87 drm_err(display->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
106 struct mipi_dsi_device *dsi; in wait_for_cmds_dispatched_to_panel() local
112 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
119 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
120 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
121 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
122 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
123 ret = mipi_dsi_dcs_nop(dsi); in wait_for_cmds_dispatched_to_panel()
125 drm_err(display->drm, in wait_for_cmds_dispatched_to_panel()
130 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
136 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
140 drm_err(display->drm, "LPTX bit not cleared\n"); in wait_for_cmds_dispatched_to_panel()
147 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_payld()
148 struct intel_display *display = to_intel_display(&intel_dsi->base); in dsi_send_pkt_payld()
149 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_payld()
150 const u8 *data = packet->payload; in dsi_send_pkt_payld()
151 u32 len = packet->payload_length; in dsi_send_pkt_payld()
156 drm_err(display->drm, "payload size exceeds max queue limit\n"); in dsi_send_pkt_payld()
157 return -EINVAL; in dsi_send_pkt_payld()
164 return -EBUSY; in dsi_send_pkt_payld()
166 for (j = 0; j < min_t(u32, len - i, 4); j++) in dsi_send_pkt_payld()
179 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_hdr()
180 struct intel_display *display = to_intel_display(&intel_dsi->base); in dsi_send_pkt_hdr()
181 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_hdr()
185 return -EBUSY; in dsi_send_pkt_hdr()
189 if (packet->payload) in dsi_send_pkt_hdr()
202 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); in dsi_send_pkt_hdr()
203 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); in dsi_send_pkt_hdr()
204 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); in dsi_send_pkt_hdr()
205 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); in dsi_send_pkt_hdr()
217 mode_flags = crtc_state->mode_flags; in icl_dsi_frame_update()
220 * case 1 also covers dual link in icl_dsi_frame_update()
221 * In case of dual link, frame update should be set on in icl_dsi_frame_update()
243 for_each_dsi_phy(phy, intel_dsi->phys) { in dsi_program_swing_and_deemphasis()
245 * Program voltage swing and pre-emphasis level values as per in dsi_program_swing_and_deemphasis()
290 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in configure_dual_link_mode()
292 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); in configure_dual_link_mode()
293 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); in configure_dual_link_mode()
302 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); in configure_dual_link_mode()
304 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in configure_dual_link_mode()
306 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
307 u16 hactive = adjusted_mode->crtc_hdisplay; in configure_dual_link_mode()
311 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; in configure_dual_link_mode()
314 drm_err(display->drm, in configure_dual_link_mode()
329 /* aka DSI 8X clock */
336 if (crtc_state->dsc.compression_enable) in afe_clk()
337 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in afe_clk()
339 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in afe_clk()
341 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); in afe_clk()
356 if (display->platform.alderlake_s || display->platform.alderlake_p) { in gen11_dsi_program_esc_clk_div()
360 esc_clk_div_m_phy = (act_word_clk - 1) / 2; in gen11_dsi_program_esc_clk_div()
365 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
371 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
377 if (display->platform.alderlake_s || display->platform.alderlake_p) { in gen11_dsi_program_esc_clk_div()
378 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
388 struct intel_display *display = to_intel_display(&intel_dsi->base); in get_dsi_io_power_domains()
391 for_each_dsi_port(port, intel_dsi->ports) { in get_dsi_io_power_domains()
392 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); in get_dsi_io_power_domains()
393 intel_dsi->io_wakeref[port] = in get_dsi_io_power_domains()
407 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_enable_io_power()
420 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_power_up_lanes()
422 intel_dsi->lane_count, false); in gen11_dsi_power_up_lanes()
434 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
443 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
452 if (display->platform.jasperlake || display->platform.elkhartlake || in gen11_dsi_config_phy_lanes_sequence()
476 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
488 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_voltage_swing_program_seq()
493 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
500 /* Program swing and de-emphasis */ in gen11_dsi_voltage_swing_program_seq()
504 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
518 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_ddi_buffer()
524 drm_err(display->drm, "DDI port:%c buffer idle\n", in gen11_dsi_enable_ddi_buffer()
539 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
541 intel_dsi->dphy_reg); in gen11_dsi_setup_dphy_timings()
544 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
546 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_dphy_timings()
549 * If DSI link operating at or below an 800 MHz, in gen11_dsi_setup_dphy_timings()
556 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
563 if (display->platform.jasperlake || display->platform.elkhartlake) { in gen11_dsi_setup_dphy_timings()
564 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_setup_dphy_timings()
578 /* Program T-INIT master registers */ in gen11_dsi_setup_timings()
579 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
581 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); in gen11_dsi_setup_timings()
584 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
586 intel_dsi->dphy_reg); in gen11_dsi_setup_timings()
589 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
591 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_timings()
596 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timings()
612 mutex_lock(&display->dpll.lock); in gen11_dsi_gate_clocks()
614 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_gate_clocks()
618 mutex_unlock(&display->dpll.lock); in gen11_dsi_gate_clocks()
628 mutex_lock(&display->dpll.lock); in gen11_dsi_ungate_clocks()
630 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_ungate_clocks()
634 mutex_unlock(&display->dpll.lock); in gen11_dsi_ungate_clocks()
647 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_is_clock_enabled()
660 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()
664 mutex_lock(&display->dpll.lock); in gen11_dsi_map_pll()
667 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
669 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); in gen11_dsi_map_pll()
673 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
680 mutex_unlock(&display->dpll.lock); in gen11_dsi_map_pll()
689 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
690 enum pipe pipe = crtc->pipe; in gen11_dsi_configure_transcoder()
695 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
699 if (intel_dsi->eotp_pkt) in gen11_dsi_configure_transcoder()
712 if (intel_dsi->clock_stop) in gen11_dsi_configure_transcoder()
726 if (intel_dsi->bgr_enabled) in gen11_dsi_configure_transcoder()
731 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
734 switch (intel_dsi->pixel_format) { in gen11_dsi_configure_transcoder()
736 MISSING_CASE(intel_dsi->pixel_format); in gen11_dsi_configure_transcoder()
758 /* program DSI operation mode */ in gen11_dsi_configure_transcoder()
761 switch (intel_dsi->video_mode) { in gen11_dsi_configure_transcoder()
763 MISSING_CASE(intel_dsi->video_mode); in gen11_dsi_configure_transcoder()
775 * As per the spec when dsi transcoder is operating in gen11_dsi_configure_transcoder()
776 * in TE GATE mode, TE comes from GPIO in gen11_dsi_configure_transcoder()
777 * which is UTIL PIN for DSI 0. in gen11_dsi_configure_transcoder()
789 /* enable port sync mode if dual link */ in gen11_dsi_configure_transcoder()
790 if (intel_dsi->dual_link) { in gen11_dsi_configure_transcoder()
791 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
802 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
809 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); in gen11_dsi_configure_transcoder()
838 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
842 drm_err(display->drm, "DSI link not ready\n"); in gen11_dsi_configure_transcoder()
853 &crtc_state->hw.adjusted_mode; in gen11_dsi_set_transcoder_timings()
868 * non-compressed link speeds, and simplifies down to the ratio between in gen11_dsi_set_transcoder_timings()
869 * compressed and non-compressed bpp. in gen11_dsi_set_transcoder_timings()
871 if (crtc_state->dsc.compression_enable) { in gen11_dsi_set_transcoder_timings()
872 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in gen11_dsi_set_transcoder_timings()
873 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
876 hactive = adjusted_mode->crtc_hdisplay; in gen11_dsi_set_transcoder_timings()
879 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_set_transcoder_timings()
883 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_set_transcoder_timings()
884 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_set_transcoder_timings()
885 hsync_size = hsync_end - hsync_start; in gen11_dsi_set_transcoder_timings()
886 hback_porch = (adjusted_mode->crtc_htotal - in gen11_dsi_set_transcoder_timings()
887 adjusted_mode->crtc_hsync_end); in gen11_dsi_set_transcoder_timings()
888 vactive = adjusted_mode->crtc_vdisplay; in gen11_dsi_set_transcoder_timings()
891 vtotal = adjusted_mode->crtc_vtotal; in gen11_dsi_set_transcoder_timings()
895 if (crtc_state->dsc.compression_enable) in gen11_dsi_set_transcoder_timings()
896 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in gen11_dsi_set_transcoder_timings()
898 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
901 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); in gen11_dsi_set_transcoder_timings()
904 vsync_start = adjusted_mode->crtc_vsync_start; in gen11_dsi_set_transcoder_timings()
905 vsync_end = adjusted_mode->crtc_vsync_end; in gen11_dsi_set_transcoder_timings()
906 vsync_shift = hsync_start - htotal / 2; in gen11_dsi_set_transcoder_timings()
908 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
910 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_set_transcoder_timings()
911 hactive += intel_dsi->pixel_overlap; in gen11_dsi_set_transcoder_timings()
916 if (adjusted_mode->crtc_hdisplay < 256) in gen11_dsi_set_transcoder_timings()
917 drm_err(display->drm, "hactive is less then 256 pixels\n"); in gen11_dsi_set_transcoder_timings()
920 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) in gen11_dsi_set_transcoder_timings()
921 drm_err(display->drm, in gen11_dsi_set_transcoder_timings()
925 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
928 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); in gen11_dsi_set_transcoder_timings()
931 /* TRANS_HSYNC register to be programmed only for video mode */ in gen11_dsi_set_transcoder_timings()
933 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { in gen11_dsi_set_transcoder_timings()
936 drm_err(display->drm, in gen11_dsi_set_transcoder_timings()
941 drm_err(display->drm, "hback porch < 16 pixels\n"); in gen11_dsi_set_transcoder_timings()
943 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
948 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
952 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); in gen11_dsi_set_transcoder_timings()
957 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
960 * FIXME: Programming this by assuming progressive mode, since in gen11_dsi_set_transcoder_timings()
961 * non-interlaced info from VBT is not saved inside in gen11_dsi_set_transcoder_timings()
963 * For interlace mode: program required pixel minus 2 in gen11_dsi_set_transcoder_timings()
966 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); in gen11_dsi_set_transcoder_timings()
970 drm_err(display->drm, "Invalid vsync_end value\n"); in gen11_dsi_set_transcoder_timings()
973 drm_err(display->drm, "vsync_start less than vactive\n"); in gen11_dsi_set_transcoder_timings()
975 /* program TRANS_VSYNC register for video mode only */ in gen11_dsi_set_transcoder_timings()
977 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
981 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); in gen11_dsi_set_transcoder_timings()
992 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1007 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1011 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); in gen11_dsi_set_transcoder_timings()
1023 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_transcoder()
1031 drm_err(display->drm, in gen11_dsi_enable_transcoder()
1032 "DSI transcoder not enabled\n"); in gen11_dsi_enable_transcoder()
1054 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, in gen11_dsi_setup_timeouts()
1056 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); in gen11_dsi_setup_timeouts()
1057 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); in gen11_dsi_setup_timeouts()
1059 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timeouts()
1092 * for dual link/DSI1 TE is from slave DSI1 in gen11_dsi_config_util_pin()
1095 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1113 /* step 4a: power up all lanes of the DDI used by DSI */ in gen11_dsi_enable_port_and_phy()
1116 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ in gen11_dsi_enable_port_and_phy()
1122 /* setup D-PHY timings */ in gen11_dsi_enable_port_and_phy()
1135 /* step 4h: setup DSI protocol timeouts */ in gen11_dsi_enable_port_and_phy()
1146 struct mipi_dsi_device *dsi; in gen11_dsi_powerup_panel() local
1153 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_powerup_panel()
1164 dsi = intel_dsi->dsi_hosts[port]->device; in gen11_dsi_powerup_panel()
1165 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); in gen11_dsi_powerup_panel()
1167 drm_err(display->drm, in gen11_dsi_powerup_panel()
1187 msleep(intel_dsi->panel_on_delay); in gen11_dsi_pre_pll_enable()
1193 /* step3: enable DSI PLL */ in gen11_dsi_pre_pll_enable()
1205 /* step4: enable DSI port and DPHY */ in gen11_dsi_pre_enable()
1219 * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1221 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1222 * it set while DSI is enabled on pipe B
1236 * Wa_16012360555:adl-p
1248 for_each_dsi_port(port, intel_dsi->ports) in adlp_set_lp_hs_wakeup_gb()
1261 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_enable()
1264 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); in gen11_dsi_enable()
1266 /* Wa_16012360555:adl-p */ in gen11_dsi_enable()
1269 /* step6d: enable dsi transcoder */ in gen11_dsi_enable()
1288 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_transcoder()
1298 drm_err(display->drm, in gen11_dsi_disable_transcoder()
1299 "DSI trancoder not disabled\n"); in gen11_dsi_disable_transcoder()
1321 /* disable periodic update mode */ in gen11_dsi_deconfigure_trancoder()
1323 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_deconfigure_trancoder()
1328 /* put dsi link in ULPS */ in gen11_dsi_deconfigure_trancoder()
1329 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1339 drm_err(display->drm, "DSI link not in ULPS\n"); in gen11_dsi_deconfigure_trancoder()
1343 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1350 /* disable port sync mode if dual link */ in gen11_dsi_deconfigure_trancoder()
1351 if (intel_dsi->dual_link) { in gen11_dsi_deconfigure_trancoder()
1352 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1368 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_port()
1374 drm_err(display->drm, in gen11_dsi_disable_port()
1387 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_io_power()
1390 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); in gen11_dsi_disable_io_power()
1398 /* set mode to DDI */ in gen11_dsi_disable_io_power()
1399 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_disable_io_power()
1422 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in gen11_dsi_post_disable()
1430 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); in gen11_dsi_post_disable()
1451 msleep(intel_dsi->panel_off_delay); in gen11_dsi_post_disable()
1454 intel_dsi->panel_power_off_time = ktime_get_boottime(); in gen11_dsi_post_disable()
1458 const struct drm_display_mode *mode) in gen11_dsi_mode_valid() argument
1460 struct intel_display *display = to_intel_display(connector->dev); in gen11_dsi_mode_valid()
1463 status = intel_cpu_transcoder_mode_valid(display, mode); in gen11_dsi_mode_valid()
1468 return intel_dsi_mode_valid(connector, mode); in gen11_dsi_mode_valid()
1476 &pipe_config->hw.adjusted_mode; in gen11_dsi_get_timings()
1478 if (pipe_config->dsc.compressed_bpp_x16) { in gen11_dsi_get_timings()
1479 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); in gen11_dsi_get_timings()
1480 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_get_timings()
1482 adjusted_mode->crtc_htotal = in gen11_dsi_get_timings()
1483 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_get_timings()
1484 adjusted_mode->crtc_hsync_start = in gen11_dsi_get_timings()
1485 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_get_timings()
1486 adjusted_mode->crtc_hsync_end = in gen11_dsi_get_timings()
1487 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_get_timings()
1490 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1491 adjusted_mode->crtc_hdisplay *= 2; in gen11_dsi_get_timings()
1492 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_get_timings()
1493 adjusted_mode->crtc_hdisplay -= in gen11_dsi_get_timings()
1494 intel_dsi->pixel_overlap; in gen11_dsi_get_timings()
1495 adjusted_mode->crtc_htotal *= 2; in gen11_dsi_get_timings()
1497 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in gen11_dsi_get_timings()
1498 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in gen11_dsi_get_timings()
1500 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { in gen11_dsi_get_timings()
1501 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1502 adjusted_mode->crtc_hsync_start *= 2; in gen11_dsi_get_timings()
1503 adjusted_mode->crtc_hsync_end *= 2; in gen11_dsi_get_timings()
1506 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in gen11_dsi_get_timings()
1507 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in gen11_dsi_get_timings()
1512 struct intel_display *display = to_intel_display(&intel_dsi->base); in gen11_dsi_is_periodic_cmd_mode()
1516 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1528 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1529 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | in gen11_dsi_get_cmd_mode_config()
1531 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1532 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; in gen11_dsi_get_cmd_mode_config()
1534 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; in gen11_dsi_get_cmd_mode_config()
1540 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_get_config()
1545 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; in gen11_dsi_get_config()
1546 if (intel_dsi->dual_link) in gen11_dsi_get_config()
1547 pipe_config->hw.adjusted_mode.crtc_clock *= 2; in gen11_dsi_get_config()
1550 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in gen11_dsi_get_config()
1551 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1558 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; in gen11_dsi_get_config()
1571 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_sync_state()
1572 pipe = intel_crtc->pipe; in gen11_dsi_sync_state()
1577 drm_dbg_kms(display->drm, in gen11_dsi_sync_state()
1579 encoder->base.base.id, in gen11_dsi_sync_state()
1580 encoder->base.name); in gen11_dsi_sync_state()
1587 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config()
1596 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1597 return -EINVAL; in gen11_dsi_dsc_compute_config()
1600 if (crtc_state->dsc.slice_count > 1) in gen11_dsi_dsc_compute_config()
1601 crtc_state->dsc.num_streams = 2; in gen11_dsi_dsc_compute_config()
1603 crtc_state->dsc.num_streams = 1; in gen11_dsi_dsc_compute_config()
1606 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()
1608 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()
1614 /* DSI specific sanity checks on the common code */ in gen11_dsi_dsc_compute_config()
1615 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()
1616 drm_WARN_ON(display->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()
1617 drm_WARN_ON(display->drm, in gen11_dsi_dsc_compute_config()
1618 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
1619 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()
1620 drm_WARN_ON(display->drm, in gen11_dsi_dsc_compute_config()
1621 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()
1627 crtc_state->dsc.compression_enable = true; in gen11_dsi_dsc_compute_config()
1638 struct intel_connector *intel_connector = intel_dsi->attached_connector; in gen11_dsi_compute_config()
1640 &pipe_config->hw.adjusted_mode; in gen11_dsi_compute_config()
1643 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1644 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1654 adjusted_mode->flags = 0; in gen11_dsi_compute_config()
1656 /* Dual link goes to trancoder DSI'0' */ in gen11_dsi_compute_config()
1657 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
1658 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; in gen11_dsi_compute_config()
1660 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; in gen11_dsi_compute_config()
1662 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in gen11_dsi_compute_config()
1663 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1665 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
1667 pipe_config->clock_set = true; in gen11_dsi_compute_config()
1670 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n"); in gen11_dsi_compute_config()
1672 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; in gen11_dsi_compute_config()
1675 * In case of TE GATE cmd mode, we in gen11_dsi_compute_config()
1677 * dual link is enabled in gen11_dsi_compute_config()
1703 encoder->power_domain); in gen11_dsi_get_hw_state()
1707 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_get_hw_state()
1725 drm_err(display->drm, "Invalid PIPE input\n"); in gen11_dsi_get_hw_state()
1733 intel_display_power_put(display, encoder->power_domain, wakeref); in gen11_dsi_get_hw_state()
1740 if (crtc_state->dsc.compression_enable) { in gen11_dsi_initial_fastset_check()
1741 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); in gen11_dsi_initial_fastset_check()
1742 crtc_state->uapi.mode_changed = true; in gen11_dsi_initial_fastset_check()
1778 struct mipi_dsi_device *dsi) in gen11_dsi_host_attach() argument
1784 struct mipi_dsi_device *dsi) in gen11_dsi_host_detach() argument
1801 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in gen11_dsi_host_transfer()
1805 if (mipi_dsi_packet_format_is_long(msg->type)) { in gen11_dsi_host_transfer()
1839 struct intel_display *display = to_intel_display(&intel_dsi->base); in icl_dphy_param_init()
1840 struct intel_connector *connector = intel_dsi->attached_connector; in icl_dphy_param_init()
1841 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; in icl_dphy_param_init()
1850 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in icl_dphy_param_init()
1851 ths_prepare_ns = max(mipi_config->ths_prepare, in icl_dphy_param_init()
1852 mipi_config->tclk_prepare); in icl_dphy_param_init()
1863 drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n", in icl_dphy_param_init()
1869 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - in icl_dphy_param_init()
1872 drm_dbg_kms(display->drm, in icl_dphy_param_init()
1880 drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n", in icl_dphy_param_init()
1886 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); in icl_dphy_param_init()
1888 drm_dbg_kms(display->drm, in icl_dphy_param_init()
1894 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - in icl_dphy_param_init()
1897 drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n", in icl_dphy_param_init()
1903 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); in icl_dphy_param_init()
1905 drm_dbg_kms(display->drm, in icl_dphy_param_init()
1912 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | in icl_dphy_param_init()
1922 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | in icl_dphy_param_init()
1939 intel_attach_scaling_mode_property(&connector->base); in icl_dsi_add_properties()
1941 drm_connector_set_panel_orientation_with_quirk(&connector->base, in icl_dsi_add_properties()
1943 fixed_mode->hdisplay, in icl_dsi_add_properties()
1944 fixed_mode->vdisplay); in icl_dsi_add_properties()
1970 encoder = &intel_dsi->base; in icl_dsi_init()
1971 intel_dsi->attached_connector = intel_connector; in icl_dsi_init()
1972 connector = &intel_connector->base; in icl_dsi_init()
1974 encoder->devdata = devdata; in icl_dsi_init()
1976 /* register DSI encoder with DRM subsystem */ in icl_dsi_init()
1977 drm_encoder_init(display->drm, &encoder->base, in icl_dsi_init()
1979 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); in icl_dsi_init()
1981 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; in icl_dsi_init()
1982 encoder->pre_enable = gen11_dsi_pre_enable; in icl_dsi_init()
1983 encoder->enable = gen11_dsi_enable; in icl_dsi_init()
1984 encoder->disable = gen11_dsi_disable; in icl_dsi_init()
1985 encoder->post_disable = gen11_dsi_post_disable; in icl_dsi_init()
1986 encoder->port = port; in icl_dsi_init()
1987 encoder->get_config = gen11_dsi_get_config; in icl_dsi_init()
1988 encoder->sync_state = gen11_dsi_sync_state; in icl_dsi_init()
1989 encoder->update_pipe = intel_backlight_update; in icl_dsi_init()
1990 encoder->compute_config = gen11_dsi_compute_config; in icl_dsi_init()
1991 encoder->get_hw_state = gen11_dsi_get_hw_state; in icl_dsi_init()
1992 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; in icl_dsi_init()
1993 encoder->type = INTEL_OUTPUT_DSI; in icl_dsi_init()
1994 encoder->cloneable = 0; in icl_dsi_init()
1995 encoder->pipe_mask = ~0; in icl_dsi_init()
1996 encoder->power_domain = POWER_DOMAIN_PORT_DSI; in icl_dsi_init()
1997 encoder->get_power_domains = gen11_dsi_get_power_domains; in icl_dsi_init()
1998 encoder->disable_clock = gen11_dsi_gate_clocks; in icl_dsi_init()
1999 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; in icl_dsi_init()
2000 encoder->shutdown = intel_dsi_shutdown; in icl_dsi_init()
2002 /* register DSI connector with DRM subsystem */ in icl_dsi_init()
2003 drm_connector_init(display->drm, connector, in icl_dsi_init()
2007 connector->display_info.subpixel_order = SubPixelHorizontalRGB; in icl_dsi_init()
2008 intel_connector->get_hw_state = intel_connector_get_hw_state; in icl_dsi_init()
2013 intel_dsi->panel_power_off_time = ktime_get_boottime(); in icl_dsi_init()
2015 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); in icl_dsi_init()
2017 mutex_lock(&display->drm->mode_config.mutex); in icl_dsi_init()
2019 mutex_unlock(&display->drm->mode_config.mutex); in icl_dsi_init()
2022 drm_err(display->drm, "DSI fixed mode info missing\n"); in icl_dsi_init()
2030 if (intel_connector->panel.vbt.dsi.config->dual_link) in icl_dsi_init()
2031 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
2033 intel_dsi->ports = BIT(port); in icl_dsi_init()
2035 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in icl_dsi_init()
2036 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; in icl_dsi_init()
2038 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in icl_dsi_init()
2039 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; in icl_dsi_init()
2041 for_each_dsi_port(port, intel_dsi->ports) { in icl_dsi_init()
2048 intel_dsi->dsi_hosts[port] = host; in icl_dsi_init()
2052 drm_dbg_kms(display->drm, "no device found\n"); in icl_dsi_init()
2063 drm_encoder_cleanup(&encoder->base); in icl_dsi_init()