1 // SPDX-License-Identifier: GPL-2.0-or-later
11 static void hibmc_dp_set_tu(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)  in hibmc_dp_set_tu()  argument
20 	lane_num = dp->link.cap.lanes;  in hibmc_dp_set_tu()
22 		drm_err(dp->dev, "set tu failed, lane num cannot be 0!\n");  in hibmc_dp_set_tu()
27 	rate_ks = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL;  in hibmc_dp_set_tu()
28 	value = (mode->clock * bpp * 5) / (61 * lane_num * rate_ks);  in hibmc_dp_set_tu()
38 	drm_dbg_dp(dp->dev, "tu value: %u.%u value: %u\n",  in hibmc_dp_set_tu()
47 static void hibmc_dp_set_sst(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)  in hibmc_dp_set_sst()  argument
55 	fclk = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL;  in hibmc_dp_set_sst()
60 	htotal_int = mode->htotal * 9947 / 10000;  in hibmc_dp_set_sst()
61 	htotal_size = htotal_int * fclk / (HIBMC_DP_SYMBOL_PER_FCLK * (mode->clock / 1000));  in hibmc_dp_set_sst()
63 	hblank_int = mode->htotal - mode->hdisplay - mode->hdisplay * 53 / 10000;  in hibmc_dp_set_sst()
65 		      (mode->clock * 10 * HIBMC_DP_SYMBOL_PER_FCLK);  in hibmc_dp_set_sst()
67 	drm_dbg_dp(dp->dev, "h_active %u v_active %u htotal_size %u hblank_size %u",  in hibmc_dp_set_sst()
68 		   mode->hdisplay, mode->vdisplay, htotal_size, hblank_size);  in hibmc_dp_set_sst()
69 	drm_dbg_dp(dp->dev, "flink_clock %u pixel_clock %d", fclk, mode->clock / 1000);  in hibmc_dp_set_sst()
77 static void hibmc_dp_link_cfg(struct hibmc_dp_dev *dp, struct drm_display_mode *mode)  in hibmc_dp_link_cfg()  argument
84 	vblank = mode->vtotal - mode->vdisplay;  in hibmc_dp_link_cfg()
85 	timing_delay = mode->htotal - mode->hsync_start;  in hibmc_dp_link_cfg()
86 	hstart = mode->htotal - mode->hsync_start;  in hibmc_dp_link_cfg()
87 	vstart = mode->vtotal - mode->vsync_start;  in hibmc_dp_link_cfg()
90 				 HIBMC_DP_CFG_TIMING_GEN0_HBLANK, mode->htotal - mode->hdisplay);  in hibmc_dp_link_cfg()
92 				 HIBMC_DP_CFG_TIMING_GEN0_HACTIVE, mode->hdisplay);  in hibmc_dp_link_cfg()
97 				 HIBMC_DP_CFG_TIMING_GEN0_VACTIVE, mode->vdisplay);  in hibmc_dp_link_cfg()
100 				 mode->vsync_start - mode->vdisplay);  in hibmc_dp_link_cfg()
103 				 HIBMC_DP_CFG_STREAM_HACTIVE, mode->hdisplay);  in hibmc_dp_link_cfg()
105 				 HIBMC_DP_CFG_STREAM_HBLANK, mode->htotal - mode->hdisplay);  in hibmc_dp_link_cfg()
108 				 mode->hsync_end - mode->hsync_start);  in hibmc_dp_link_cfg()
111 				 HIBMC_DP_CFG_STREAM_VACTIVE, mode->vdisplay);  in hibmc_dp_link_cfg()
116 				 mode->vsync_start - mode->vdisplay);  in hibmc_dp_link_cfg()
119 				 mode->vsync_end - mode->vsync_start);  in hibmc_dp_link_cfg()
127 				 mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 : 0);  in hibmc_dp_link_cfg()
129 				 mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 : 0);  in hibmc_dp_link_cfg()
132 	writel(HIBMC_DP_MSA1, dp->base + HIBMC_DP_VIDEO_MSA1);  in hibmc_dp_link_cfg()
133 	writel(HIBMC_DP_MSA2, dp->base + HIBMC_DP_VIDEO_MSA2);  in hibmc_dp_link_cfg()
135 	hibmc_dp_set_tu(dp, mode);  in hibmc_dp_link_cfg()
147 	hibmc_dp_set_sst(dp, mode);  in hibmc_dp_link_cfg()
152 	struct drm_device *drm_dev = dp->drm_dev;  in hibmc_dp_hw_init()
155 	dp_dev = devm_kzalloc(drm_dev->dev, sizeof(struct hibmc_dp_dev), GFP_KERNEL);  in hibmc_dp_hw_init()
157 		return -ENOMEM;  in hibmc_dp_hw_init()
159 	mutex_init(&dp_dev->lock);  in hibmc_dp_hw_init()
161 	dp->dp_dev = dp_dev;  in hibmc_dp_hw_init()
163 	dp_dev->dev = drm_dev;  in hibmc_dp_hw_init()
164 	dp_dev->base = dp->mmio + HIBMC_DP_OFFSET;  in hibmc_dp_hw_init()
168 	dp_dev->link.cap.lanes = 0x2;  in hibmc_dp_hw_init()
169 	dp_dev->link.cap.link_rate = DP_LINK_BW_2_7;  in hibmc_dp_hw_init()
172 	writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG);  in hibmc_dp_hw_init()
174 	writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE);  in hibmc_dp_hw_init()
175 	writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS);  in hibmc_dp_hw_init()
177 	writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL);  in hibmc_dp_hw_init()
179 	writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL);  in hibmc_dp_hw_init()
186 	struct hibmc_dp_dev *dp_dev = dp->dp_dev;  in hibmc_dp_display_en()
190 		writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);  in hibmc_dp_display_en()
192 		writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);  in hibmc_dp_display_en()
195 		writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);  in hibmc_dp_display_en()
197 		writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);  in hibmc_dp_display_en()
203 int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode)  in hibmc_dp_mode_set()  argument
205 	struct hibmc_dp_dev *dp_dev = dp->dp_dev;  in hibmc_dp_mode_set()
208 	if (!dp_dev->link.status.channel_equalized) {  in hibmc_dp_mode_set()
211 			drm_err(dp->drm_dev, "dp link training failed, ret: %d\n", ret);  in hibmc_dp_mode_set()
217 	hibmc_dp_link_cfg(dp_dev, mode);  in hibmc_dp_mode_set()