1 // SPDX-License-Identifier: GPL-2.0-only
9  * - Split functions by vbt type
10  * - Make them all take drm_device
11  * - Check ioremap failures
22 	struct pci_dev *pdev = to_pci_dev(dev->dev);  in mid_get_fuse_settings()
24 		pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),  in mid_get_fuse_settings()
48 		dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;  in mid_get_fuse_settings()
51 		 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");  in mid_get_fuse_settings()
54 	 if (dev_priv->iLVDS_enable) {  in mid_get_fuse_settings()
55 		dev_priv->is_lvds_on = true;  in mid_get_fuse_settings()
56 		dev_priv->is_mipi_on = false;  in mid_get_fuse_settings()
58 		dev_priv->is_mipi_on = true;  in mid_get_fuse_settings()
59 		dev_priv->is_lvds_on = false;  in mid_get_fuse_settings()
62 	dev_priv->video_device_fuse = fuse_value;  in mid_get_fuse_settings()
67 	dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);  in mid_get_fuse_settings()
70 	dev_priv->fuse_reg_value = fuse_value;  in mid_get_fuse_settings()
74 		dev_priv->core_freq = 200;  in mid_get_fuse_settings()
77 		dev_priv->core_freq = 100;  in mid_get_fuse_settings()
80 		dev_priv->core_freq = 166;  in mid_get_fuse_settings()
83 		dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",  in mid_get_fuse_settings()
85 		dev_priv->core_freq = 0;  in mid_get_fuse_settings()
87 	dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);  in mid_get_fuse_settings()
97 	struct pci_dev *pdev = to_pci_dev(dev_priv->dev.dev);  in mid_get_pci_revID()
98 	int domain = pci_domain_nr(pdev->bus);  in mid_get_pci_revID()
107 	dev_priv->platform_rev_id = (uint8_t) platform_rev_id;  in mid_get_pci_revID()
109 	dev_dbg(dev_priv->dev.dev, "platform_rev_id is %x\n", dev_priv->platform_rev_id);  in mid_get_pci_revID()
114 	u8 revision;  member
140 		return -1;  in read_vbt_r0()
154 		return -1;  in read_vbt_r10()
170 		return -1;  in mid_get_vbt_data_r0()
172 	gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));  in mid_get_vbt_data_r0()
174 		return -1;  in mid_get_vbt_data_r0()
178 	bpi = gct.PD.BootPanelIndex;  in mid_get_vbt_data_r0()
179 	dev_priv->gct_data.bpi = bpi;  in mid_get_vbt_data_r0()
180 	dev_priv->gct_data.pt = gct.PD.PanelType;  in mid_get_vbt_data_r0()
181 	dev_priv->gct_data.DTD = gct.panel[bpi].DTD;  in mid_get_vbt_data_r0()
182 	dev_priv->gct_data.Panel_Port_Control =  in mid_get_vbt_data_r0()
184 	dev_priv->gct_data.Panel_MIPI_Display_Descriptor =  in mid_get_vbt_data_r0()
198 		return -1;  in mid_get_vbt_data_r1()
200 	gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));  in mid_get_vbt_data_r1()
202 		return -1;  in mid_get_vbt_data_r1()
206 	bpi = gct.PD.BootPanelIndex;  in mid_get_vbt_data_r1()
207 	dev_priv->gct_data.bpi = bpi;  in mid_get_vbt_data_r1()
208 	dev_priv->gct_data.pt = gct.PD.PanelType;  in mid_get_vbt_data_r1()
209 	dev_priv->gct_data.DTD = gct.panel[bpi].DTD;  in mid_get_vbt_data_r1()
210 	dev_priv->gct_data.Panel_Port_Control =  in mid_get_vbt_data_r1()
212 	dev_priv->gct_data.Panel_MIPI_Display_Descriptor =  in mid_get_vbt_data_r1()
223 	struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;  in mid_get_vbt_data_r10()
225 	int ret = -1;  in mid_get_vbt_data_r10()
228 		return -1;  in mid_get_vbt_data_r10()
232 		return -ENOMEM;  in mid_get_vbt_data_r10()
241 	dev_priv->gct_data.bpi = vbt.primary_panel_idx;  in mid_get_vbt_data_r10()
242 	dev_priv->gct_data.Panel_MIPI_Display_Descriptor =  in mid_get_vbt_data_r10()
246 	dp_ti->pixel_clock = ti->pixel_clock;  in mid_get_vbt_data_r10()
247 	dp_ti->hactive_hi = ti->hactive_hi;  in mid_get_vbt_data_r10()
248 	dp_ti->hactive_lo = ti->hactive_lo;  in mid_get_vbt_data_r10()
249 	dp_ti->hblank_hi = ti->hblank_hi;  in mid_get_vbt_data_r10()
250 	dp_ti->hblank_lo = ti->hblank_lo;  in mid_get_vbt_data_r10()
251 	dp_ti->hsync_offset_hi = ti->hsync_offset_hi;  in mid_get_vbt_data_r10()
252 	dp_ti->hsync_offset_lo = ti->hsync_offset_lo;  in mid_get_vbt_data_r10()
253 	dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;  in mid_get_vbt_data_r10()
254 	dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;  in mid_get_vbt_data_r10()
255 	dp_ti->vactive_hi = ti->vactive_hi;  in mid_get_vbt_data_r10()
256 	dp_ti->vactive_lo = ti->vactive_lo;  in mid_get_vbt_data_r10()
257 	dp_ti->vblank_hi = ti->vblank_hi;  in mid_get_vbt_data_r10()
258 	dp_ti->vblank_lo = ti->vblank_lo;  in mid_get_vbt_data_r10()
259 	dp_ti->vsync_offset_hi = ti->vsync_offset_hi;  in mid_get_vbt_data_r10()
260 	dp_ti->vsync_offset_lo = ti->vsync_offset_lo;  in mid_get_vbt_data_r10()
261 	dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;  in mid_get_vbt_data_r10()
262 	dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;  in mid_get_vbt_data_r10()
272 	struct drm_device *dev = &dev_priv->dev;  in mid_get_vbt_data()
273 	struct pci_dev *pdev = to_pci_dev(dev->dev);  in mid_get_vbt_data()
278 		pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),  in mid_get_vbt_data()
280 	int ret = -1;  in mid_get_vbt_data()
291 	dev_dbg(dev->dev, "drm platform config address is %x\n", addr);  in mid_get_vbt_data()
307 	dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);  in mid_get_vbt_data()
309 	switch (vbt_header.revision) {  in mid_get_vbt_data()
320 		dev_err(dev->dev, "Unknown revision of GCT!\n");  in mid_get_vbt_data()
325 		dev_err(dev->dev, "Unable to read GCT!");  in mid_get_vbt_data()
327 		dev_priv->has_gct = true;  in mid_get_vbt_data()