Lines Matching defs:pc
64 struct imx8qxp_pc *pc;
76 static inline u32 imx8qxp_pc_read(struct imx8qxp_pc *pc, unsigned int offset)
78 return readl(pc->base + offset);
82 imx8qxp_pc_write(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
84 writel(value, pc->base + offset);
88 imx8qxp_pc_write_set(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
90 imx8qxp_pc_write(pc, offset + PC_REG_SET, value);
94 imx8qxp_pc_write_clr(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
96 imx8qxp_pc_write(pc, offset + PC_REG_CLR, value);
114 struct imx8qxp_pc *pc = ch->pc;
117 DRM_DEV_ERROR(pc->dev,
133 struct imx8qxp_pc *pc = ch->pc;
137 ret = pm_runtime_get_sync(pc->dev);
139 DRM_DEV_ERROR(pc->dev,
142 ret = clk_prepare_enable(pc->clk_apb);
144 DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
148 imx8qxp_pc_write_clr(pc, PC_CTRL_REG,
152 imx8qxp_pc_write_clr(pc, PC_CTRL_REG,
156 imx8qxp_pc_write_set(pc, PC_CTRL_REG,
160 imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_VSYNC_MASK_ENABLE);
163 val = imx8qxp_pc_read(pc, PC_CTRL_REG);
171 imx8qxp_pc_write(pc, PC_CTRL_REG, val);
174 imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_DISP_BYPASS(ch->stream_id));
176 clk_disable_unprepare(pc->clk_apb);
183 struct imx8qxp_pc *pc = ch->pc;
186 ret = pm_runtime_put(pc->dev);
188 DRM_DEV_ERROR(pc->dev, "failed to put runtime PM: %d\n", ret);
271 struct imx8qxp_pc *pc;
279 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
280 if (!pc)
283 pc->base = devm_platform_ioremap_resource(pdev, 0);
284 if (IS_ERR(pc->base))
285 return PTR_ERR(pc->base);
287 pc->dev = dev;
289 pc->clk_apb = devm_clk_get(dev, "apb");
290 if (IS_ERR(pc->clk_apb)) {
291 ret = PTR_ERR(pc->clk_apb);
297 platform_set_drvdata(pdev, pc);
309 ch = &pc->ch[i];
310 ch->pc = pc;
347 if (i == 1 && pc->ch[0].next_bridge)
348 drm_bridge_remove(&pc->ch[0].bridge);
356 struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
361 ch = &pc->ch[i];
376 struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
379 ret = clk_prepare_enable(pc->clk_apb);
381 DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
385 imx8qxp_pc_write_clr(pc, PC_SW_RESET_REG, PC_FULL_RESET_N);
387 clk_disable_unprepare(pc->clk_apb);
398 struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
401 ret = clk_prepare_enable(pc->clk_apb);
403 DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
409 imx8qxp_pc_write_set(pc, PC_SW_RESET_REG, PC_FULL_RESET_N);
411 clk_disable_unprepare(pc->clk_apb);