Lines Matching defs:atom_vram_module_v11

3388 struct atom_vram_module_v11 {  struct
3390 …int32_t  memory_size;                   // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3391 …2_t  channel_enable;                // bit vector, each bit indicate specific channel enable or not
3392 	uint16_t  mem_voltage;                   // mem_voltage
3393 	uint16_t  vram_module_size;              // Size of atom_vram_module_v9
3394 	uint8_t   ext_memory_id;                 // Current memory module ID
3395 	uint8_t   memory_type;                   // enum of atom_dgpu_vram_type
3396 	uint8_t   channel_num;                   // Number of mem. channels supported in this module
3397 	uint8_t   channel_width;                 // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3398 	uint8_t   density;                       // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3399 	uint8_t   tunningset_id;                 // MC phy registers set per.
3400 	uint16_t  reserved[4];                   // reserved
3401 	uint8_t   vender_rev_id;                 // [7:4] Revision, [3:0] Vendor code
3402 	uint8_t   refreshrate;			 // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3403 	uint8_t   vram_flags;			 // bit0= bankgroup enable
3404 	uint8_t   vram_rsd2;			 // reserved
3405 	uint16_t  gddr6_mr10;                    // gddr6 mode register10 value
3406 	uint16_t  gddr6_mr0;                     // gddr6 mode register0 value
3407 	uint16_t  gddr6_mr1;                     // gddr6 mode register1 value
3408 	uint16_t  gddr6_mr2;                     // gddr6 mode register2 value
3409 	uint16_t  gddr6_mr4;                     // gddr6 mode register4 value
3410 	uint16_t  gddr6_mr7;                     // gddr6 mode register7 value
3411 	uint16_t  gddr6_mr8;                     // gddr6 mode register8 value
3412 	char    dram_pnstring[40];               // part number end with '0'.