Lines Matching +full:loss +full:- +full:of +full:- +full:signal
2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
8 * and/or sell copies of the Software, and to permit persons to whom the
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
59 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
63 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
90 // Sizes defined as multiples of 64KB
112 // for example, 1080p -> 8K is 4.0, or 4000 raw value
120 // for example, 8K -> 1080p is 0.25, or 250 raw value
132 * DOC: color-management-caps
137 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
144 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
160 * struct dpp_color_caps - color pipeline capabilities for display pipe and
165 * just plain 256-entry lookup
174 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
175 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
176 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
196 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
205 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
217 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
378 * The update type is determined at the very beginning of the function based
388 * re-programming however do not affect bandwidth consumption or clock
405 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
527 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
528 INGAME_FAMS_DISABLE, // disable in-game fams
529 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
530 …INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR s…
534 * enum pipe_split_policy - Pipe split strategy supported by DCN
542 * pipe in order to bring the best trade-off between performance and
549 * try any sort of split optimization.
574 DCN_PWR_STATE_UNKNOWN = -1,
589 * struct dc_clocks - DC pipe clocks
613 * Elements below are not compared for the purposes of
636 int bw_dppclk_khz; /*a copy of dppclk_khz*/
662 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
663 dm_get_timestamp(dc->ctx) : 0
666 if (dc->debug.bw_val_profile.enable) \
667 dc->debug.bw_val_profile.total_count++
670 if (dc->debug.bw_val_profile.enable) { \
672 voltage_level_tick = dm_get_timestamp(dc->ctx); \
673 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
677 if (dc->debug.bw_val_profile.enable) \
678 voltage_level_tick = dm_get_timestamp(dc->ctx)
681 if (dc->debug.bw_val_profile.enable) \
682 watermark_tick = dm_get_timestamp(dc->ctx)
685 if (dc->debug.bw_val_profile.enable) { \
686 end_tick = dm_get_timestamp(dc->ctx); \
687 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
688 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
690 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
691 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
729 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */
796 * 15-2: reserved
797 * 31-16: timeout in ms
870 * struct dc_debug_options - DC debug struct
980 /* TODO - remove once tested */
1091 /* Generic structure that can be used to query properties of DC. More fields
1124 * of the real VBIOS. Intended use is Diagnostics on FPGA.
1138 * IP offset for run time initializaion of register addresses
1159 /* Returns the number of vmids supported */
1173 /* display chromaticities and white point in units of 0.00001 */
1238 uint32_t rmu_mux_num:3; /*index of mux to use*/
1239 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1409 /* used to temporarily backup plane states of a stream during
1488 …bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first…
1536 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)
1568 * struct dc_validation_set - Struct to store surface/stream associations for validation
1582 * @plane_count: Total of active planes
1628 * The streams parameter is an absolute set of all active streams.
1647 * return - minimum required timing bandwidth in kbps.
1656 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1685 bool hpd_status; /* HPD status of link without physical HPD pin. */
1690 * which expects the same link settings to be used every retry on a link loss.
1691 * This flag is used to skip the fallback when link loss occurs during automation.
1709 * management of the override pointers.
1729 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1733 * pending_test_pattern will be invalid or contain a non-PHY test pattern
1821 * Use dc_get_caps() to get number of links.
1825 /* Return instance id of the edp link. Inst 0 is primary edp link. */
1830 /* Return an array of link pointers to edp links. */
1849 * @reason - Indicate which event triggers this detection. dc may customize
1851 * return false - if detection is not fully completed. This could happen when
1854 * link->connection_type == dc_connection_mst_branch when returning false).
1855 * return true - detection is completed, link has been fully updated with latest
1867 * @dc_link - link the remote sink will be added to.
1868 * @edid - byte array of EDID raw data.
1869 * @len - size of the edid in byte
1870 * @init_data -
1879 * @link - link the sink should be removed from
1880 * @sink - sink to be removed.
1894 * @type - dc_connection_single if connected, dc_connection_none otherwise.
1895 * return - false if an unexpected error occurs, true otherwise.
1899 * return dc_connection_single if the branch device is connected despite of
1906 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1916 * @link - The link the HPD pin is associated with.
1917 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1924 * @enable = false - disable hardware HPD filter. HPD event will be queued
1931 * @link_index - index to a link with ddc in i2c mode
1932 * @cmd - i2c command structure
1933 * return - true if success, false otherwise.
1941 * @link_index - index to a link with ddc in i2c mode
1942 * @cmd - i2c command structure
1943 * return - true if success, false otherwise.
1951 * retries or handle error states. The reply is returned in the payload->reply
1952 * and the result through operation_result. Returns the number of bytes
1953 * transferred,or -1 on a failure.
1968 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1969 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1973 * TODO - When defer_handling is true the function will have a different purpose.
1978 * true - Downstream port status changed. DM should call DC to do the
1980 * false - no change in Downstream port status. No further action required
1989 /* handle DP Link loss sequence and try to recover RX link loss with best
1995 * return true - hpd rx irq should be handled.
1996 * return false - it is safe to ignore hpd rx irq event
2000 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
2001 * @link - link the hpd irq data associated with
2002 * @hpd_irq_dpcd_data - input hpd irq data
2003 * return - true if hpd irq data indicates a link lost
2009 * @link - link where the hpd irq data should be read from
2010 * @irq_data - output hpd irq data
2011 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
2021 * TODO - in the future we should consider to expand link resume interface to
2027 /* Destruct the mst topology of the link and reset the allocated payload table
2036 * return - total effective link bandwidth in kbps.
2049 /* The function calculates the minimum size of hblank (in bytes) needed to
2054 * return - min hblank size in bytes, 0 if 8b/10b SST.
2060 /* The function takes a snapshot of current link resource allocation state
2061 * @dc: pointer to dc of the dm calling this
2064 * DM needs to capture a snapshot of current link resource allocation mapping
2067 * Some of the link resource is using first come first serve policy.
2077 * @dc: pointer to dc of the dm calling this
2084 * Some of the link resource is using first come first serve policy.
2094 * interface i.e stream_update->dsc_config
2102 * @link - current detected link
2103 * @req_bw - requested bandwidth in kbps
2104 * @link_settings - returned most optimal link settings that can fit the
2106 * return - false if link can't support requested bandwidth, true if link
2122 * @link - a link with DP RX connection
2123 * return - if stream is committed to this link with MST signal type, type of
2132 * @link - a link with DP RX connection
2133 * return - max dp link settings the link can enable.
2141 * @link - a link with DP RX connection
2142 * return - highest encoding format link supports.
2147 * to a link with dp connector signal type.
2148 * @link - a link with dp connector signal type
2149 * return - true if connected, false otherwise
2153 /* Force DP lane settings update to main-link video signal and notify the change
2154 * to DP RX via DPCD. This is a debug interface used for video signal integrity
2156 * signal.
2158 * @lt_settings - a container structure with desired hw_lane_settings
2165 * test or debugging purpose. The test pattern will remain until next un-plug.
2167 * @link - active link with DP signal output enabled.
2168 * @test_pattern - desired test pattern to output.
2170 * @test_pattern_color_space - for video test pattern choose a desired color
2172 * @p_link_settings - For PHY pattern choose a desired link settings
2173 * @p_custom_pattern - some test pattern will require a custom input to
2175 * @cust_pattern_size - size of the custom pattern input.
2200 * @link_settings - if not NULL, force preferred link settings to the link.
2201 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2213 /* return - true if FEC is supported with connected DP RX, false otherwise */
2218 * return - true if FEC should be enabled, false otherwise.
2229 * NOTE: this interface doesn't update dp main-link. Calling this function will
2230 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2233 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2238 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2239 * current value read from extended receiver cap from 02200h - 0220Fh.
2240 * Some DP RX has problems of providing accurate DP receiver caps from extended
2249 /* Set backlight level of an embedded panel (eDP, LVDS).
2256 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2302 * return - true if trace is initialized and has valid data. False dp trace
2323 * @in_detection - true to get link training end time stamp of last link
2325 * of last link training in commit (dpms) sequence
2331 * @in_detection - true to get link training count of last link
2332 * training in detection sequence. false to get link training count of last link
2338 /* Get how many link loss has happened since last link training attempts */
2345 * Send a request from DP-Tx requesting to allocate BW remotely after
2359 * Unplug => de-allocate bw
2369 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2374 * @count: number of valid DPIA streams
2381 /* Sink Interfaces - A sink corresponds to a display output device */
2386 // 8 byte port ID -> ELD.PortID
2388 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2390 // 2 byte product code -> ELD.ProductCode
2396 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2406 …// 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST t…
2499 enum signal_type signal,