Lines Matching full:v0
424 // Save v0 by itself since it requires only two SGPRs.
429 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] V_COHERENCE
430 v_mov_b32 v0, 0x0
447 v_writelane_b32 v0, ttmp4, 0x4
448 v_writelane_b32 v0, ttmp5, 0x5
449 v_writelane_b32 v0, ttmp6, 0x6
450 v_writelane_b32 v0, ttmp7, 0x7
451 v_writelane_b32 v0, ttmp8, 0x8
452 v_writelane_b32 v0, ttmp9, 0x9
453 v_writelane_b32 v0, ttmp10, 0xA
454 v_writelane_b32 v0, ttmp11, 0xB
455 v_writelane_b32 v0, ttmp13, 0xD
456 v_writelane_b32 v0, exec_lo, 0xE
457 v_writelane_b32 v0, exec_hi, 0xF
461 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 V_COHERENCE
462 v_readlane_b32 ttmp14, v0, 0xE
463 v_readlane_b32 ttmp15, v0, 0xF
511 write_vgprs_to_mem_with_sqc_w32(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
518 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
520 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128
521 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*2
522 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*3
534 write_vgprs_to_mem_with_sqc_w64(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
541 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
543 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256
544 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*2
545 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*3
559 v_mov_b32 v0, 0x0 //Offset[31:0] from buffer resource
592 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
635 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
656 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
699 //load 0~63*4(byte address) to vgpr v0
700 v_mbcnt_lo_u32_b32 v0, -1, 0
701 v_mbcnt_hi_u32_b32 v0, -1, v0
702 v_mul_u32_u24 v0, 4, v0
716 ds_read_b32 v1, v0
722 v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes
736 ds_read_b32 v1, v0
738 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
742 v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes
754 ds_read_b32 v1, v0
760 v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes
774 ds_read_b32 v1, v0
776 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
780 v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes
823 v_movrels_b32 v0, v0 //v0 = v[0+m0]
828 write_vgprs_to_mem_with_sqc_w32(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
838 v_movrels_b32 v0, v0 //v0 = v[0+m0]
843 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
844 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128
845 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*2
846 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:128*3
868 v_movrels_b32 v0, v0 //v0 = v[0+m0]
873 write_vgprs_to_mem_with_sqc_w64(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
883 v_movrels_b32 v0, v0 //v0 = v[0+m0]
888 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
889 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256
890 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*2
891 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE offset:256*3
915 v_movrels_b32 v0, v0
917 write_vgprs_to_mem_with_sqc_w64(v0, 1, s_save_buf_rsrc0, s_save_mem_offset)
927 v_movrels_b32 v0, v0 //v0 = v[0+m0]
928 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset V_COHERENCE
987 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW
989 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset
991 ds_store_addtid_b32 v0
1001 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW
1003 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset
1005 ds_store_addtid_b32 v0
1038 …s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be th…
1045 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE
1046 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128
1047 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128*2
1048 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:128*3
1050 v_movreld_b32 v0, v0 //v[0+m0] = v0
1057 s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete?
1059 /* VGPR restore on v0 */
1060 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE
1061 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128
1062 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128*2
1063 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:128*3
1072 …s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be th…
1079 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE
1080 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256
1081 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256*2
1082 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE offset:256*3
1084 v_movreld_b32 v0, v0 //v[0+m0] = v0
1091 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete?
1105 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset V_COHERENCE
1107 v_movreld_b32 v0, v0 //v[0+m0] = v0
1111 s_cbranch_scc1 L_RESTORE_SHARED_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete?
1113 s_mov_b32 exec_hi, 0xFFFFFFFF //restore back exec_hi before restoring V0!!
1115 /* VGPR restore on v0 */
1117 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE
1118 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256
1119 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256*2
1120 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save V_COHERENCE offset:256*3